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ICS580-01
Glitch-Free Clock Multiplexer
Description
The ICS580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can also be configured to switch automatically if one of the input clocks stops. The part also provides clock detection by reporting when an input clock has stopped. For a clock mux with zero delay and smooth switching, see either the ICS581-01 or the ICS581-02.
Features
* * * * * * * * * *
16-pin SOIC package Available in Pb (lead) free package No short pulses or glitches on output Operates from 2 to 220 MHz Low skew outputs Clock detect feature Ideal for systems with back-up or redundant clocks Selectable timeouts for clock detection Separate supply voltages allow power supply voltage translation Operates from 2.5 V to 5 V
Block Diagram
VDDC VDDI
INB
CLK1 1 OE1
INA
0
CLK2
SELB Transition Detector
OE2 NO_INA OE3
Transition Detector OE4 DIV Timer
NO_INB
GND
MDS 580-01 D
1
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Pin Assignment
SELB DIV VDDI INA INB GND OE4 OE3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OE1 VDDC CLK1 CLK2 NO_INA NO_INB GND OE2
Timeout Selection
DIV 0 1 Nominal Timeout 600 ns 75 ns
16 pin (150 mil) SOIC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
SELB DIV VDDI INA INB GND OE4 OE3 OE2 GND NO_INB NO_INA CLK2 CLK1 VDDC OE1
Pin Type
Input Input Power Input Input Power Input Input Input Power Output Output Output Output Power Input
Pin Description
Mux select. Selects INB when high. Internal pull-up. Time out select. See table above. Internal pull-up. Supply for input clocks only. Can be higher than VDDC. Input Clock A. Input Clock B. Connect to ground. Output enable. Tri-states NO_INB when low. Internal pull-up. Output enable. Tri-states NO_INA when low. Internal pull-up. Output enable. Tri-states CLK2 when low. Internal pull-up. Connect to ground. Goes high when clock on INB stops. Goes high when clock on INA stops. Clock 2 output. Low skew compared to CLK1. Clock 1 output. Low skew compared to CLK2. Main chip supply. Output clocks amplitude will match this VDD. Output enable. Tri-states CLK1 when low. Internal pull-up.
MDS 580-01 D
2
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Device Operation
The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to switch between two clocks, whether running or not. In the first example, clocks are running on both INA and INB. When SELB changes, the output clock goes low after three cycles of the output clock (nominally). The output then stays low for three cycles of the new input clock (nominally) and then starts with the new input clock. This is shown in Figure 1.
Figure 1
INA INB SELB CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low). This is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the DIV input in. The SELB pin is now changed to select the new input clock which is running. The output clock immediately goes low and stays low for three cycles of the new input clock and then starts with the new input clock. Figure 2 shows an example of this
Figure 2
INA INB SELB
Timeout
NO_INA CLK1, 2
MDS 580-01 D
3
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Application Example
In the third example, the ICS580-01 is configured to automatically switch clocks when an input stops. The clock that could stop is connected to INA while the backup clock (always running) is connected to INB. The output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA goes high selecting the clock on INB which is muxed to the output after three cycles. When the clock on INA restarts, NO_INA immediately goes low, selecting the clock on INA. The output then switches in the manner described in the first example. The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are unused and are disabled by grounding OE2 and OE4. A 33 series termination resistor is used on the clock output and two decoupling capacitors of 0.01F are used. All other inputs are left floating and are therefore pulled high by the on-chip pull-ups.
VDD
SELB DIV
0.01F
OE1 VDDC CLK1 CLK2 NO_INA NO_INB GND OE2
33
0.01F
VDDI INA INB GND OE4 OE3
Output Clock
Normal Clock Backup Clock
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01F decoupling capacitors, one between VDDI and GND and one between VDDC and GND. Series termination resistors of 33 can be used on CLK1 and CLK2.
MDS 580-01 D
4
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Split Power Supplies
The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the rest of the chip are connected to VDDC. This allows for supply voltage translation. For example, INA and INB could be 5V clocks (VDDI = 5V) and the rest of the chip could use a 3.3V supply on VDDC giving 3.3V output clocks. For correct operation VDDI must always be greater than or equal to VDDC.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS580-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -40 to +85C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 -40 +2.5
Typ.
Max.
+70 +85 +5.5
Units
C C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Input High Voltage
Symbol
VDDC VDDI IDD VIH VIL VIH
Conditions
Min.
2.5 VDDC
Typ.
Max.
5.5 5.5
Units
V V mA V V V
50 MHz, no load Non-clock inputs Non-clock inputs INA and INB only Note 3 (VDDC/2)+1 2
6 VDDC 0.8 VDDC/2 VDDI
MDS 580-01 D
5
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Parameter
Input Low Voltage Input Capacitance Output High Voltage Output Low Voltage Short Circuit Current On-chip pull-up Resistor
Symbol
VIL CIN VOH VOL IOS RPU
Conditions
INA and INB only Note 3 IOH = -12 mA IOL = 12 mA
Min.
Typ.
VDDC/2 4
Max.
(VDDC/2)-1
Units
V pF V
VDDC-0.5 0.5 70
V mA k
Non-clock inputs Pull-up to VDDC
250
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C
Parameter
Input Frequency INA and INB, Note 1
Symbol
fIN
Conditions
VDDC = 5V VDDC = 3.3V VDDC = 2.7V VDDC = 5V
Min.
1/timeout 1/timeout 1/timeout
Typ.
Max.
270 220 180
Units
MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ps
4 5 6 175 500 750 20 55 100 350 1000 1500 40 110 200
8 10 12 750 2000 3000 80 210 400 1.5 1.5
Propagation Delay INA or INB to output
VDDC = 3.3V VDDC = 2.7V VDDI = 5V
Transition Detector Timeout, DIV = 0
VDDI = 3.3V VDDI = 2.7V VDDI = 5V
Transition Detector Timeout, DIV = 1 Output Clock Rise Time Output Clock Fall Time Output Clock Skew
VDDI = 3.3V VDDI = 2.7V
CLK1 to CLK2 Note 2
-250
0
250
Note 1. Frequencies less than the minimum may cause a timeout which will not guarantee glitch-free switching unless the clock is actually stopped. Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2. Note 3: Output duty cycle is set by duty cycle of input clock at VDDC/2.
MDS 580-01 D
6
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 115 105 58
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram (ICS580M-01)
16 9
Marking Diagram (ICS580M-01LF)
16 9
ICS580M-01 ###### YYWW
1 8
1
580M01LF ###### YYWW
8
Marking Diagram (ICS580M-01I)
16 9
Marking Diagram (ICS580M-01ILF)
16 9
ICS580M-01I ###### YYWW
1
Notes: 1. ###### is the lot number.
580M01ILF ###### YYWW
1 8
8
2. YYWW is the last two digits of the year and week that the part was assembled. 3. "LF" denotes Pb (lead) free package.
MDS 580-01 D
7
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS580-01 Glitch-Free Clock Multiplexer
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol
E INDEX AREA H
Inches Min Max
Min
Max
12 D
A A1 B C D E e H h L
h x 45
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS580M-01 ICS580M-01T ICS580M-01LF ICS580M-01LFT ICS580M-01I ICS580M-01IT ICS580M-01ILF ICS580M-01ILFT see page 7
Marking
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 580-01 D
8
Revision 021605
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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