View ICS8533-11_986864.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 4 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or crystal inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 650MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 2ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8533-11 is a low skew, high performance ICS 1-to-4 Crystal Oscillator/Differential-to-3.3V HiPerClockSTM LVPECL fanout buffer and a member of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS8533-11 has selectable differential clock or crystal inputs. The CLK, nCLK pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8533-11 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK XTAL1 XTAL2 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nCLK XTAL1 XTAL2 nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
ICS8533-11
20-Lead TSSOP 6.5mm x 4.4mm x 0.92 package body G Package Top View
8533AG-11
www.icst.com/products/hiperclocks.html
1
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Name VEE CLK_EN CLK_SEL CLK nCLK XTAL1 XTAL2 nc VCC nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Input Input Input Unused Power Output Output Output Output Type Description
Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. Pullup LVCMOS / LVTTL interface levels. Clock select input. When LOW, selects CLK, nCLK input. Pulldown When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Cr ystal oscillator input. No connect. Positive supply pins. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Pulldown Cr ystal oscillator input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
8533AG-11
www.icst.com/products/hiperclocks.html
2
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK XTAL1, XTAL2 CLK, nCLK Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 XTAL1, XTAL2 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or crystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described in Table 3B.
nCLK CLK
Disabled
Enabled
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8533AG-11
www.icst.com/products/hiperclocks.html
3
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN CLK_SEL CLK_EN CLK_SEL Test Conditions Minimum 2 -0.3 VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 Typical Maximum VCC + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
8533AG-11
www.icst.com/products/hiperclocks.html
4
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 14 Test Conditions Minimum Typical Maximum 25 50 7 Units MHz pF
Fundamental
TABLE 6. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise/Fall Time 20% to 80% @ 50MHz 300 650MHz 1.0 Test Conditions Minimum Typical Maximum 650 2.0 30 150 700 53 Units MHz ns ps ps ps %
t sk(o) t sk(pp)
tR / tF
o dc Output Duty Cycle; NOTE 4 47 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Measured using CLK. For XTAL input, refer to Application Note. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8533AG-11
www.icst.com/products/hiperclocks.html
5
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
SCOPE
VCC
nCLK
LVPECL
V VEE
nQx
CLK
PP
Cross Points
V
CMR
-1.3V 0.165V
V EE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nCLK
CLK nQ0:nQ3 Q0:Q3
tsk(o)
tPD
OUTPUT SKEW
PROPAGATION DELAY
nQ0:nQ3 Q0:Q3
Pulse Width t
PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8533AG-11
OUTPUT RISE/FALL TIME
www.icst.com/products/hiperclocks.html
6
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
8533AG-11
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. E DECEMBER 14, 2004
www.icst.com/products/hiperclocks.html
7
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8533AG-11
BY
www.icst.com/products/hiperclocks.html
8
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
be located as close as possible to the XTAL1 and XTAL2 pins. The experiments show that using a 19.44MHz crystal results in an output frequency of 19.4404746MHz and approximately 44% of duty cycle.
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode operation. The ICS8533-11 fanout buffer has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components as shown in Figure 5. The physical location of the crystal should
XTAL2
C2 SPARE
X1 Cry stal
XTAL1
C1 40p
FIGURE 5. CRYSTAL INPUT INTERFACE
SCHEMATIC EXAMPLE
Figure 6 shows a schematic example of the ICS8533-11. In this example, the XTAL input is selected. The decoupling capacitors
should be physically located near the power pin. For ICS8533-11, the unused clock outputs can be left floating.
Zo = 50
+
3.3V
Zo = 50
R2 50
R1 50
R11 1K
R12 1K
U1
40p - 60pF C4
X1
3.3V
1 2 3 4 5 6 7 8 9 10
C5 SPARE
C1 0.1u
VEE CLK_EN CLK_SEL CLK nCLK XTAL1 XTAL2 NC NC VCC
Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
20 19 18 17 16 15 14 13 12 11
R3 50
3.3V
3.3V
ICS8533-11
Zo = 50
+
3.3V
Zo = 50
C2 0.1u
C3 0.1u
R8 50
R7 50
R9 50
FIGURE 6. ICS8533-11 LVPECL BUFFER SCHEMATIC EXAMPLE
8533AG-11
www.icst.com/products/hiperclocks.html
9
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-11. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.294W * 66.6C/W = 89.58C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8533AG-11
www.icst.com/products/hiperclocks.html
10
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8533AG-11
www.icst.com/products/hiperclocks.html
11
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-11 is: 428
8533AG-11
www.icst.com/products/hiperclocks.html
12
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MS-153
8533AG-11
www.icst.com/products/hiperclocks.html
13
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking ICS8533AG-11 ICS8533AG-11 ICS8533AG11L ICS8533AG11L Package 20 Lead TSSOP 20 Lead TSSOP on Tape and Reel 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8533AG-11 ICS8533AG-11T ICS8533AG-11LF ICS8533AG-11LFT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8533AG-11
www.icst.com/products/hiperclocks.html
14
REV. E DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev D D D D D D
Table
Page 3 3 8-10
Description of Change Revised Figure 1, CLK_EN Timing Diagram. Revised Figure 1, CLK_EN Timing Diagram. Deleted Cr ystal Oscillator Circuit Frequency Fine Tuning section from datasheet. Shor tened Cr ystal Characteristics table. ESR row, values have changed from 50 Min, 80 Max. to 70 Max. Added Termination for LVPECL Outputs section. Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V 0.165V from VEE = -1.3V 0.135V. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Absolute Maximum Ratings - revised Output rating. LVCMOS DC Characteristics Table - changed VIH max. from 3.765V to VCC + 0.3V. LVPECL DC CHaracteristics Table - changed VSWING max. from 0.85V to 1.0V. Cr ystal Characteristics Table - changed ESR from 70 max. to 50 max. AC Characteristics Table - deleted oscTOL row from table. Updated Single Ended Signal Driving Differential Input Diagram. Updated LVPECL Output Termination Diagrams. Added Differential Clock Input Interface section. Added Cr ystal section. Added Schematic Example. Features Section - added Lead-Free bullet. Ordering Information Table - added "Lead-Free" par t number.
Date 10/18/01 11/2/01 12/11/01 1/11/02 5/28/02 10/3/02
T5
5 8 6
T2 T4B T4D T5
2 4 4 5 5 5 7 7 8 9 9 1 14
E
10/30/03
E
T10
12/14/04
8533AG-11
www.icst.com/products/hiperclocks.html
15
REV. E DECEMBER 14, 2004

▲Up To Search▲

Price & Availability of ICS8533-11

	To Download ICS8533-11 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .