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Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
FEATURES
* Dual /2, /4 differential 3.3V LVPECL outputs; Dual /4, /5, /6 differential 3.3V LVPECL outputs * One differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum clock input frequency: 1GHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Output skew: 35ps (maximum) * Part-to-part skew: 385ps (maximum) * Bank skew: Bank A - 20ps (maximum) Bank B - 20ps (maximum) * Propagation delay: 2.1ns (maximum) * LVPECL mode operating voltage supply range: VCC = 3V to 3.6V, VEE = 0V * Lead-Free package fully RoHS compliant
ICS87339I-11
GENERAL DESCRIPTION
The ICS87339I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock GenHiPerClockSTM erator/Divider and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87339I-11 has one differential clock input pair. The CLK, nCLK pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS87339I-11 ideal for clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
DIV_SELA QA0 nQA0 nCLK_EN D Q LE CLK nCLK QB0 nQB0
/4, /5, /6 /2, /4
PIN ASSIGNMENT
VCC nCLK_EN DIV_SELB0 CLK nCLK RESERVED MR VCC DIV_SELB1 DIV_SELA 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 VEE
R
QA1 nQA1
ICS87339I-11
20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View 20-Lead SOIC, 300MIL 7.5mm x 12.8mm x 2.25mm package body M Package Top View
R MR DIV_SELB0 DIV_SELB1
QB1 nQB1
87339AGI-11
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1
REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
Type Description Positive supply pins. Pulldown Clock enable. LVCMOS / LVTTL interface levels. See Table 3. Selects divide value for Bank B outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup
ICS87339I-11
TABLE 1. PIN DESCRIPTIONS
Number 1, 8, 20 2 3 4 5 6 Name VCC nCLK_EN DIV_SELB0 CLK nCLK RESERVED Power Input Input Input Input Reser ve
Inver ting differential clock input. Reserve pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go 7 MR Input Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divide value for Bank B outputs as described in Table 3. 9 DIV_SELB1 Input Pulldown LVCMOS / LVTTL interface levels. Selects divide value for Bank A outputs as described in Table 3. 10 DIV_SELA Input Pulldown LVCMOS / LVTTL interface levels. Power Negative supply pin. 11 VEE 12, 13 nQB1, QB1 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output 18, 19 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
Outputs DIV_SELB1 X X 0 1 0 1 0 1 0 1 QA0, QA1 LOW Not Switching /2 /2 /2 /2 /4 /4 /4 /4 nQA0, nQA1 HIGH Not Switching /2 /2 /2 /2 /4 /4 /4 /4 QB0, QB1 LOW Not Switching /4 /5 /6 /5 /4 /5 /6 /5 nQB0, nQB1 HIGH Not Switching /4 /5 /6 /5 /4 /5 /6 /5 X X 0 0 1 1 0 0 1 1
ICS87339I-11
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 0 0 0 0 0 0 nCLK_EN X 1 0 0 0 0 0 0 0 0 DIV_SELA X X 0 0 0 0 1 1 1 1 DIV_SELB0
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
CLK
tRR
MR
Q (/n)
FIGURE 1A. MR TIMING DIAGRAM
Disabled
CLK nCLK
Enabled
nCLK_EN
QAx, QBx nQAx, nQBx
FIGURE 1B. NCLK_EN TIMING DIAGRAM
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 73.2C/W (0 lfpm) 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87339I-11
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA 20 Lead TSSOP 20 Lead SOIC Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 105 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current nCLK_EN, MR, DIV_SELA, DIV_SELBx nCLK_EN, MR, DIV_SELA, DIV_SELBx VIN = VCC = 3.6V VIN = 0V, VCC = 3.6V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VCC = 3.6V VIN = VCC = 3.6V VIN = 0V, VCC = 3.6V VIN = 0V, VCC = 3.6V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
ICS87339I-11
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fCLK tPD Clock Input Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Bank Skew; NOTE 3, 5 Bank A Bank B nCLK_EN to CLK CLK to nCLK_EN CLK 20% to 80% 350 100 400 550 100 600 52 CLK to Q (Diff) 1. 6 15 10 10 Test Conditions Minimum Typical Maximum 1 2.1 35 20 20 385 Units GHz ns ps ps ps ps ps ps ps ps ps %
t sk(o) t sk(b) t sk(pp)
tS tH t RR tPW tR / tF
Par t-to-Par t Skew; NOTE 4, 5 Setup Time Hold Time Reset Recover y Time Minimum Pulse Width Output Rise/Fall Time
odc Output Duty Cycle 48 All data taken with outputs /4. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points NOTE 3: Defined as skew within a bank of outputs and with equal load conditions. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS87339I-11
PARAMETER MEASUREMENT INFORMATION
2V V CC
VCC, VCCO
Qx
SCOPE
nCLK V
PP
LVPECL
nQx
Cross Points
V
CMR
CLK
VEE VEE
-1.3V 0.3V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nQAx 80% QAx nQBx QBx Clock Outputs 20% tR tF 80% VSW I N G 20%
tsk(b)
BANK SKEW
nCLK CLK nQAx, nQBx QAx, QBx
OUTPUT RISE/FALL TIME
nQAx, nQBx QAx, QBx
Pulse Width t
PERIOD
t
PD
odc =
t PW t PERIOD
PROPAGATION DELAY
87339AGI-11
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
ICS87339I-11
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 3A. LVPECL OUTPUT TERMINATION
87339AGI-11
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. A APRIL 12, 2005
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Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
ICS87339I-11
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
87339AGI-11
BY
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
ICS87339I-11
This section provides information on power dissipation and junction temperature for the ICS87339I-11. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87339I-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 105mA = 378mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.6V, with all outputs switching) = 378mW + 120mW = 498mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.498W * 66.6C/W = 118.1C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6A. Thermal Resistance JA for 20-pin TSSOP, Forced Convection
by Velocity (Linear Feet per Minute)
JA
0
114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance JA for 20-pin SOIC, Forced Convection
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS87339I-11
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
ICS87339I-11
TABLE 7A. JAVS. AIR FLOW TSSOP TABLE
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW SOIC TABLE
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87339I-11 is: 1745 Compatible with MC10EP139, MC100EP139
87339AGI-11
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REV. A
APRIL 12, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
20 LEAD TSSOP PACKAGE OUTLINE - M SUFFIX
FOR
ICS87339I-11
PACKAGE OUTLINE - G SUFFIX
FOR
20 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
87339AGI-11
Reference Document: JEDEC Publication 95, MS-013, MO-119
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Integrated Circuit Systems, Inc.
LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS87339I-11
TABLE 9. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS87339AGI-11 ICS87339AI11 20 lead TSSOP Tube -40C to 85C ICS87339AGI-11T ICS87339AI11 20 lead TSSOP 2500 Tape & Reel -40C to 85C -40C to 85C ICS87339AGI-11LF TBD 20 Lead "Lead-Free" TSSOP Tube ICS87339AGI-11LFT TBD 20 Lead "Lead-Free" TSSOP 2500 Tape & Reel -40C to 85C 20 lead SOIC Tube -40C to 85C ICS87339AMI-11 ICS87339AMI-11 ICS87339AMI-11T ICS87339AMI-11 20 lead SOIC 1000 Tape & Reel -40C to 85C 20 Lead "Lead-Free" SOIC Tube -40C to 85C ICS87339AMI-11LF TB D ICS87339AMI-11LFT TBD 20 Lead "Lead-Free" SOIC 1000 Tape & Reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87339AGI-11
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LOW SKEW, /2/4,/4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Pin Assignment - changed pin 6, "nc" to "reser ved". Pin Description table - corrected pin 6 to read reser ved to coordinate with Pin Assignment. Features section - corrected Output skew and Par t-to-Par t skew bullets. Ordering Information table - added Lead-Free note. Date 3/10/05 4/12/05
ICS87339I-11
Rev A A
Table T1
Page 1 2 1 13
T9
87339AGI-11
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