View ICS87972-147I_986936.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
* Fully integrated PLL * 14 LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync * Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs * CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL * Output frequency range: 10MHz to 150MHz * VCO range: 240MHz to 500MHz * Output skew: 200ps (maximum) * Cycle-to-cycle jitter, (all banks /4): 55ps (maximum) * Full 3.3V operating supply * -40C to 85C ambient operating temperature * Pin compatible with MPC972 * Compatible with PowerPCTM and PentiumTM Microprocessors
GENERAL DESCRIPTION
ICS
HiPerClockSTM
The ICS87972I-147 is a low skew, LVCMOS/LVTTL Clock Generator and a member of the HiPerClockTM S family of High Performance Clock Solutions from ICS.The ICS87972I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs.
The ICS87972I-147 is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the ICS87972I-147 can be used as a zero delay buffer/multiplier/ divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. Input frequency range is 6MHz to 150MHz. The ICS87972I-147 also has a QSYNC output which can be used or system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1. System Clock generator: Use a 16.66 MHz Crystal to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply 19.44MHz from a back plane to 77.76MHz for the line Card ASICs and Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay.
PIN ASSIGNMENT
FSEL_FB0 EXT_FB GNDO GNDO GNDO VDDO VDDO QB0 QB1 QB2 QFB QB3 VDD
FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1
GNDI
FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK
25 24 23 22 21
ICS87972I-147
20 19 18 17 16 15
2
nMR/OE
3
FRZ_CLK
4
FRZ_DATA
56
FSEL_FB2 PLL_SEL
78
REF_SEL CLK_SEL
14 9 10 11 12 13
CLK0 CLK1 XTAL1 XTAL2 VDDA
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
87972DYI-147
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
XTAL1 XTAL2
VCO_SEL PLL_SEL REF_SEL 1 0 CLK0 CLK1 CLK_SEL EXT_FB 0 1 PHASE DETECTOR LPF VCO 0 1
D Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
D
Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_FB2
nMR/OE POWER-ON RESET /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 0 /2 SYNC PULSE 1
D
Q
QC0
SYNC FRZ
QC1 QC2 QC3 QFB
D
Q
SYNC FRZ SYNC FRZ
FSEL_A0:1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2
2 2 2 3
/4, /6, /8, /10
D
Q
D
Q
SYNC FRZ
QSYNC
DATA GENERATOR
FRZ_CLK OUTPUT DISABLE CIRCUITRY 12
FRZ_DATA
INV_CLK
87972DYI-147
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
XTAL1 XTAL2 CLK0 CLK1 CLK_SEL REF_SEL
/2 0 1 /1 1
FSEL_A[0:1]
OSC
1 0 1 VCO RANGE 240MHz - 500MHz 0 0 PLL
2
FSEL_ A1 A0 00 01 10 11
QAx /4 /6 /8 /12
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
EXT_FB
FSEL_B[0:1]
2
VCO_SEL
PLL_SEL
FSEL_ B1 B0 00 01 10 11
QBx /4 /6 /8 /10
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_C[0:1]
2
FSEL_ C1 C0 00 01 10 11
QCx /2 /4 /6 /8
QC0
SYNC FRZ
QC1 QC2 QC3
0
SYNC FRZ SYNC FRZ
1 INV_CLK FSEL_FB[0:2]
3
FSEL_ FB2 FB1 FB0 QFB 0 0 0 /4 0 0 1 /6 0 1 0 /8 0 1 1 /10 1 0 0 /8 1 0 1 /12 1 1 0 /16 1 1 1 /20
FRZ_CLK FRZ_DATA
OUTPUT DISABLE CIRCUITRY SYNC FRZ
QFB
QSYNC
87972DYI-147
www.icst.com/products/hiperclocks.html
3
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Power Input Input Input Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 26, 27 Name GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2, FSEL_FB1, FSEL_FB0 PLL_SEL Power supply ground. Master reset and output enable. When HIGH, enables the outputs. When Pullup LOW, resets the outputs to tristate and resets output divide circuitr y. Enables and disables all outputs. LVCMOS / LVTTL interface levels. Pullup Clock input for freeze circuitr y. LVCMOS / LVTTL interface levels. Configuration data input for freeze circuitr y. Pullup LVCMOS / LVTTL interface levels. Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
6
Input
7 8 9, 10 11, 12 13 14 15, 24, 30, 35, 39, 47, 51 16, 18, 21, 23 17, 22, 33 37, 45, 49 19, 20 25 28 29 31 32, 34, 36, 38 40, 41 42, 43 44, 46, 48, 50 52
REF_SEL CLK_SEL CLK0, CLK1 XTAL1, XTAL2 VDDA INV_CLK GNDO QC3, QC2, QC1, QC0 VDDO FSEL_C1, FSEL_C0 QSYNC VDD QFB EXT_FB QB3, QB2, QB1, QB0 FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, QA0 VCO_SEL
Input Input Input Input Power Input Power Output Power Input Output Power Output Input Output Input Input Output Input
Selects between the PLL and reference clocks as the input to the output Pullup dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. Selects between cr ystal and reference clock. Pullup When LOW, selects CLK0 or CLK1. When HIGH, selects cr ystal inputs. LVCMOS / LVTTL interface levels. Clock select input. When LOW, selects CLK0. Pullup When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Analog supply pin. Inver ted clock select for QC2 and QC3 outputs. Pullup LVCMOS / LVTTL interface levels. Power supply ground. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins. Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. Core supply pins. Feedback clock output. LVCMOS / LVTTL interface levels. Pullup External feedback. LVCMOS / LVTTL interface levels. Bank B clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. Bank A clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Selects VCO. When HIGH, selects VCO / 1. Pullup When LOW, selects VCO / 2. LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See table 2, Pin Characteristics, for typical values.
87972DYI-147
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical 4 51 VDDA, VDD, VDDO = 3.465V 5 7 18 12 Maximum Units pF K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_A1 0 0 1 1 FSEL_A0 0 1 0 1 Outputs QA /4 /6 /8 /12 0 0 1 1 Inputs FSEL_B1 FSEL_B0 0 1 0 1 Outputs QB /4 /6 /8 /10 0 0 1 1 Inputs FSEL_C1 FSEL_C0 0 1 0 1 Outputs QC /2 /4 /6 /8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB /4 /6 /8 /10 /8 /12 /16 /20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic 0 VCO/2 CLK0 or CLK1 CLK0 BYPASS PLL Master Reset/Output Hi Z Non-Inver ted QC2, QC3 Logic 1 VCO XTAL CLK1 Enable PLL Enable Outputs Inver ted QC2, QC3
87972DYI-147
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
1:1 MODE
fVCO
QA QC QSYNC
2:1 MODE
QA QC QSYNC
3:1 MODE
QC(/2) QA(/4) QSYNC
3:2 MODE
QC(/2) QA(/8) QSYNC
4:1 MODE
QC(/2) QA(/8) QSYNC
4:3 MODE
QA(/6) QC(/8) QSYNC
6:1 MODE
QA(/12) QC(/2) QSYNC
FIGURE 1. TIMING DIAGRAMS
87972DYI-147
www.icst.com/products/hiperclocks.html
6
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 250 20 Units V V V mA mA
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH Input High Voltage VCO_SEL, PLL_SEL, REF_SEL, CLK_SEL EXT_FB, FSEL_FB2, nMR/OE, FSEL_X0:1, FSEL_FB0:2, FRZ_DATA CLK0, CLK1, FRZ_CLK, INV_CLK IOH = -20mA IOL = 20mA Test Conditions Minimum Typical 2 Maximum VDD + -0.3 Units V
-0.3
0.8
V
VIL
Input Low Voltage
-0.3
1.3 120
V A V V
IIN VOH VOL
Input Current Output High Voltage Output Low Voltage 2.4
0.5
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter CLK0, CLK1; NOTE 1 fIN Input Frequency XTAL1, XTAL2 12 Test Conditions Minimum Typical Maximum 150 40 Units MHz MHz
FRZ_CLK 20 MHz NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to 500MHz.
87972DYI-147
www.icst.com/products/hiperclocks.html
7
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum 12 Typical Maximum 40 50 7 Units MHz pF
TABLE 6. CRYSTAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Test Conditions /2 fMAX Output Frequency /4 /6 /8 t(O) Static Phase Offset; NOTE 1 CLK0 CLK1 QFB / 8 In Frequency = 50MHz - 10 -65 145 90 Minimum Typical Maximum 150 125 83.33 62.5 300 245 200 All Banks / 4 240 55 500 10 0.8V to 2V 0.15 45 0.7 55 10 8 Units MHz MHz MHz MHz ps ps ps ps MHz ms ns % ns ns
tsk(o) tjit(cc)
fVCO tLOCK tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 2, 4 Cycle-to-Cycle Jitter; NOTE 4 PLL VCO Lock Range PLL Lock Time; NOTE 3 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable TIme; NOTE 3
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87972DYI-147
www.icst.com/products/hiperclocks.html
8
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5%
VDD, VDDA, VDDO
SCOPE
V
Qx
DDO
Qx
LVCMOS
GND
2
V
Qy
DDO
2 tsk(o)
-1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VDD
CLK0, CLK1
V QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB
DDO
V
DDO
V
DDO
2
2
2
2
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
t(O)
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
CYCLE-TO-CYCLE JITTER
V
STATIC PHASE OFFSET
DDO
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB
2 Pulse Width t
PERIOD
Clock Outputs
0.8V
tR tF
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
87972DYI-147
www.icst.com/products/hiperclocks.html
9
tcycle n+1
EXT_FB
VDD 2
t(O) mean = Static Phase Offset
2V
2V 0.8V
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87972I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10 F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS87972I-147 has been characterized with 18 pF parallel resonant crystals. External capacitors are not required for this crystal interface. While layout the PC board, it is recommended to have spare footprints capacitor C1 and C2. If required, the spare C1 and C2 footprints can be used for fine tuned further for more accurate frequency. The possible C1 and C2 value are ranged from 2pF - 25pF. The suggest footprint size is 0402 or 0603.
XTAL2
C1 SPARE
X1 18pF Parallel Cry stal
XTAL1
C2 SPARE
Figure 3. CRYSTAL INPUt INTERFACE
87972DYI-147
www.icst.com/products/hiperclocks.html
10
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of ICS87972I-147 (Except QC0 and QFB) can be individually frozen (stopped in the logic "0" state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the ICS87972I-147 serial interface are FPGA's and ASICs. To place an output in the freeze state, a logic "0" must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic "1" must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic "0", it is used for the start bit of the next cycle; otherwise, the device will wait and won't start the next cycle until it sees a logic "0" bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic "0" start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the ICS87972I-147 can sample each FRZ_DATA bit with the rising edge of the FRZ_CLK signal.
FRZ_DATA
rt Sta it B
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3 QSYNC
FRZ_CLK
FIGURE 4A.
FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 4B. OUTPUT DISABLE TIMING
87972DYI-147
www.icst.com/products/hiperclocks.html
11
FRZ Latched
FRZ Clocked
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87972I-147 is: 8364
87972DYI-147
www.icst.com/products/hiperclocks.html
12
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
52 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b b1 D D1 E E1 e ccc ddd 0.45 --0.05 1.35 0.22 0.22 BCC MINIMUM NOMINAL 52 --1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC --0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87972DYI-147
www.icst.com/products/hiperclocks.html
13
REV. A AUGUST 26, 2003
Integrated Circuit Systems, Inc.
ICS87972I-147
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking ICS87972DYI147 ICS87972DYI147 Package 52 Lead LQFP 52 Lead LQFP on Tape and Reel Count 160 per tray 500 Temperature -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS87972DYI-147 ICS87972DYI-147T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87972DYI-147
www.icst.com/products/hiperclocks.html
14
REV. A AUGUST 26, 2003

▲Up To Search▲

Price & Availability of ICS87972-147I

	To Download ICS87972-147I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .