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Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
FEATURES
* Fully integrated PLL * 15 single ended 3.3V LVCMOS / LVTTL outputs * Selectable CLK1 or differential CLK0, nCLK0 inputs for redundant clock applications * CLK1 accepts LVCMOS or LVTTL input levels * CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 125MHz * VCO range: 250MHz to 500MHz * External feedback for "zero delay" clock regeneration * Cycle-to-cycle jitter: 50ps (maximum) * Output skew: 200ps (maximum) * Bank skew: 70ps (maximum) * PLL reference zero delay: CLK1: -150ps to 150ps CLK0, nCLK0: -475ps to -175ps * 3.3V operating supply
GENERAL DESCRIPTION
The ICS87974I-01 is a low skew, low jitter 1-to-15 Differential-to-LVCMOS / LVTTL Clock Generator/ HiPerClockSTM Zero Delay Buffer and is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-toinput frequency ratios. The CLK1 and CLK0, nCLK0 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources.
ICS
Guaranteed low jitter and output skew characteristics make the ICS87974I-01 ideal for those applications demanding well defined performance and repeatability.
PIN ASSIGNMENT
VCO_SEL VDDOC VDDOC VDDOB GND GND GND QC3 QC0 QC1 QC2 QB0 nc
* -40C to 70C ambient operating temperature
GND nMR CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK1 CLK0 nCLK0 VDD VDDA
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
GND QB1 VDDOB QB2 GND QB3 VDDOB QB4 FB_IN GND QFB VDDOFB nc
ICS87974I-01
33 32 31 30 29 28
10 11 12
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
QA3 QA1 QA4 VDDOA QA2 VDDOA QA0 FB_SEL0 FB_SEL1 VDDOA GND GND GND
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
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1
REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
BLOCK DIAGRAM
SEL_A CLK_SEL
(Internal Pulldown) (Internal Pulldown)
0 CLK0 (Internal Pulldown) 1 nCLK0 (Internal Pullup)
FB_IN (Internal Pullup) PLL_SEL (Internal Pullup) VCO_SEL (Internal Pulldown) SEL_B (Internal Pulldown)
CLK1 (Internal Pulldown)
/2
0
0
/4
/2 /4 /6
0
DQ
5
QA0:QA4
PLL
1
1
1
0
DQ
5
QB0:QB4
1
0
DQ
4
QC0:QC3
1
SEL_C (Internal Pulldown)
nMR (Internal Pullup) FB_SEL1 FB_SEL0
(Internal Pulldown)
0 1 /2
0
DQ
QFB
1
(Internal Pulldown)
CLK_EN (Internal Pullup)
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
SIMPLIFIED BLOCK DIAGRAM
CLK_EN SEL_A VCO_SEL
CLK_SEL CLK1 CLK0 nCLK0 FB_IN
0 0 1 PLL 1
/2
0
/4
1
SEL_A 0 /2 1 /4
DQ
5
QA0:QA4
SEL_B
PLL_SEL SEL_B
0 1
/2 /4
DQ
5
QB0:QB4
SEL_C 0 /4 1 /6
SEL_C
DQ
4
QC0:QC3
FB_0 FB_1 0 0 /4 0 1 /6 1 0 /8 1 1 /12
DQ
QFB
FB_SEL(0:1) nMR/OE
2
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
Type Power Description Power supply ground. Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the outputs to go low. when logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Clock enable. When LOW, all outputs except QFB are low. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3. LVCMOS / LVTTL interface levels. Selects divide value for Bank C output as described in Table 3. LVCMOS / LVTTL interface levels. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 15, 19, 24, 30, 35, 39, 43, 47, 51 2 Name GND
nMR
Input
Pullup
3 4 5 6 7 8 9 10 11 27, 42 12 13 14, 20 16, 18, 21, 23, 25 17, 22, 26 28 29 31
CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK1 CLK0 nCLK0 nc VDD VDDA FB_SEL0, FB_SEL1 QA4, QA3, QA2, QA1, QA0 VDDOA VDDOFB QFB FB_IN
Input Input Input Input Input Input Input Input Input Unused Power Power Input Output Power Power Output Input Output Power Output Power Input
Pullup Pulldown Pulldown Pullup Pulldown Pulldown
Pulldown Clock input. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input No connect. Core supply pin. Analog supply pin. Selects divide value for Bank feedback output as described in Pulldown Table 3. LVCMOS / LVTTL interface levels. Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank A clock outputs. Output supply pin for QFB clock output. Clock output. LVCMOS / LVTTL interface levels. Feedback input to phase detector for generating clocks with Pullup "zero delay". Connect to pin 29. LVCMOS / LVTTL interface levels. Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank B clock outputs. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank C clock outputs. Selects VCO / 4 when HIGH. Selects VCO / 2 when LOW. Pulldown LVCMOS / LVTTL interface levels.
32, 34, QB4, QB3, 36, 38, 40 QB2, QB1, QB0 33, 37, 41 VDDOB 44, 46, QC3, QC2, 48, 50 QC1, QC0 45, 49 VDDOC 52 VCO_SEL
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 5 7 12 15 Maximum Units pF K K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
Output Impedance Power Dissipation Capacitance CPD VDD, VDDA, VDDOx = 3.465V; NOTE 1 (per output) NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs nMR 0 1 1 CLK_EN X 0 1 QA0:QA4 HiZ LOW Enable QB0:QB4 HiZ LOW Enable Outputs QC0:QC3 HiZ LOW Enable QFB HiZ Enable Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL 0 1 Operating Mode Bypass PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs CLK_SEL 0 1 PLL Input CLK1 CLK0, nCLK0
TABLE 3D. SELECT PIN FUNCTION TABLE
SEL_A 0 1 QAx /2 /4 SEL_B 0 1 QBx /2 /4 SEL_C 0 1 QCx /4 /6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs FB_SEL1 0 0 1 1 FB_SEL0 0 1 0 1 Outputs QFB /4 /6 /8 / 12
TABLE 3F. VCO SELECT FUNCTION TABLE
Inputs VCO_SEL 0 1 fVCO VCO/2 VCO/4
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 70C
Symbol VDD VDDA VDDOx IDD IDDO IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 125 25 15 Units V V V mA mA mA
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage FB_SEL0, FB_SEL1, CLK1, SEL_A:SEL_C, Input High Current CLK_SEL, VCO_SEL FB_IN, nMR, PLL_SEL, CLK_EN FB_SEL0, FB_SEL1, CLK1, SEL_A:SEL_C, Input Low Current CLK_SEL, VCO_SEL FB_IN, nMR, PLL_SEL, CLK_EN Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDD = VIN = 3.465V VDD = VIN = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 2.4 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V V
IIH
IIL
VOH VOL
NOTE 1: Outputs terminated with 50 to VDDOx/2.
87974AYI-01
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
Test Conditions CLK0 nCLK0 CLK0 nCLK0 VDD = VIN = 3.465V VDD = VIN = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 0.15 1.3 VDD -0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 70C
Symbol fMAX fVCO t(O) tsk(b) Parameter Output Frequency PLL VCO Lock Range; NOTE 5 PLL Reference Zero Delay; NOTE 2, 5, 6 Bank Skew; NOTE 3, 5 Output Skew; NOTE 4, 5 Cycle-to-Cycle Jitter ; NOTE 5 PLL Lock Time Output Rise/Fall Time Output Duty Cycle Output Enable Time 20% to 80% 200 45 VCO = 500MHz, Div 4 CLK1 CLK0, nCLK0 PLL_SEL = 1 Test Conditions Qx / 2, VCO / 2 Qx / 4, VCO / 2 Qx / 6, VCO / 2 250 -150 -475 0 -325 Minimum Typical Maximum 125 62.5 41.67 500 150 -175 70 200 50 10 700 55 10 10 Units MHz MHz MHz MHz ps ps ps ps ps mS ps % ns ns
tsk(o) tjit(cc)
tL tR / tF odc tEN
Output Disable Time tDIS All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 point of the input to theVDDOx/2 of the output. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew within a bank with equal load conditions. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Reference frequency of 50MHz used with all banks in DIV4.
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% V DD VDD, VDDA, VDDO
SCOPE
nCLK0
Qx
V
PP
LVCMOS
GND
Cross Points
V
CMR
CLK0
GND -1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
V V V
DIFFERENTIAL INPUT LEVEL
DDOX
DDOX
DDOX
V
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
QX0:QXx
VDDOX 2
QX0:QXx
tsk(b)
VDDOX 2
BANK SKEW (where X denotes outputs in the same bank)
V
DDOX
QAx, QBx, QCx, QFB
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87974AYI-01
2
QAx, QBx, QCx, QFB
2
2
2
DDOX
Qx
2
tcycle n+1
V
DDOX
Qy
2 tsk(o)
OUTPUT SKEW
VDD 2
CLK1 nCLK0 CLK0
QAx, QBx, QCx, QFB
VDDO 2
STATIC PHASE OFFSET
80% 20% tR
80% 20% tF
Clock Outputs
OUTPUT RIS/FALL TIME
REV. A FEBRUARY 9, 2004
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Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87974I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
87974AYI-01
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
example of the ICS87974I-01 LVCMOS clock generator. In this example, the input is driven by an LVCMOS driver.
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS87974I-01 LVCMOS buffer. Figure 4 shows a schematic
R8
43
Zo = 50
VDD=3.3V
VDDO
SP = Space (i.e. not intstalled)
U5
VDD
VCO_SEL GND QC0 VDDOC QC1 GND QC2 VDDOC QC3 GND nc VDDOB QB0
52 51 50 49 48 47 46 45 44 43 42 41 40
RS
Zo = 50
Driv er_LVCMOS_no_Ro
R7
VDD
VDD
10 - 15
C16 10u
C11 0.01u
C13 0.01u
Logic Input Pin Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
14 15 16 17 18 19 20 21 22 23 24 25 26
87974I-01
FB_SEL0 GND QA4 VDDOA QA3 GND FB_SEL1 QA2 VDDOA QA1 GND QA0 VDDOA
1 2 3 4 5 6 7 8 9 10 11 12 13
GND nMR CLK_EN SELB SELC PLL_SEL SELA CLK_SEL CLK1 CLK0 nCLK0 VDD VDDA
GND QB1 VDDOB QB2 GND QB3 VDDOB QB4 FB_IN GND QFB VDDOFB nc
39 38 37 36 35 34 33 32 31 30 29 28 27
R1
43
Zo = 50
To Logic Input pins
RD1 Not Install
To Logic Input pins
RD2 1K
(U1-17)
VDDO
(U1-22)
(U1-26)
(U1-28)
(U1-33)
(U1-37)
(U1-41)
(U1-45)
(U1-49)
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
C9 0.1uF
C10 0.1uF
C12 0.1uF
FIGURE 4. EXAMPLE ICS87974I-01 LVCMOS/LVTTL CLOCK OUTPUT BUFFER SCHEMATIC
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87974I-01 is: 4225
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
52 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
Marking ICS87974AYI-01 ICS87974AYI-01 Package 52 Lead LQFP 52 Lead LQFP on Tape and Reel Count 160 per tray 500 Temperature -40C to 70C -40C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87974AYI-01 ICS87974AYI-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87974AYI-01
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REV. A FEBRUARY 9, 2004
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Added schematic layout. Swichted labels for FB_SEL0 and FB_SEL1 in the Block Diagram and Simplified Block Diagram. Date 11/13/03 2/9/04
Rev A A
Table
Page 11 2&3
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