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Integrated Circuit Systems, Inc.
ICS95V850
DDR Phase Lock Loop Clock Driver (60MHz - 210MHz)
Recommended Application: DDR Clock Driver Product Description/Features: * Low skew, low jitter PLL clock driver * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * With bypass mode mux * Operating frequency 60 to 210 MHz * Universal input (LVTTL, LVPECL, LVDS, LVCMOS) Switching Characteristics: * CYCLE - CYCLE jitter: <60ps * OUTPUT - OUTPUT skew: <60ps * Period jitter: 30ps * DUTY CYCLE: 49.5% - 50.5%
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD NC CLK_INT CLK_INC NC AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD NC FB_INC FB_INT VDD FB_OUTT FB_OUTC GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
48-Pin TSSOP 6.10mm Body, 0.5mm Pitch
Block Diagram
FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
Functionality
INPUTS GND GND 2.5V (nom) 2.5V (nom) L H L H H L H L L H L H H L H L OUTPUTS L H L H H L H L AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC PLL State Bypassed/Off Bypassed/Off On On
FB_INT FB_INC CLK_INC CLK_INT
CLKT5 CLKC5
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
AVDD
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ICS95V850
ICS95V850
Pin Descriptions
PIN NUMBER PIN NAME TYPE PWR OUT OUT PWR IN IN PWR PWR OUT Ground "Complementary" clocks of differential pair outputs "Tr ue" Clock of differential pair outputs Power supply, 2.5V "True" reference clock input "Complementary" reference clock input Analog power supply, 2.5V A n a l o g gr o u n d "Complementary" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error "Complementary" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error No Connects DESCRIPTION 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 26, 30, 40, 43, 47, CLKC[9:0] 23, 19, 9, 6, 2 27, 29, 39, 44, 46, CLKT[9:0] 22, 20, 10, 5, 3 4, 11, 21, 28, 34, 38, 45, 13 14 16 17 32 VDD CLK_INT CLK_INC AVDD AGND FB_OUTC
33 35 36 12, 15, 37
FB_OUTT FB_INT FB_INC NC
OUT IN IN
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ICS95V850
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V Input clamp current: IIK (VI < 0 or VI > VDD) . . . . . . +/- 50mA Output clamp current: IOK (VO < 0 or VO > VDD) . . +/- 50mA Continuous output current: I O (VO = 0 to VDD) . . . . +/- 50mA Package thermal impedance, theta JA: DGG package +89C/ Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current High Impedance Output Current Input Clamp Voltage High-level output voltage Low-level output voltage SYMBOL I IH I IL IDD2.5 IDDPD IOZ VIK VOH VOL CONDITIONS VI = V DD or GND VI = VDD or GND CL = 0pf @ 200MHz CL = 0pf VDD = 2.7V, Vout = VDD or GND VDD = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL =1 mA IOH =12 mA VI = GND or V DD MIN 5 TYP MAX 5 148 100 10 -1.2 VDD - 0.1 1.7V 0.1 0.6 3.5 UNITS A A mA A mA V V V V V pF
CIN Input Capacitance1 1 Guaranteed by design at 233MHz, not 100% tested in production.
2.5
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ICS95V850
Recommended Operating Condition (see note1)
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature SYMBOL VDD, A VDD VIL VIH VIN VID V OX VIX IOH IOL TA 0 DC - CLKT, FB_INT AC - CLKT, FB_INT CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# MIN 2.3 -0.3 V DD/2 + 0.18 1.7 -0.3 0.36 0.7 VDD/2 - 0.15 TYP 2.5 0.4 2.1 MAX UNITS 2.7 V V VDD/2 - 0.18 0.7 V V V V DD + 0.6 V DD + 0.3 V DD + 0.6 V DD + 0.6 VDD/2 + 0.15 V V V V V mA mA C
0.45(VIH - VIL) V DD/2 0.55(V IH - VIL) -6.4 5.5 85
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN TYP Operating clock frequency Input clock duty cycle CLK stabilization freqop dtin TSTAB 66 40 MAX 210 60 15 UNITS MHz % s
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ICS95V850
Switching Characteristics (see note 3)
PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Phase error Output to Output Skew SYMBOL tPLH1 tPLL1 tEN tdis Tjit (per) t(jit_hper) t sl(i) t sl(o) Tcyc -Tcyc t(phase error) Tskew
4
CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz
MIN
TYP 5.5 5.5 5 5
MAX
UNITS ns ns ns ns ps ps V/ns V/ns ps ps ps
-30 -75 1 1 -50 0
100MHz to 200MHz
30 30 4 2.5 60 50 60
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design.
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ICS95V850
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD/2 V(CLKC) ICS95V850 GND Figure 1. IBIS Model Output Load VDD/2 ICS95V850 Z = 60 C = 14 pF -V DD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS95V850
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX # YX
YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter
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ICS95V850
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t (hper_n) 1 fo t (hper_n+1)
t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter
80%
80% VID , VOD
Clock Inputs and Outputs
20% Rise tsl Fall tsl
20%
Figure 8. Input and Output Slew Rates
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ICS95V850
Recommended Layout for the ICS95V850
General Layout Precautions: Use copper flooded ground on the top signal layer under the clock buffer The area under U1 on the right is an example. Flood over the ground vias. 1) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 2) Make all power and ground traces are as wide as the via pad for lower inductance. 3) VAA for pin 16 has a low pass RC filter to decouple the digital and analog supplies. The 4.7uF capacitors may be replaced with a single low ESR device with the same total capacitance. VAA is routed on a outside signal layer. Do not cut a power or ground plane and route in it. 4) Notice that ground vias are never shared. 5) When ever possible, VCC (net V2P5 in the schematic) pins have a decoupling capacitor. Power is always routed from the plane connection via to the capacitor pad to the VCC pin on the clock buffer. Moats or plane cuts are not used to isolate power. 6) Differential mode clock output traces are routed: a. With a ground trace between the pairs. Trace is grounded on both ends. b. Without a ground trace, clock pairs are routed with a separation of at least 5 times the thickness of the dielectric. If the dielectric thickness is 4.5 mil, the trace separation is at least 18 mils. 7) Terminate differential CLK_IN and FB_IN traces after routing to buffer pads. Component Values: Ref Desg. Value
C1,C4,C5, C7,C11,C12 C2,C3,C8, C9 C10 C6 R9,R12 R9 U1 .01uF 4.7uF .22uF 2200pF 120 4.7
Description
CERAMIC MLC CERAMIC MLC CERAMIC MLC CERAMIC MLC
Package
0603 1206 0603 0603 0603 0603 TSSOP48
ICS95V850
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ICS95V850
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
-Ce
b SEATING PLANE
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48 D mm. MIN MAX 12.40 12.60 D (inch) MIN .488 MAX .496
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Ref erence Doc.: JEDEC Publicat ion 95, M O-153 10-0039
Ordering Information
ICS95V850yGT
Example:
ICS XXXX y G - T
Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
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