View ICS9DB102_986984.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
2 Output PCI Express* Buffer with CLKREQ# Function
Recommended Application: * 1-to-2 Zero-delay or fanout buffer for PCI Express Pin Configuration
PLL_BW 1 20 VDDA CLK_INT 2 19 GNDA Output Features: CLK_INC 3 18 IREF * 2 - 0.7V current mode differential output pairs (HSCL) **CLKREQ0# 4 17 **CLKREQ1# VDD 5 16 VDD Key Specifications: GND 6 15 GND * Cycle-to-cycle jitter < 40ps PCIEXT0 7 14 PCIEXT1 * Output-to-output skew < 25 ps PCIEXC0 8 13 PCIEXC1 VDD 9 12 VDD Features/Benefits: SMBDAT 10 11 SMBCLK * CLKREQ# pin for outputs 1 and 4/output enable for Note: Express Card applications * PLL or bypass mode/PLL can dejitter incoming clock Pins preceeded by '**' have internal 120K ohm pull down resistors
* * * Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled
20-pin SSOP & TSSOP
0852B--07/26/04
*Other names and brands may be claimed as the property of others.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9DB102
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NAME PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD **CLKREQ1# PIN TYPE IN IN IN IN PWR PWR OUT OUT PWR I/O IN PWR OUT OUT PWR PWR IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complimentary" reference clock input. Output enable for PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for PCI Express output pair '1' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
18 19 20
IREF GNDA VDDA
OUT PWR PWR
Note: Pins preceeded by '**' have internal 120K ohm pull down resistors
0852B--07/26/04
2
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
General Description
The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the ICS9DB102 suitable for Express Card applications.
Block Diagram
CLKREQ0# CLKREQ1#
PCIEX0 CLK_INT SPREAD COMPATIBLE PLL PCIEX1
C LK_IN C
PLL_BW SMBDAT SMBCLK CONTROL LOGIC
IREF
Power Groups
Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core
0852B--07/26/04
3
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
Absolute Max
Symbol VDDA VDD Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH I IL1 Input Low Current I IL2 Operating Supply Current Input Frequency 3 Pin Inductance1 Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Spread Spectrum Modulation Frequency PLL Bandwidth SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time
1
CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock Triangular Modulation Lexmark Modulation PLL Bandwidth when PLL_BW=0 PLL Bandwidth when PLL_BW=1
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 0.8 5
UNITS NOTES V V uA uA uA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
I DD3.3OP Fi Lpin CIN COUT TSTAB
99
75 27 100
100 50 101 7 5 4.5 1.8
mA mA MHz nH pF pF ms kHz KHz KHz MHz
30 25 400 1.2 2.7
33 45
fMOD
BW VDD VOLSMBUS I PULLUP TRI2C TFI2C
@ I PULLUP SMBus SDATA pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15)
5.5 0.4
4 1000 300
V V mA ns ns
Guaranteed by design and characterization, not 100% tested in production.
0852B--07/26/04
4
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 > REF> 9, PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage SYMBOL Zo VHigh VLow Vovs Vuds CONDITIONS VO = Vx Statistical measurement on single ended signal using Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V 350 12 9.9970 9.9970 9.8720 175 175 550 140 850 150 1150 TYP MAX UNITS mV mV mV mV NOTE S 1 1,3 1,3 1,3 1,3 1,3 1,3 1,2 2 2 1,2 1 1 1 1 1 1 1 1 1 1
Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Input to Output Delay Duty Cycle Output-to-Output Skew Jitter, Cycle to cycle
1 2
d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-t f t pd t pdbyp dt3 t sk3 t jcyc-cyc t jcyc-cycbyp
PLL Mode. Bypass mode Measurement from differential wavefrom V T = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode
135 3.2 45
0 ppm 10.0030 ns 10.0533 ns ns 700 ps 700 ps 30 125 ps 30 125 ps 185 ps 3.7 ns 55 25 40 25 % ps ps ps
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements
3
I REF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50 .
0852B--07/26/04
5
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) 0 Pin # Name Control Function Type Byte 0 Functions Enables SMBus controlled by SW_EN RW Bit 7 Control SMBus registers RESERVED RW Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 Selects PLL PLL BW #adjust RW Low BW Bit 1 Bandwidth Bypasses PLL for PLL bypassed PLL Enable RW Bit 0 board test (fan out mode) SMBus Table: Output Enable Register Pin # Name Control Function Type Byte 1 RW RESERVED Bit 7 RW RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RW RESERVED Bit 0 SMBus Table: Function Select Register Pin # Name Control Function Type Byte 2 RESERVED RW Bit 7 RW RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RW RESERVED Bit 0
1 Functions controlled by device pins
PWD 1 X X X X X
High BW PLL enabled (ZDB mode)
1 1
0 -
1
PWD X X X X X X X X
0 -
1
PWD X X X X X X X X
0852B--07/26/04
6
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
SMBus Table: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 SMBus Table: DEVICE ID Pin # Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 -
1 -
PWD 0 0 0 0 0 0 0 1
Name
Control Function Type R R R Device ID R = 06 Hex R R R R
0 -
1
PWD 0 0 0 0 0 1 1 0
SMBus Table: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 1 0
0852B--07/26/04
7
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
20-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 SEE VARIATIONS SEE VARIATIONS
SYMBOL A A1 A2 b c D E E1 e L N a ZD VARIATIONS N 20
D mm. MIN 8.55 MAX 8.75
ZD (Ref) 1.47
D (inch) MIN .337 MAX .344
ZD (Ref) .058
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS9DB102yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0852B--07/26/04
8
Integrated Circuit Systems, Inc.
ICS9DB102 Preliminary Product Preview
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEATING PLANE
N 20
D mm. MIN 6.40 MAX 6.60 MIN .252
D (inch) MAX .260
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9DB102yGLFT
Example:
ICS XXXX yG LF T
Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0852B--07/26/04
9

▲Up To Search▲

Price & Availability of ICS9DB102

	To Download ICS9DB102 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .