View LP3970_988742.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LP3970 Power Management Unit for Advanced Application Processor
November 2005
LP3970 Power Management Unit for Advanced Application Processor
General Description
The LP3970 is a multi-function, programmable Power Management Unit, designed especially for advanced application processors. The LP3970 is optimized for low power handheld PMU applications and provides 11 low dropout, low noise linear regulators, two DC/DC magnetic buck regulators, a back-up battery charger and 4 GPO's. A high speed serial interface is included to program individual regulator output voltages as well as on/off control.
Features
n Compatible with advanced applications processors requiring dynamic voltage management (DVM) n Two buck regulator for powering high current processor functions or peripheral devices n Eleven LDO's for powering internal processor functions and I/O's n Backup battery charger with automatic switching for lithium and lithium-manganese coin cell batteries n I2C compatible high speed serial interface n Software control of regulator functions and settings n Thermal overload protection n Current overload protection n Tiny 48-Pin LLP package
Key Specifications
Buck Regulators n Programmable VOUT from 0.8 to 3.3V n Up to 95% efficiency n 650 mA output current n 3% output voltage accuracy LDO's n Programmable VOUT of 1.5-3.3V n 3% output voltage accuracy n 50 mA to 300 mA output current n 100 mV dropout
Applications
n n n n PDA phones Smart phones Personal media players Digital cameras
Simplified Application Circuit
20137101
(c) 2005 National Semiconductor Corporation
DS201371
www.national.com
LP3970
Connection Diagrams and Package Mark Information
48-Pin LLP
20137102
Package Mark
20137104
Top View
Note: Circle marks pin 1 position
www.national.com
2
LP3970
Ordering Information
LDO 4 Default Buck 2 Default (VCC_MEM) (VCC_IO) 2.8 1.8 Part Number LP3970SQ-31 LP3970SQX-31 2.8 3.0 3.0 3.3 3.0 3.3 LP3970SQ-35 LP3970SQX-35 LP3970SQ-44 LP3970SQX-44 LP3970SQ-45 LP3970SQX-45 3970-35 3970-44 3970-45 Package Marking 3970-31 Transport Media 250 Units Tape and Reel 2.5k Units Tape and Reel 250 Units Tape and Reel 2.5k Units Tape and Reel 250 Units Tape and Reel 2.5k Units Tape and Reel 250 Units Tape and Reel 2.5k Units Tape and Reel NSC Drawing SQA48A
*Contact National Semiconductor for availability
20137122
Default VOUT Coding
Y 1 2 3 4 5 Default VOUT 1.8 2.5 2.8 3.0 3.3
3
www.national.com
LP3970
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name VOUT 9 AGND 2,4,9 nVDD_FLT SYS_EN PWR_EN VOUT 2 VIN 2 VIN 7 VOUT 7 VBIAS Cap LDO 7 VOUT 1 VIN 1 AGND (LDO 1,7,8,RTC) nRSTO nRSTI nBAT_FLT VIN BU_Batt VOUT RTC VIN 8, RTC, VBAT_MON VOUT 8 VBIAS Cap LDO8 VOUT 3 VIN 3,10 VOUT 10 AGND 3,5,6,10 GPO1 GPO2 VOUT 5 VIN 5, 6 VOUT 6 GPO3 GPO4 BGND FB1 SYNC FB2 VIN B2 SW2 PGND B2 GND B1 ,B2 PGND B1 SW1 VIN B1 I/O O G O I I O I I O I O I G O I O I O I O I O I O G O O O I O O O G I I I I O G G G O I Type P G D D D A P P P A P P G D D D P P P P A P P P G D D P P P D D G A D A P P G G G P P LDO 9 output Ground pin LDO's 2,4,9 Regulator fault output High voltage domain power enable Low voltage domain power enable LDO 2 output Input power terminal to LDO 2 Input power terminal to LDO 7 LDO 7 Output Voltage reference bypass output. Only connect a 0.01 F ceramic capacitor from VREF to GND within 0.2 in. (5 mm) of the VREF pin LDO 1 output Input power terminal to LDO 1 Ground pin LDO's 1, 7, 8, RTC Output to applications processor from PMU Input to PMU Battery fault output Back-up battery positive connection RTC LDO output Input power terminal to LDO's 8, RTC, battery monitor LDO 8 output Voltage reference bypass output. Only connect a 0.01 F ceramic capacitor from VREF to AGND within 0.2 in. (5 mm) of the VREF pin LDO 3 output Input power terminal to LDO's 3 & 10 LDO 10 output Ground pin LDO's 3, 5, 6, 10 General purpose CMOS output General purpose CMOS output LDO 5 Output Input power terminal to LDO's. 5 & 6 LDO 6 output General purpose CMOS Output General purpose CMOS Output Ground for buck isolation Feedback/VOUT Buck 1 System clock input for buck converters synchronization in PWM mode Feedback/VOUT Buck 2 Input power terminal to buck 2 Output switch pin buck 2 NMOS power ground pin buck 2 Circuit ground SW1 and SW2 NMOS power ground pin buck 1 Output switch pin buck 1 Input power terminal to buck 1 Description
www.national.com
4
LP3970
Pin Descriptions
Pin # 44 45 46 47 48
A: Analog Pin I: Input Pin D: Digital Pin I/O: Input/Output Pin G: Ground Pin O: Output Pin P: Power Pin
(Continued) I/O I/O I G O I Type D D G P P Serial interface clock input Digital ground pin. LDO 4 Output Input power terminal to LDO's 4 & 9 Description Serial interface data input/output
Name SDA SCL DGND VOUT 4 VIN 4, 9
Applications Schematic Diagram
20137105
5
www.national.com
LP3970
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. All Input GND to GND Slug Junction Temperature (TJMAX) Storage Temperature Power Dissipation (TA = 70C) (Note 4) JA Maximum Lead Temp (Soldering) -0.3 to +6V
ESD Rating (Note 5) Human Body Model Machine Model 1.0 kV 200V
0.3V
150C -65C to 150C 3.2W 25C/W 260C
Operating Ratings (Note 1)
VIN VEN Junction Temperature (TJ) Operating Temperature (TA) Maximum Power Dissipation (TA = 70C) 2.7 to 5.5V 0 to (VIN + 0.3V) -40C to 125C -40C to 85C 2.2W
General Electrical Characteristics Unless otherwise noted, VIN = 3.6, CIN = 1.0 F, COUT = 0.47 F, COUT (VRTC) = 1.0 F ceramic, CBYP = 0.1F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6) Supply Specification LP3970
Supply Supply Type Power Domain Default (V) LDO_RTC LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 LDO9 LDO10 Buck 1 Buck 2 Digital Analog Digital Digital Digital Digital Digital Analog Analog Digital Digital Digital Digital VBATT VCC_PLL VCC_SRAM VCC_USB VCC_IO VCC_USIM VCC_BB/LCD GP Analog GP Analog GP Digital GP Digital VCC_CORE VCC_MEM Part Number LP3970SQ-31 LP3970SQ-35 LP3970SQ-44 LP3970SQ-45 2.8 1.3 1.1 2.8 See Table Below 3.0 2.8 1.8 2.8 2.8 2.8 1.45 See Table Below LDO4 Default (V) 2.8 2.8 3.0 3.0 VOUT (Volts) Range (V) Fixed Fixed Fixed 1.5 to 3.4 1.5 to 3.4 1.5 to 3.4 1.5 to 3.4 Fixed 1.5 to 3.4 1.5 to 3.4 1.5 to 3.4 0.8 to 2.0 1.8 to 3.3 Resolution (mV) N/A N/A N/A 100 100 100 100 N/A 100 100 100 50 100 IMAX Maximum Output Current (mA) 5 100 100 150 150 150 50 100 150 300 300 650 650
Buck 2 Default (V) 1.8 3.3 3.0 3.3
www.national.com
6
LP3970
RTC LDO
Unless otherwise noted, VIN = VBATT = 3.6V CIN = 1.0 F, COUT (VRTC) = 0.47 F ceramic. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6) Symbol VOUT VOUT Parameter Output Voltage, Fixed (Note1) Line Regulation Load Regulation IMAX ISC VIN VOUT IQ_Max CO Load Current Short Circuit Current Limit Dropout Voltage Maximum Quiescent Current Output Capacitor Condition VIN Connected, ILOAD = 1 mA VIN = (VOUT + 0.3V) to 5.5V Load Current = IMAX VIN = 3.6V, Load Current = 1 mA to IMAX VIN = VOUT +0.3 to 5.5V VOUT = 0V Load Current = IMAX (Note 7) IOUT = 0 mA Capacitance for Stability ESR 0.7 5 35 220 40 1 500 375 Min 2.632 Typ 2.8 Max 2.968 0.15 0.05 5 %/V %/mA mA mA mV A F m Units
Common Performance Specifications LDO 1 to 10
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 F, COUT = 0.47 F, CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ= 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6) Symbol VOUT Accuracy Parameter LDO 1 Output Voltage Accuracy (Default VOUT) LDO 2 Output Voltage Accuracy (Default VOUT) LDO 3-10 Output Voltage Accuracy (Default VOUT) VOUT Line Regulation Load Regulation LDO 1,2,7 Load Regulation LDO 3,4,5,8 Load Regulation LDO 6 Load Regulation LDO 9,10 ISC VIN VOUT PSRR PSRR n Analog IQ Digital IQ TON TSD Short Circuit Current Limit Dropout Voltage Digital Supply Ripple Rejection Analog Supply Ripple Rejection Analog Supply Output Noise Voltage Quiescent Current "On" Quiescent Current "Off" Quiescent Current "On" Quiescent Current "Off" Turn On Time Thermal Shutdown VOUT = 0V Load Current = 50 mA (Note 7) f = 10 kHz, Load Current = IMAX f = 10 kHz, Load Current = IMAX 10 Hz < F < 100 kHz IOUT = 0 mA IOUT = IMAX EN is de-asserted IOUT = 0 mA IOUT = IMAX EN is de-asserted Start up from Shut-down (Note 10) Temperature Hysteresis 160 20 45 60 80 40 60 0.03 40 60 0.03 300 sec C 95 180 A 80 130 A 400 150 Condition ILOAD = 1 mA ILOAD = 1 mA ILOAD = 1 mA VIN = (VOUT +0.3) to 5.5V, Load Current = IMAX (Note 2) VIN = 3.6V, Load Current = 1 mA to IMAX Min 1.2285 1.056 -3 Typ 1.3 1.1 Max 1.3715 1.144 +3 0.15 0.015 0.011 0.075 0.006 mA mV dB dB uVrms %/mA V Units
% %/V
7
www.national.com
LP3970
Common Performance Specifications LDO 1 to 10
(Continued)
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 F, COUT = 0.47 F, CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ= 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6) Symbol COUT Parameter Output Capacitance LDO 1 Output Capacitance LDO 2 - 10 Output Capacitor LDO 1 - 10 Condition Capacitance for Stability Capacitance for Stability C TJ 125C -40 TJ 125C ESR Min 0.33 0.33 0.68 5 Typ 0.47 0.47 1 500 F Max Units
Buck Converters SW1, SW2
Unless otherwise noted, VIN = VBATT = 3.6V CIN = 10 F, COUT = 10 F, LOUT = 2.2 H Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6) Symbol VOUT Eff ISHDN Efficiency Shutdown Supply Current Sync Mode Clock Frequency fOSC IPEAK IQ RDSON (P) RDSON (N) TON TSD CIN CO Internal Oscillator Frequency Peak Switching Current Limit Quiescent Current "On" Pin-Pin Resistance PFET Pin-Pin Resistance NFET Turn On Time Thermal Shutdown Input Capacitor Output Capacitor Start up from Shut-down Temperature Hysteresis Capacitance for Stability Capacitance for Stability 10 10 (Open Loop) No Load PFM Mode No Load PWM Mode Parameter Output Voltage Accuracy Condition Default VOUT Load Current = 200 mA EN is de-asserted Synchronized from 13 MHz System Clock 1.1 Min 3 90 0.1 1.6 1.6 850 33 200 400 250 500 150 20 F F 675 500 m m sec C 55 2.0 Typ Max 3 Units % % A MHz MHz mA A
Back-Up Charger Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6), (Note 8) Symbol VIN IOUT VOUT Parameter Operational Voltage Range Backup Battery Charging Current (Default Setting) Charger Termination Voltage Backup Battery Charger Short Circuit Current PSRR Power Supply Ripple Rejection Ratio Quiescent Current Condition Voltage at VIN VIN = 3.6V, Backup_Bat = 2.5V, Backup Battery Charger Enabled VIN = 5.5V Backup Battery Charger Enabled Backup_Bat = 0V, Backup Battery Charger Enabled IOUT 50 A, VOUT = 3.15V VOUT + 0.4 VBATT = VIN 5.5V f < 10 kHz IOUT < 50 A 2.8 Min 3.3 500 3.0 9 15 3.2 Typ Max 5.5 Units V A V mA dB
IQ
25
A
www.national.com
8
LP3970
Back-Up Charger Electrical Characteristics
(Continued)
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 TJ 125C. (Note 1), (Note 6), (Note 8) Symbol COUT Parameter Output Capacitance Output Capacitor ESR Condition 0 A IOUT 100 A 5 Min Typ 0.1 500 Max Units F M
Logic Inputs DC Operating Conditions
Logic input specifications applies to SYS_EN, PWR_EN and nRSTI. Symbol VIL VIH ILEAK Parameter Low Level Input Voltage High Level Input Voltage Input Leakage Current 1.6 0.01 Condition Min Typ Max 0.4 Units V V A
Logic Output DC Operating Conditions
Symbol VOL VOH ILEAK Parameter Output Low Level Output High Level Output Leakage Current 2.3 +5 Condition Min Typ Max 0.4 Units V V A
GPO Logic Output DC Operating Conditions
The LP3970 contains four (4) general purpose CMOS outputs (GPO) connected to the VDD_RTC. Each GPO can be set to high impendence (HiZ), logic high (VOH), or logic low (VOL) by using the serial interface. The default setting is HiZ Symbol VOL VOH VHZ Parameter Output Low Level Output High Level Logic Current in High Z Mode VIN = VRTC/2 2.1 5 Condition Min Typ Max 0.4 Units V V A
nBATT_FLT DC Operating Conditions
Symbol Parameter nBATT_FLT Default Voltage nBATT_FLT Threshold Voltage VOL VOH ILEAK Output Low Level Output High Level Input Leakage Current 2.3 +5 Programmable via serial data port 2.5 Condition Min Typ 2.8 3.5 0.4 V V V A Max Units
I2C Compatible Serial Interface Electrical Specifications
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40C TJ 125C. (Note 1), (Note 6), (Note 9) Symbol VIL VIH VOL IOL FCLK tBF tHOLD tCLKLP tCLKHP Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage Low Level Output Current Clock Frequency Bus-Free Time Between Start and Stop Hold Time Repeated Start Condition CLK Low Period CLK High Period
9
Condition
Min -0.5 0.7VRTC 0
Typ
Max 0.3 VRTC VRTC 0.2 VTRC
Units V
VOL = 0.4V
3.0 400 1.3 0.6 1.3 0.3
mA kHz s s s s
www.national.com
LP3970
I2C Compatible Serial Interface Electrical Specifications
Symbol tSU tDATAHLD tCLKSU TSU TTRANS Parameter Set Up Time Repeated Start Condition Data Hold Time Data Set Up Time Set Up Time for Start Condition Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of Both DATA & CLK Signals Condition Min 0.6 0 100 0.6
(Continued)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40C TJ 125C. (Note 1), (Note 6), (Note 9) Typ Max Units s s s s 50 ns
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: LDO 1,2,7 Line Regulation Specified as VIN = 2.5V to 5.5V ILOAD= IMAX. Specification does not apply to LDO 1. Note 3: All voltages are with respect to the potential at the GND pin. Note 4: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. (JESD22-A114C) The machine model is a 200 pF capacitor discharged directly into each pin. (EAIJ) Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 7: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. Dropout specification does not apply to LDO 1,2,6,7. Note 8: Back-up battery charging current is programmable via the I2C compatible interface. Refer to the Application Section for more information. Note 9: Both I2C compatible signals from the applications processor have alternate functions as GPIO's. Following cold-start power-on or a hard reset both signals default to GPIO"s. An internal pull-down resistor on each signal prevents them from floating during reset or power-on events. The I2C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 k to 20 k range. The I2C signals from the processor are pulled low after power-up or reset. Note 10: CBYP not connected to LDO 7 & 8. Use of a CBYP capacitor will increase the LDO's start-up time.
www.national.com
10
LP3970
Typical Performance Characteristics
Output Voltage Change vs. Temperature
Typical LDO Characteristics Ground Current vs. Load Current
20137123
20137124
Enable Start-Up Time
Enable Start-Up Time
20137125
20137126
Load Transient
Output Voltage vs. Temperature, VOUT = 1.45V)
20137127
20137128
11
www.national.com
LP3970
Typical Performance Characteristics
Buck1 Change in Output Voltage vs. Load Current
Typical Buck Converter Characteristics RDSON vs. Temperature
20137129
20137130
Efficiency vs. Output Current (VOUT = 1.45V, L = 2.2 H)
Efficiency vs. Output Current (VOUT = 1.8V, L = 2.2 H)
20137131
20137132
Switching Frequency vs. Temperature
Line Transient Response (PWM Mode)
20137134
20137133
www.national.com
12
LP3970
Typical Performance Characteristics Typical Buck Converter Characteristics
Load Transient Response (PWM Mode)
(Continued)
Load Transient Response (PFM Mode 0.5 mA to 50 mA)
20137135
20137136
Load Transient Response (PFM Mode 50 mA to 0.5 mA)
Start Up into PWM Mode (Output Current = 300 mA)
20137137
20137138
Start Up into PFM Mode (Output Current = 1 mA)
20137139
13
www.national.com
LP3970
Functional Block Diagram
20137121
www.national.com
14
LP3970
Buck Converter Operation
DEVICE INFORMATION The LP3970 includes two high efficiency step down DC-DC switching buck converters. Using a voltage mode architecture with synchronous rectification, the buck converters have the ability to deliver up to 600 mA depending on the input voltage, output voltage, ambient temperature and the inductor chosen. There are three modes of operation depending on the current required - PWM, PFM, and shutdown. The device operates in PWM mode at load currents of approximately 80 mA or higher, having voltage tolerance of 4% with 90% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced current consumption. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN = 0.01 A typ). Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage is 2.8V or higher. CIRCUIT OPERATION The buck converters operates as follows. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN-VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L. The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET.
20137106
FIGURE 1. Typical PWM Operation Internal Synchronous Rectification While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. Current Limiting A current limit feature allows the converters to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 850 mA (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A: The inductor current becomes discontinuous. B: The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30 mA + VIN/42).
15
www.national.com
LP3970
Buck Converter Operation
(Continued)
20137107
FIGURE 2. Typical PFM Operation During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.6% and 1.7% above the nominal PWM output voltage. If the output voltage is below the "high" PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage reaches the `high' PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/27. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the `high' PFM comparator threshold (see Figure 3), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the `high' PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this `sleep' mode is 16 A (typ), which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the `low' PFM threshold, the cycle repeats to restore the output voltage (average voltage in PFM mode) to 1.15% above the nominal PWM output voltage. If the load current should increase during PFM mode (see Figure 3) causing the output voltage to fall below the `low2' PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN = 2.8V the part transitions from PWM to PFM mode at 35 mA output current and from PFM to PWM mode at 85 mA , when VIN = 3.6V, PWM to PFM transition happens at 50 mA and PFM to PWM transition happens at 100 mA, when VIN = 4.5V, PWM to PFM transition happens at 65 mA and PFM to PWM transition happens at 115 mA.
20137108
FIGURE 3. Operation in PFM Mode and Transfer to PWM Mode
www.national.com
16
LP3970
Buck Converter Operation
SHUTDOWN MODE
(Continued)
Typical start-up times with 22 F output capacitor and 300 mA load current is 400 s and with 1 mA load current its 275 s. LDO - LOW DROP OUT OPERATION The buck converter can operate at 100% duty cycle (no switching, PMOS switch completely on) for low drop out support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the converters are turned off. When the converter is enabled, EN, soft start is activated. It is recommended to disable the converter during the system power up and undervoltage conditions when the supply is less than 2.8V. SOFT START The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 70 mA, 140 mA, 280 mA and 1020 mA (typ. switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up.
*ILOAD *RDSON, PFET *RINDUCTOR
Load Current Drain to source resistance of PFET switch in the triode region Inductor resistance
Power Controller Interface Signals
Signal PWR_EN SYS_EN PWR_SCL PWR_SDA nRSTI nRSTO nBATT_FLT nVDD_FLT Definition Low voltage power enable High voltage power enable Serial bus clock Serial bus data Forces an unconditional hardware reset Forces an unconditional hardware reset Indicates main battery removed or discharged Indicates one or more supplies are out of regulation Low Low Low Low Active State High High Clock Signal Direction (x) Input Input Input Bidirectional Input Output Output Output
Forces an unconditional reset when activated from a momentary contact push button switch. is an active-low signal from the PMU to the Applications processor that tells the processor to enter the hardwarereset state. nRSTO is asserted for a cold start power-on or if the reset button is pushed. The PMU must assert nRSTO for both events. nRSTO will remain asserted for a minimum of 50 ms. PWR_EN is an active-high input to the PMU from the Applications processor that enables the low voltage power supplies (VCC_CORE, VCC_SRAM, and VCC_PLL). SYS_EN is an active-high input to the PMU from the Applications processor that enables the high voltage power supplies (VCC_IO, VCC_LCD, VCC_MEM, VCC_USIM, VCC_BB, and VCC_USB). nVDD_FLT signals the Applications processor that one or more of it's enabled supplies are below the minimum regulation limit (supplies that are not enabled do not cause nVDD_FLT assertion).
nRSTI nRSTO
Power Enables
PMU Output LDO_RTC LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 LDO9 LDO10 None PWR_EN PWR_EN SYS_EN SYS_EN SYS_EN SYS_EN PWR_EN SYS_EN SYS_EN SYS_EN Enable Applications Input VCC_BAT VCC_PLL VCC_SRAM VCC_USB VCC_IO VCC_USIM VCC_BB/LCD Peripheral Peripheral Peripheral Peripheral Phase locked loops Internal SRAM Differential USB interface Peripheral input/output USIM interface Baseband interface, LCD input/output AUX1, GP Analog AUX2, GP Analog AUX3, GP Digital AUX4, GP Digital Supply Reference Sleep-control subsystem. oscillators, and real-time clock
17
www.national.com
LP3970
Power Enables
PMU Output SW1 SW2
(Continued) Enable Applications Input VCC_CORE VCC_MEM CPU Core Memory controller input/output Supply Reference
PWR_EN SYS_EN
I2C Compatible Interface
I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW.
20137109
I2C START and STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always
generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.
20137110
TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received.
After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3970 address is 46h. For the eighth bit, a "0" indicates a WRITE and a "1" indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.
www.national.com
18
LP3970
I2C Compatible Interface
(Continued) I2C Write Cycle
20137111
w = write (SDA = "0") r = read (SDA = "1") ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start
xx = 46h However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 5.
I2C Read Cycle
20137112
I2C Timing Diagram
20137113
LP3970 Serial Port Communication Address Code 7h'46
1 0 0 0 1 1 0 R/W
19
www.national.com
LP3970
I2C Compatible Interface
(Continued)
LP3970 Control and Data Codes
Numbers in parentheses indicate default setting. (0) bit is set to low state and(1) bit is set to high state. R/O -Read Only, All other bits are Read and Write. Addrs 8h'0 8h'01 8h'02 Register Enable 0 Enable 1 GPO Control LDO3 Data Code LDO4 Data Code LDO5 Data Code LDO6 Data Code LDO8 Data Code LDO9 Data Code LDO10 Data Code Buck1 Data Code Buck2 Data Code Back Up Battery Charger 7 LDO8-EN (1) Not used (0) GPO4 nHZ EN (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) nBU_Bat EN (0) 6 LDO7-EN (1) Not used (0) GPO4 EN (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Ext_clk EN (0) Ext_clk EN (0) nBat_FLT EN (0) 5 LDO6-EN (1) Not used (0) GPO3 nHZ EN (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) Not used (0) nStep_EN (1) nStep_EN (1) BAT_FLT Voltage (0) 4 LDO5-EN (1) Not used (0) GPO3 EN (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (0) BAT_FLT Voltage (1) 3 LDO4-EN (1) Buck2_EN (1) GPO2 nHZ EN (0) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (0) BAT_FLT Voltage (0) 2 LDO3-EN (1) Buck1_EN (1) GPO2 EN (0) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (0) nBU_Bat Charger Enable (0) 1 LDO2-EN (1) LDO10_EN (1) GPO1 nHZ EN (0) VOUT (0) VOUT (0) VOUT (1) VOUT (0) VOUT (0) VOUT (0) VOUT (0) VOUT (1) VOUT (0) BU_Bat Charger Current (0) 0 LDO1_EN (1) LDO9_EN (1) GPO1 EN (0) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (1) VOUT (0) VOUT (1) BU_Bat Charger Current (1)
8h'03
8h'04
8h'05
8h'06
8h'08
8h'09
8h'0A
8h'0B
8h'0C
8h'0D
www.national.com
20
LP3970
I2C Compatible Interface
Data Code 5h'00 5h'01 5h'02 5h'03 5h'04 5h'05 5h'06 5h'07 5h'08 5h'09 5h'0A 5h'0B 5h'0C 5h'0D 5h'0E 5h'0F 5h'10 5h'11 5h'12 5h'13 5h'14 5h'15 5h'16 5h'17 5h'18 5h'19 5h'1A 5h'1B 5h'1C 5h'1D 5h'1E 5h'1F
(Continued) Output Voltage Selection Codes LDO's 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Buck_1 (V) N/A 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 Buck _2 (V) N/A 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
3.1 3.2 3.3 3.4 nBATT_FLT Threshold Voltage Voltage Selection Codes Bold face voltages are default values
Data Code 3h'00 3h'01 3h'02 3h'03 3h'04 3h'05
De-asserted 2.4 2.6 2.8 3.0 3.2 3.4
Asserted 2.6 2.8 3.0 3.2 3.4 3.6
21
www.national.com
LP3970
Battery Monitoring
When Back-Up battery is connected but Main battery removed or voltage too low, LP3970 uses Back-Up Battery for generating LDO_RTC voltage. When Main Battery is avail-
able the battery switch changes main battery for LDO_RTC voltage and Back-Up Battery charger starts charging. User can set the battery fault determination voltage and battery charging current via I2C compatible interface.
BU Charger Current Selection Code Data Code 2h'00 2h'01 2h'02 ISET (A) 375 500 625 The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is available. 4. After system power (VIN) is applied, the LP3970 deasserts nBATT_FLT. 5. The Applications processor asserts SYS_EN, the LP3970 enables the system high-voltage power supplies. The Applications processor starts its countdown timer set to 125 mS 3.
Power On Sequence
The Power Management Unit (PMU) supplies both highvoltage (I/O) and low-voltage power to the Applications processor. There are two power control signal inputs to the LM3970 PMU. SYS_EN controls the high-voltage supplies and PWR_EN controls the low-voltage supplies. When the back-up battery is installed, the processor begins the initial cold-start, power-up sequence enabling its internal power management unit and one oscillator. The LP3970 will monitor voltages and generate the nBATT_FLT and nVDD_FLT signals. The LP3970 will assert both nBATT_FLT and nVDD_FLT until VIN is above the default threshold voltage. Initial Cold Start Power on Sequence 1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the RTC_LDO turns on and supplies a stable output voltage to the VCC_BATT pin of the Applications processor (initiating the power-on reset event) with nRSTO asserted from the LP3970 to the processor. 2. nRSTO de-asserts after a minimum of 50 mS.
The LP3970 enables the high-voltage power supplies. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power supplies. The processor starts the countdown timer set to 125 mS period. 8. The Applications processor asserts PWR_EN, the LP3970 enables the low-voltage regulators. 9. Countdown timer expires; If nVDD_FLT is de-asserted the power up sequence continues by enabling the processors 13 MHz oscillator and PLL's. 10. The Applications processor begins the execution of code.
6. 7.
Cold Start Power on Timing
20137114
www.national.com
22
LP3970
Power On Sequence
Symbol t1 t2 t3 t4 t5 t6 Description
(Continued)
Power-On Timing Specifications
Min 50 100 10 125 120 125 Typ Max Units ms s ms ms ms ms Delay from VCC_RTC assertion to nRSTO de-assertion Delay from nBATT_FLT de-assertion to nRESET assertion Delay from nRST de-assertion to SYS_EN assertion Delay from SYS_EN assertion to PWT_EN assertion Delay from PWR_EN assertion to nVDD_FLT de-assertion Delay from PWR_EN assertion to nRST_OUT de-assertion
Hardware Reset Sequence
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters hardware reset state. The LP3970 must hold the nRST low long enough to allow the processor time to initiate the reset state, which is a minimum of 50 ms Reset Sequence nRSTI is asserted nRSTO is asserted and will de-asserts after a minimum of 50 ms. 3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is available. 4. After system power (VIN) is turned on, the LP3970 deasserts nBATT_FLT. 5. The Applications processor asserts SYS_EN, the LP3970 enables the system high-voltage power sup1. 2.
plies. The Applications processor starts its countdown timer set to 125 ms. 6. The LP3970 enables the high-voltage power supplies. 7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power supplies. The processor starts the countdown timer set to 125 mS period.
8.
The Applications processor asserts PWR_EN, the LP3970 enables the low-voltage regulators. 9. Countdown timer expires; If nVDD_FLT is de-asserted the power up sequence continues by enabling the processors 13 MHz oscillator and PLL's. 10. The Applications processor begins the execution of code.
23
www.national.com
LP3970
Typical Application Circuit
Connection Diagram for PXA27x and LP3970 Power Domains
20137115
www.national.com
24
LP3970
Application Hints
LDO CONSIDERATIONS External Capacitors The LP3970's regulators requires external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input Capacitor An input capacitor is required for stability. It is recommended that a 1.0 F capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important:Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1.0 F over the entire operating temperature range. Output Capacitor The LDO's are designed specifically to work with very small ceramic output capacitors. A 1.0 F ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 m to 500 m, are suitable in the application circuit. For this device the output capacitor should be connected between the VOUT pin and ground. It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 m to 500 m for stability. No-Load Stability The LDO's will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. Capacitor Characteristics The LDO's are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 F to 4.7 F, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1.0 F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability for the LDO's.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 4 shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.
20137116
FIGURE 4. Graph Showing a Typical Variation in Capacitance vs. DC Bias The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55C to +125C, will only vary the capacitance to within 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55C to +85C. Many large value ceramic capacitors, larger than 1 F are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25C to 85C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 F to 4.7 F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would
25 www.national.com
LP3970
Application Hints
(Continued)
Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the max current limit of 1150 mA. A 2.2 H inductor with a saturation current rating of at least 1150 mA is recommended for most applications. The inductor's resistance should be less than 0.3 for good efficiency. Table 1 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. INPUT CAPACITOR SELECTION A ceramic input capacitor of 10 F, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as:
have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. BUCK CONSIDERATIONS Inductor Selection There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25C so ratings at max ambient temperature of application should be requested from manufacturer. There are two methods to choose the inductor saturation current rating. Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as
* * * * * *
IRIPPLE: Average to peak inductor current IOUTMAX: Maximum load current (600 mA) VIN: Maximum input voltage in application L: Min inductor value including worst case tolerances (30% drop can be considered for method 1) f: Minimum switching frequency (1.6 MHz) VOUT: Output voltage
The worst case is when VIN = 2 * VOUT
TABLE 1. Suggested Inductors and their Suppliers
Model DO3314-222MX LPO3310-222MX ELL5GM2R2N CDRH2D14-2R2 Vendor Coilcraft Coilcraft Panasonic Sumida Dimensions LxWxH (mm) 3.3 x 3.3 x 1.4 3.3 x 3.3 x 1.0 5.2 x 5.2 x 1.5 3.2 x 3.2 x 1.55 D.C.R (Max) 200 m 150 m 53 m 94 m
OUTPUT CAPACITOR SELECTION Use a 10 F, 6.3V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The LP3970 has been evaluated with 10 F, 6.3V, 0805 capacitor. The output filter capacitor smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions.
www.national.com 26
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follows
Voltage peak-to-peak ripple due to ESR can be expressed as follows VPP-ESR = (2 * IRIPPLE) * RESR
LP3970
Application Hints
(Continued)
Because these two components are out of phase the rms value can be used to get an approximate value of peak-topeak ripple. Voltage peak-to-peak ripple, root mean squared can be expressed as follows
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part.
TABLE 2. Suggested Capacitor and their Suppliers
Model 22 F for COUT GRM21BR60J226K C2012X5R0J226K JMK212BJ226K 10 F for CIN or COUT GRM21BR60J106K JMK212BJ106K C2012X5R0J106K Ceramic, X5R Ceramic, X5R Ceramic, X5R Murata Taiyo-Yuden TDK 6.3V 6.3V 6.3V 0805 (2012) 0805 (2012) 0805 (2012) Ceramic, X5R Ceramic, X5R Ceramic, X5R Murata TDK Taiyo-Yuden 6.3V 6.3V 6.3V 0805 (2012) 0805 (2012) 0805 (2012) Type Vendor Voltage Case Size Inch (mm)
Board Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the converters can be implemented by following a few simple design rules. 1. Place the converters, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the converter and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the converter by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the converter and filter capacitors together using generous component-side cop-
per fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the converter by giving it a low-impedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the converter circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter's own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio RF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noisesensitive circuitry in the system can be reduced through distance.
27
www.national.com
LP3970
Application Note 1 nVDD FLT
When I C commands are used to enable LDO 1 to 6 or Buck1, 2 the nVDD_FLT output momentarily glitches, see plot below.
2
Application Note 2 Back-Up Battery Switch
When operating from a backup battery the battery selection switch may latch up if the backup battery voltage has discharged below 2.0V. The circuit shown below will prevent back up battery from latching up under these conditions. D1 and D2 are silicon SMT diodes and the 10 k resistor can be adjusted for different capacity BU batteries however care should be taken not to exceed manufactures specification.
20137140
The nVDD_FLT signal can be deglitched using the following circuit. This will deglitch nVDD_FLT and allow the system designer to use I2C commands to turn the supplies on or off.
20137142
Application Note 3 VCC IO
The PXA27x power requirements document states VCC_IO shall be 200 mV of VCC_RTC when VCC_IO is active. The current LP3970 datasheet specification has VCC_RTC = 2.8V and VCC_IO = to 2.8V. The LP3970 does not incorporate circuitry for the RTC_LDO to tract VCC_IO. The LP3970 can accommodate VCC_IO voltages of no more then 3.0V. If a higher IO voltage is required an external low dropout regulator such as the LP3871 can be used to power VCC_RTC with the output voltage set to VCC_IO.
20137141
www.national.com
28
LP3970 Power Management Unit for Advanced Application Processor
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Pin LLP NS Drawing SQA48A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2. Leadfree products are RoHS compliant.
National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

▲Up To Search▲

Price & Availability of LP3970

	To Download LP3970 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .