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M50FW080
8 Mbit (1M x8, Uniform Block) 3V Supply Firmware Hub Flash Memory
FEATURES SUMMARY
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SUPPLY VOLTAGE - VCC = 3V to 3.6V for Program, Erase and Read Operations - VPP = 12V for Fast Program and Fast Erase (optional) TWO INTERFACES - Firmware Hub (FWH) Interface for embedded operation with PC Chipsets - Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility FIRMWARE HUB (FWH) HARDWARE INTERFACE MODE - 5 Signal Communication Interface supporting Read and Write Operations - Hardware Write Protect Pins for Block Protection - Register Based Read and Write Protection - 5 Additional General Purpose Inputs for platform design flexibility - Synchronized with 33MHz PCI clock PROGRAMMING TIME - 10s typical - Quadruple Byte Programming Option 16 UNIFORM 64 KByte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER - Embedded Byte Program and Block/Chip Erase algorithms - Status Register Bits PROGRAM and ERASE SUSPEND - Read other Blocks during Program/Erase Suspend - Program other Blocks during Erase Suspend FOR USE in PC BIOS APPLICATIONS ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 2Dh
Figure 1. Packages
PLCC32 (K)
TSOP32 (NB) 8 x 14mm
TSOP40 (N) 10 x 20mm
August 2004
1/47
M50FW080
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Figure 3. Table 1. Table 2. Figure 4. Figure 5. Figure 6. Logic Diagram (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Communications (FWH0-FWH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Identification Inputs (ID0-ID3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 12 . . . . 12 . . . . 12 . . . . 12
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Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 21 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 16. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 17. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10.A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 19. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 20. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 16.PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 35 Table 26. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 36 Figure 17.TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 37 Table 27. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 37 Figure 18.TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 38 Table 28. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 38 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 20.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 41
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Figure 21.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 42 Figure 22.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 43 Figure 23.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 24.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 45 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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SUMMARY DESCRIPTION
The M50FW080 is an 8 Mbit (1Mbit x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Two different bus interfaces are supported by the memory. The primary interface, the Firmware Hub (or FWH) Interface, uses Intel's proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50FW080 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.
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Figure 2. Logic Diagram (FWH Interface)
VCC VPP 4 ID0-ID3 5 FGPI0FGPI4 FWH4 CLK IC RP
VCC
Table 1. Signal Names (FWH Interface)
FWH0-FWH3 FWH4 ID0-ID3 Input/Output Communications Input Communication Frame Identification Inputs General Purpose Inputs Interface Configuration Interface Reset CPU Reset Clock Top Block Lock Write Protect Reserved for Future Use. Leave disconnected Supply Voltage Optional Supply Voltage for Fast Erase Operations Ground Not Connected Internally
4 FWH0FWH3 WP TBL
FGPI0-FGPI4 IC RP INIT CLK
M50FW080
TBL WP RFU
INIT
VPP
VSS
AI03979
VSS NC
Table 2. Signal Names (A/A Mux Interface) Figure 3. Logic Diagram (A/A Mux Interface)
IC A0-A10 DQ0-DQ7 Interface Configuration Address Inputs Data Inputs/Outputs Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast Program and Fast Erase Operations Ground Not Connected Internally
VCC VPP 11 A0-A10 8 DQ0-DQ7
G W RC RB
RC IC G W RP M50FW080 RB
RP VCC VPP VSS NC
VSS
AI03981
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M50FW080
Figure 4. PLCC Connections
A/A Mux
A8 A9 RP VPP VCC RC A10
A/A Mux
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
FGPI2 FGPI3 RP VPP VCC CLK FGPI4 1 32 FGPI1 FGPI0 WP TBL ID3 ID2 ID1 ID0 FWH0 IC (VIL) NC NC VSS VCC INIT FWH4 RFU RFU IC (VIH) NC NC VSS VCC G W RB DQ7 9 M50FW080 25 17 FWH1 FWH2 VSS FWH3 RFU RFU RFU A/A Mux DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
A/A Mux
AI04897
Note: Pins 27 and 28 are not internally connected.
Figure 5. TSOP32 Connections
NC NC NC NC IC (VIH) A10 RC VCC VPP RP A9 A8 A7 A6 A5 A4
NC NC NC VSS IC GPI4 CLK VCC VPP RP GPI3 GPI2 GPI1 GPI0 WP TBL
1
32
A/A Mux
INIT FWH4/LFRAME NC RFU RFU RFU RFU FWH3/LAD3 VSS FWH2/LAD2 FWH1/LAD1 FWH0/LAD0 ID0 ID1 ID2 ID3
G W NC DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
A/A Mux
8 9
M50FW080
25 24
16
17
AI09757B
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M50FW080
Figure 6. TSOP40 Connections
NC IC (VIH) NC NC NC NC A10 NC RC VCC VPP RP NC NC A9 A8 A7 A6 A5 A4
NC IC (VIL) NC NC NC NC FGPI4 NC CLK VCC VPP RP NC NC FGPI3 FGPI2 FGPI1 FGPI0 WP TBL
1
40
10 11
M50FW080
31 30
20
21
VSS VCC FWH4 INIT RFU RFU RFU RFU RFU VCC VSS VSS FWH3 FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3
VSS VCC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
A/A Mux
A/A Mux
AI03980
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M50FW080
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub (FWH) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions section, respectively, while the supply signals are discussed in the Supply Signal Descriptions section. Firmware Hub (FWH) Signal Descriptions For the Firmware Hub (FWH) Interface see Figure 2. and Table 1.. Input/Output Communications (FWH0-FWH3). All Input and Output Communication with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed on a bus. For an address bit to be `0' the pin can be left floating or driven Low, VIL; an internal pulldown resistor is included with a value of RIL. For an address bit to be `1' the pin must be driven High, V IH; there will be a leakage current of ILI2 through each pin when pulled to V IH; see Table 20.. By convention the boot memory must have address `0000' and all additional memories take sequential addresses starting from `0001'. General Purpose Inputs (FGPI0-FGPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V IL, or High, VIH. Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed. The state of the Interface Configuration, IC, should not be changed during operation. To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the pin should be driven High, VIH. An internal pull-down resistor is included with a value of R IL; there will be a leakage current of ILI2 through each pin when pulled to VIH; see Table 20.. Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP is set High, V IH, the memory is in normal operation. After exiting Reset mode, the memory enters Read mode. CPU Reset (INIT). The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed. When Top Block Lock, TBL, is set Low, V IL, Program and Block Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 14). Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 14) from being changed. When Write Protect, WP, is set Low, V IL, Program and Block Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is set High, VIH, the protection of the Block determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 15). Write Protect, WP, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or un-
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predictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected. Table 3. Block Addresses
Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh Block Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Block Type Top Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block
Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 3. and Table 2.. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A19). They are latched during any bus operation by the Row/Column Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory's Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfaces. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V CC becomes valid the Command Interface is reset to Read mode. A 0.1F capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both V CC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V PP < VPPLK Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When V PP = VCC Program and Erase operations take place as normal. When V PP = VPPH Fast Program (if A/A Mux interface is selected) and Fast Erase operations are used. Any other voltage input to VPP will result in undefined behavior and should not be used.
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VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the voltage measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but the signals and timings are completely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/Address Multiplexed (A/A Mux) Interface. See the sections: The Firmware Hub (FWH) Bus Operations and Address/Address Multiplexed (A/ A Mux) Bus Operations, for details of the bus operations on each interface. Firmware Hub (FWH) Bus Operations The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT) are available to put the memory into a known state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock rises and the correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7. See Table 4. and Figure 7., for a description of the Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the timings of the signals. Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock rises and the correct Start cycle is on FWH0FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0FWH3. The memory outputs Sync data until the wait-states have elapsed. See Table 5. and Figure 8., for a description of the Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the timings of the signals. Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory will tri-state the Input/Output Communication pins, FWH0FWH3. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately. Standby. When FWH4 is High, VIH, the memory is put into Standby mode where FWH0-FWH3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP, or CPU Reset, INIT, is Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory resets to Read mode upon return from Reset mode and the Lock Registers return to their default states regardless of their state before Reset, see Table 14.. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. Block Protection. Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming
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M50FW080
equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP) must be High, VIH, and Output Enable, G, Low, V IL, in order to perform a Bus Read operation. The Data Inputs/ Outputs will output the value, see Figure 14. and Table 24., for details of when the output becomes valid. Table 4. FWH Bus Read Field Definitions
Clock Cycle Number 1 Clock Cycle Count 1 Field FWH0FWH3 1101b Memory I/O I Description On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address phase is transferred starting with the most significant nibble first. Always 0000b (only single byte transfers are supported). The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle. Data transfer is two CLK cycles, starting with the least significant nibble.
Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, VIL. The Data Inputs/ Outputs are latched on the rising edge of Write Enable, W. See Figure 15. and Table 25., for details of the timing requirements. Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP is Low, VIL. RP must be held Low, V IL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation.
START
2
1
IDSEL
XXXX
I
3-9 10 11 12
7 1 1 1
ADDR MSIZE TAR TAR
XXXX 0000b 1111b 1111b (float) 0101b
I I I O
13-14
2
WSYNC
O
15
1
RSYNC
0000b
O
16-17
2
DATA
XXXX
O
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M50FW080
Clock Cycle Number 18 19 Clock Cycle Count 1 1
Field
FWH0FWH3 1111b 1111b (float)
Memory I/O O N/A
Description The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.
TAR TAR
Figure 7. FWH Bus Read Waveforms
CLK
FWH4
FWH0-FWH3 Number of clock cycles
START 1
IDSEL 1
ADDR 7
MSIZE 1
TAR 2
SYNC 3
DATA 2
TAR 2 AI03437
Table 5. FWH Bus Write Field Definitions
Clock Cycle Number 1 Clock Cycle Count 1 Field FWH0FWH3 1110b Memory I/O I Description On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address phase is transferred starting with the most significant nibble first. Always 0000b (single byte transfer). Data transfer is two cycles, starting with the least significant nibble. The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b, indicating a turnaround cycle. The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3.
START
2
1
IDSEL
XXXX
I
3-9 10 11-12 13 14 15 16 17
7 1 2 1 1 1 1 1
ADDR MSIZE DATA TAR TAR SYNC TAR TAR
XXXX 0000b XXXX 1111b 1111b (float) 0000b 1111b 1111b (float)
I I I I O O O N/A
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Figure 8. FWH Bus Write Waveforms
CLK
FWH4
FWH0-FWH3 Number of clock cycles
START 1
IDSEL 1
ADDR 7
MSIZE 1
DATA 2
TAR 2
SYNC 1
TAR 2 AI03441
Table 6. A/A Mux Bus Operations
Operation Bus Read Bus Write Output Disable Reset G VIL VIH VIH VIL or VIH W VIH VIL VIH VIL or VIH RP VIH VIH VIH VIL VPP Don't Care VCC or VPPH Don't Care Don't Care DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
Table 7. Manufacturer and Device Codes
Operation Manufacturer Code Device Code G VIL VIL W VIH VIH RP VIH VIH A19-A1 VIL VIL A0 VIL VIH DQ7-DQ0 20h 2Dh
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COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. After power-up or a Reset operation the memory enters Read mode. The commands are summarized in Table 9., Commands. The following text descriptions should be read in conjunction with Table 9.. Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 8.. Table 8. Read Electronic Signature
Code Manufacturer Code Device Code Address 00000h 00001h Data 20h 2Dh
Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data
in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 14.. Note that the Program command cannot change a bit set at `0' back to `1' and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to `1'. See Figure 19., for a suggested flowchart on using the Program command. Quadruple Byte Program Command. The Quadruple Byte Program Command can be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A10. Programming should not be attempted when V PP is not at V PPH. The operation can also be executed if VPP is below V PPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 8.. Note that the Quadruple Byte Program command cannot change a bit set to `0' back to `1' and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to `1'. See Figure 20., Quadruple Byte Program Flowchart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command.
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Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 14.. The Chip Erase command sets all of the bits in the memory to `1'. See Figure 22., for a suggested flowchart on using the Chip Erase command. Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the block is protected then the Block Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. During the Block Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 14.. The Block Erase command sets all of the bits in the block to `1'. All previous data in the block is lost. See Figure 22., for a suggested flowchart on using the Erase command. Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command. Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or Block Erase operation. One Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 14.. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Block Erase then the Program command will also be accepted; only the blocks not being erased may be read or programmed correctly. See Figure 21., and Figure 24., for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register.
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Table 9. Commands
Command Cycles Bus Write Operations 1st Addr X X X X X X X X X X X X X X X X X Data FFh 70h 90h 98h 40h 10h 30h 80h 20h 50h B0h D0h 00h 01h 60h 2Fh C0h PA PA A1 X BA PD PD PD 10h D0h A2 PD A3 PD A4 PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data
Read Memory Array Read Status Register Read Electronic Signature
1 1 1 1 2
Program 2 Quadruple Byte Program Chip Erase Block Erase Clear Status Register Program/Erase Suspend Program/Erase Resume 5 2 2 1 1 1 1 1 Invalid/Reserved 1 1 1
Note: X Don't Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block. Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued. Block Erase, Program. After these commands read the Status Register until the command completes and another command is issued. Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A 1, A2, A3 and A4 must be consecutive addresses differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another command is issued. Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes and another command is issued. Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to `0'. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved. Do not use Invalid or Reserved commands.
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STATUS REGISTER
The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The Status Register bits are summarized in Table 10.. The following text descriptions should be read in conjunction with Table 10.. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is `0', the Program/Erase Controller is active; when the bit is `1', the Program/Erase Controller is inactive. The Program/Erase Controller Status is `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is `1'. During Program and Erase operation the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is `1'. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is `0' the Program/Erase Controller is active or has completed its operation; when the bit is `1' a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block(s) and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Erase Status bit is `0' the memory has successfully verified that the block(s) has erased correctly; when the Erase Status bit is `1' the Program/Erase Controller has applied the maximum number of pulses to the block(s) and still failed to verify that the block(s) has erased correctly. Once the Erase Status bit is set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Program Status bit is `0' the memory has successfully verified that the byte has programmed correctly; when the Program Status bit is `1' the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed correctly. Once the Program Status bit is set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during a Program or Erase operation. When the VPP Status bit is `0' the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is `1' the V PP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected; Program and Erase operation cannot be performed. Once the VPP Status bit set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
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Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is `0' the Program/Erase Controller is active or has completed its operation; when the bit is `1' a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the ProTable 10. Status Register Bits
Operation Program active Program suspended Program completed successfully Program failure due to VPP Error Program failure due to Block Protection (FWH Interface only) Program failure due to cell failure Erase active Block Erase suspended Erase completed successfully Erase failure due to VPP Error Block Erase failure due to Block Protection (FWH Interface only) Erase failure due to failed cell(s) Bit 7 `0' `1 `1' `1' `1' `1' `0' `1' `1' `1' `1' `1' Bit 6 X(1) X(1) X(1) X(1) X(1) X(1) `0' `1' `0' `0' `0' `0' Bit 5 `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `1' Bit 4 `0' `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `0' Bit 3 `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' `0' Bit 2 `0' `1' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' Bit 1 `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0'
gram or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to `0' no Program or Block Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is `1' a Program or Block Erase operation has been attempted on a protected block. Once it is set to `1' the Block Protection Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail. Using the A/A Mux Interface the Block Protection Status bit is always `0'. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.
Note: 1. For Program operations during Erase Suspend Bit 6 is `1', otherwise Bit 6 is `0'.
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FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks, read the General Purpose Input pins and identify the memory using the Electronic Signature codes. See Table 11. for the memory map of the Configuration Registers. Lock Registers The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the protection of each block, the Write Lock Bit, the Read Lock Bit and the Lock Down Bit. The Lock Registers can be read and written, though care should be taken when writing as, once the Lock Down Bit is set, `1', further modifications to the Lock Register cannot be made until cleared, to `0', by a reset or power-up. See Table 12. for details on the bit definitions of the Lock Registers. Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, `1', the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, `0', the block is not write protected through the Lock Register and may be modified unless write protected through some other means. When V PP is less than VPPLK all blocks are protected and cannot be modified, regardless of the state of the Write Lock Bit. If Top Block Lock, TBL, is Low, V IL, then the Top Block (Block 15) is write protected and cannot be modified. Similarly, if Write Protect, WP, is Low, VIL, then the Main Blocks (Blocks 0 to 14) are write protected and cannot be modified. After power-up or reset the Write Lock Bit is always set to `1' (write protected). Read Lock. The Read Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, `1', the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, `0', read operations in the Block return the data programmed into the block as expected. After power-up or reset the Read Lock Bit is always reset to `0' (not read protected). Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, `1', further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock Down Bit is reset, `0', the Write Lock, Read Lock and Lock Down Bits can be changed.
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Table 11. Firmware Hub Register Configuration Map
Mnemonic T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK FGPI_REG MANUF_REG DEV_REG Register Name Top Block Lock Register (Block 15) Top Block [-1] Lock Register (Block 14) Top Block [-2] Lock Register (Block 13) Top Block [-3] Lock Register (Block 12) Top Block [-4] Lock Register (Block 11) Top Block [-5] Lock Register (Block 10) Top Block [-6] Lock Register (Block 9) Top Block [-7] Lock Register (Block 8) Top Block [-8] Lock Register (Block 7) Top Block [-9] Lock Register (Block 6) Top Block [-10] Lock Register (Block 5) Top Block [-11] Lock Register (Block 4) Top Block [-12] Lock Register (Block 3) Top Block [-13] Lock Register (Block 2) Top Block [-14] Lock Register (Block 1) Top Block [-15] Lock Register (Block 0) Firmware Hub (FWH) General Purpose Input Register Manufacturer Code Register Device Code Register Memory Address FBF0002h FBE0002h FBD0002h FBC0002h FBB0002h FBA0002h FB90002h FB80002h FB70002h FB60002h FB50002h FB40002h FB30002h FB20002h FB10002h FB00002h FBC0100h FBC0000h FBC0001h Default Value 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h N/A 20h 2Dh Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
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Firmware Hub (FWH) General Purpose Input Register The Firmware Hub (FWH) General Purpose Input Register holds the state of the Firmware Hub Interface General Purpose Input pins, FGPI0-FGPI4. When this register is read, the state of these pins is returned. This register is read-only and writing to it has no effect. The signals on the Firmware Hub Interface General Purpose Input pins should remain constant throughout the whole Bus Read cycle in order to guarantee that the correct data is read. Manufacturer Code Register Reading the Manufacturer Code Register returns the manufacturer code for the memory. The manufacturer code for STMicroelectronics is 20h. This register is read-only and writing to it has no effect. Device Code Register Reading the Device Code Register returns the device code for the memory, 2Dh. This register is read-only and writing to it has no effect.
Table 12. Lock Register Bit Definitions
Bit 7-3 `1' 2 Read-Lock `0' Bit Name Value Reserved Bus Read operations in this Block always return 00h. Bus read operations in this Block return the Memory Array contents. (Default value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a `1' is written to the Lock-Down bit it cannot be cleared to `0'; the bit is always reset to `0' following a Reset (using RP or INIT) or after power-up. Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). Program and Block Erase operations in this Block will set an error in the Status Register. The memory contents will not be changed. (Default value). Program and Block Erase operations in this Block are executed and will modify the Block contents. Function
`1' 1 Lock-Down `0' `1' 0 Write-Lock `0'
Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Register (T_MINUS15_LK).
Table 13. General Purpose Input Register Definition
Bit 7-5 `1' 4 FGPI4 `0' `1' 3 FGPI3 `0' `1' 2 FGPI2 `0' `1' 1 FGPI1 `0' `1' 0 FGPI0 `0' Input Pin FGPI0 is at VIL Input Pin FGPI1 is at VIL Input Pin FGPI0 is at VIH Input Pin FGPI2 is at VIL Input Pin FGPI1 is at VIH Input Pin FGPI3 is at VIL Input Pin FGPI2 is at VIH Input Pin FGPI4 is at VIL Input Pin FGPI3 is at VIH Bit Name Value Reserved Input Pin FGPI4 is at VIH Function
Note: Applies to the General Purpose Input Register (FGPI_REG).
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PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table 14.. Table 14. Program and Erase Times
Parameter Byte Program Quadruple Byte Program Chip Erase Block Program VPP = VCC VPP = 12V 5% Block Erase Program/Erase Suspend to Program pause (3) Program/Erase Suspend to Block Erase pause (3)
Note: 1. TA = 25C, VCC = 3.3V 2. This time is obtained executing the Quadruple Byte Program Command. 3. Sampled only, not 100% tested.
Interface
Test Condition
Min
Typ (1) 10
Max 200 200
Unit
s s
sec
A/A Mux A/A Mux A/A Mux
VPP = 12V 5% VPP = 12V 5% VPP = 12V 5%
10 9 0.1 (2) 0.4 0.75 1
5 5 8 10 5 30
sec sec sec sec
VPP = VCC
s s
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MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 15. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering Input or Output range 2 Supply Voltage Program Voltage Electrostatic Discharge Voltage (Human Body model) 3 Parameter Min. -65 Max. 150 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
See note 1 -0.50 -0.50 -0.6 -2000
ECOPACK (R)
VCC + 0.6 4 13 2000
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. Minimum voltage may undershoot to -2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for less than 20ns during transitions. 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 16. Operating Conditions
Symbol VCC TA Ambient Operating Temperature (Device Grade 1) 0 70 C Supply Voltage Ambient Operating Temperature (Device Grade 5) Parameter Min. 3.0 -20 Max. 3.6 85 Unit V C
Conditions summarized in Table 16., Table 17. and Table 18.. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 17. FWH Interface AC Measurement Conditions
Parameter Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 10 Unit pF ns V V
1.4
0.2 VCC and 0.6 VCC 0.4 VCC
Table 18. A/A Mux Interface AC Measurement Conditions
Parameter Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 30 Unit pF ns V V
10
0 to 3 1.5
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Figure 9. FWH Interface AC Testing Input Output Waveforms
0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform
IO < ILO
IO > ILO
IO < ILO
Output AC Tri-state Testing Waveform
AI03404
Figure 10. A/A Mux Interface AC Testing Input Output Waveform
3V 1.5V 0V
AI01417
Table 19. Impedance
Symbol CIN(1) CCLK(1) LPIN(2) Parameter Input Capacitance Clock Capacitance Recommended Pin Inductance Test Condition VIN = 0V VIN = 0V 3 Min Max 13 12 20 Unit pF pF nH
Note: 1. Sampled only, not 100% tested. 2. See PCI Specification. 3. TA = 25C, f = 1MHz.
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Table 20. DC Characteristics
Symbol VIH Parameter Input High Voltage A/A Mux VIL VIH(INIT) VIL(INIT) ILI(2) ILI2 RIL FWH Input Low Voltage A/A Mux INIT Input High Voltage INIT Input Low Voltage Input Leakage Current IC, IDx Input Leakage Current IC, IDx Input Pull Low Resistor FWH VOH Output High Voltage A/A Mux FWH VOL ILO VPP1 VPPH VPPLK(1) VLKO(1) ICC1 Output Low Voltage A/A Mux Output Leakage Current VPP Voltage VPP Voltage (Fast Program/Fast Erase) VPP Lockout Voltage VCC Lockout Voltage Supply Current (Standby) FWH FWH4 = 0.9 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz FWH4 = 0.1 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz VCC = VCC max, VPP = VCC f(CLK) = 33MHz IOUT = 0mA G = VIH, f = 6MHz Program/Erase Controller Active VPP > VCC VPP = VCC VPP = 12V 5% IOL = 1.8mA 0V VOUT VCC 3 11.4 1.5 1.8 2.3 100 0.45 10 3.6 12.6 V IOH = -100A IOL = 1.5mA VCC - 0.4 0.1 VCC V V IOH = -500A FWH FWH 0V VIN VCC IC, ID0, ID1, ID2, ID3 = VCC 20 0.9 VCC -0.5 1.35 -0.5 0.8 VCC + 0.5 0.2 VCC 10 200 100 V V V 0.7 VCC -0.5 VCC + 0.3 0.3 VCC V V Interface FWH Test Condition Min 0.5 VCC Max VCC + 0.5 Unit V
A A
k V
A
V V V V
A
ICC2
Supply Current (Standby) Supply Current (Any internal operation active) Supply Current (Read) Supply Current (Program/Erase) VPP Supply Current (Read/Standby) VPP Supply Current (Program/Erase active)
FWH
10
mA
ICC3 ICC4 ICC5(1) IPP IPP1(1)
FWH A/A Mux A/A Mux
60 20 20 400 40 15
mA mA mA
A
mA mA
Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
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Figure 11. FWH Interface Clock Waveform
tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC
AI03403
tLOW
0.4 VCC, p-to-p (minimum)
Table 21. FWH Interface Clock Characteristics
Symbol tCYC tHIGH tLOW Parameter CLK Cycle Time(1) CLK High Time CLK Low Time CLK Slew Rate peak to peak Max 4 V/ns Test Condition Min Min Min Min Value 30 11 11 1 Unit ns ns ns V/ns
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification.
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Figure 12. FWH Interface AC Signal Timing Waveforms
CLK tCHQV tCHQZ tCHQX FWH0-FWH3 VALID OUTPUT DATA FLOAT OUTPUT DATA tCHDX VALID VALID INPUT DATA
AI03405
tDVCH
Table 22. FWH Interface AC Signal Timing Characteristics
Symbol PCI Symbol tval ton toff tsu th Parameter Test Condition Min CLK to Data Out Max CLK to Active (Float to Active Delay) CLK to Inactive (Active to Float Delay) Input Set-up Time(2) Input Hold Time(2) Min Max Min Min 11 2 28 7 0 ns ns ns ns ns Value 2 Unit ns
tCHQV tCHQX(1) tCHQZ tAVCH tDVCH tCHAX tCHDX
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK.
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Figure 13. Reset AC Waveforms
RP, INIT tPLPH W, G, FWH4 tPHWL, tPHGL, tPHFL
tPLRH
RB
AI03420
Table 23. Reset AC Characteristics
Symbol tPLPH tPLRH Parameter RP or INIT Reset Pulse Width Program/Erase Inactive RP or INIT Low to Reset Program/Erase Active RP or INIT Slew Rate(1) tPHFL tPHWL tPHGL RP or INIT High to FWH4 Low RP High to Write Enable or Output Enable Low Rising edge only FWH Interface only A/A Mux Interface only Max Min Min Min 30 50 30 50 Test Condition Min Max Value 100 100 Unit ns ns
s
mV/ns
s s
Note: 1. See Chapter 4 of the PCI Specification.
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Figure 14. A/A Mux Interface Read AC Waveforms
tAVAV A0-A10 tAVCL tCLAX RC tCHQV G tGLQV tGLQX DQ0-DQ7 tGHQZ tGHQX VALID ROW ADDR VALID COLUMN ADDR VALID tAVCH tCHAX NEXT ADDR VALID
W tPHAV RP
AI03406
Table 24. A/A Mux Interface Read AC Characteristics
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV(1) tGLQV(1) tPHAV tGLQX tGHQZ tGHQX Parameter Read Cycle Time Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC high RC High to Column Address Transition RC High to Output Valid Output Enable Low to Output Valid RP High to Row Address Valid Output Enable Low to Output Transition Output Enable High to Output Hi-Z Output Hold from Output Enable High Test Condition Min Min Min Min Min Max Max Min Min Max Min Value 250 50 50 50 50 150 50 1 0 50 0 Unit ns ns ns ns ns ns ns
s
ns ns ns
Note: 1. G may be delayed up to tCHQV - t GLQV after the rising edge of RC without impact on tCHQV.
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Figure 15. A/A Mux Interface Write AC Waveforms
Write erase or program setup A0-A10 R1 C1 tCLAX tAVCL RC tWHWL tWLWH W tVPHWH G tWHRL RB tQVVPL VPP tDVWH DQ0-DQ7 DIN1 DIN2 tWHDX VALID SRD
AI04194
Write erase confirm or valid address and data R2 tAVCH tCHAX C2
Automated erase or program delay
Read Status Register Data
Ready to write another command
tCHWH
tWHGL
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Table 25. A/A Mux Interface Write AC Characteristics
Symbol tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPHWH(1) tWHGL tWHRL tQVVPL(1,2) Parameter Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC High RC High to Column Address Transition Write Enable High to Write Enable Low RC High to Write Enable High VPP High to Write Enable High Write Enable High to Output Enable Low Write Enable High to RB Low Output Valid, RB High to VPP Low Test Condition Min Min Min Min Min Min Min Min Min Min Min Min Min Value 100 50 5 50 50 50 50 100 50 100 30 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (V PP < 3.6V).
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PACKAGE MECHANICAL
Figure 16. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
D D1
1N
A1 A2
B1 E2 E3 E1 E e F 0.51 (.020) 1.14 (.045) D3 R CP A E2 B
D2
D2
PLCC-A
Note: Drawing is not to scale.
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M50FW080
Table 26. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B B1 CP D D1 D2 D3 E E1 E2 E3 e F R N 0.89 32 10.16 1.27 7.62 12.32 11.35 4.78 - 14.86 13.89 6.05 - - 0.00 - Min 3.18 1.53 0.38 0.33 0.66 Max 3.56 2.41 - 0.53 0.81 0.10 12.57 11.51 5.66 - 15.11 14.05 6.93 - - 0.13 - 0.035 32 0.400 0.050 0.300 0.485 0.447 0.188 - 0.585 0.547 0.238 - - 0.000 - Typ Min 0.125 0.060 0.015 0.013 0.026 Max 0.140 0.095 - 0.021 0.032 0.004 0.495 0.453 0.223 - 0.595 0.553 0.273 - - 0.005 - inches
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Figure 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 27. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 0.050 0.950 0 0.170 0.100 Min Max 1.200 0.150 1.050 5 0.270 0.210 0.100 13.800 12.300 0.500 - 7.900 0.500 32 14.200 12.500 - 8.100 0.700 32 0.0197 0.5433 0.4843 - 0.3110 0.0197 0.0020 0.0374 0 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 5 0.0106 0.0083 0.0039 0.5591 0.4921 - 0.3189 0.0276 inches
B C CP D D1 e E L N
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M50FW080
Figure 18. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 28. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 e E L 0.500 19.800 18.300 - 9.900 0.500 0 40 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.100 20.200 18.500 - 10.100 0.700 5 40 0 1 1 - 0 0 0 0 0 0 0 Typ Min Max 0 0 0 0 0 0 1 1 - 0 0 5 inches
N
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M50FW080
PART NUMBERING
Table 29. Ordering Information Scheme
Example: Device Type M50 = Flash Memory for PC BIOS Architecture F = Firmware Hub Interface Operating Voltage W = VCC = 3.0 to 3.6V Device Function 080 = 8 Mbit (1Mbx8), Uniform Blocks Package K = PLCC32 NB = TSOP32: 8 x 14mm N = TSOP40: 10 x 20mm Device Grade 5 = Temperature range -20 to 85 C. Device tested with standard test flow 1 = Temperature range 0 to 70 C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free M50FW080 N 5 T G
Devices are shipped from the factory with the memory content bits erased to '1'.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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APPENDIX A. FLOWCHARTS AND PSEUDO CODES
Figure 19. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
Write Address and Data
Program command: - Write 40h or 10h - Write Address and Data (memory enters read status state after the Program command)
NO Read Status Register Suspend NO YES Suspend Loop
do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES FWH/LPC Interface Only SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
If SR3 = 1, - Enter the "VPP invalid" error handler
NO
Program Error (1, 2)
If SR4 = 1, - Enter the "Program error" error handler
NO
Program to Protected Block Error (1, 2)
If SR1 = 1, - Enter the "Program to protected block" error handler
AI08425B
Note: 1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 20. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
Quadruple Byte Program command: - write 30h - write Address 1 & Data 1 (3) - write Address 2 & Data 2 (3) - write Address 3 & Data 3 (3) - write Address 4 & Data 4 (3) (memory enters read status state after the Quadruple Byte Program command)
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3) do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
NO Read Status Register Suspend NO YES Suspend Loop
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES End
NO
VPP Invalid Error (1, 2)
If SR3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If SR4 = 1, Program error: - error handler
AI08437B
Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
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Figure 21. Program Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
SR7 = 1 YES SR2 = 1 YES Write a read Command
NO
while SR7 = 0
NO
Program Complete
If SR2 = 0 Program completed
Read data from another address
Write D0h
Write FFh
Program Continues
Read Data
Program/Erase Resume command: - write D0h to resume the program - if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI08426B
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used.
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Figure 22. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 80h
Chip Erase command: - write 80h - write 10h (memory enters read Status Register after the Chip Erase command)
Write 10h do: - read Status Register
Read Status Register
SR7 = 1
NO
while SR7 = 0
YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES End
AI08428B
NO
VPP Invalid Error (1)
If SR3 = 1, VPP invalid error: - error handler
NO
Command Sequence Error (1)
If SR4, SR5 = 1, Command sequence error: - error handler
NO
Erase Error (1)
If SR5 = 1, Erase error: - error handler
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 23. Block Erase Flowchart and Pseudo Code
Start
Write 20h/32h
Write Block Address and D0h
Block Erase command: - Write 20h/32h - Write block Address and D0h (memory enters read Status Register after the Block Erase command)
Read Status Register
NO Suspend
YES
do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
SR7 = 1
NO
Suspend Loop
YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES FWH/LPC Interface Only SR1 = 0 YES End
AI08424B
NO
VPP Invalid Error (1)
If SR3 = 1, - Enter the "VPP invalid" error handler
NO
Command Sequence Error (1)
If SR4, SR5 = 1, - Enter the "Command sequence"error handler
NO
Erase Error (1)
If SR5 = 1, - Enter the "Erase Error" error handler
NO
Erase to Protected Block Error (1)
If SR1 = 1, - Enter the "Erase to protected block" error handler
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 24. Erase Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
SR7 = 1 YES SR6 = 1 YES
NO
while SR7 = 0
NO
Erase Complete
If SR6 = 0, Erase completed
Read data from another block/sector or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume erase - if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI08429B
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REVISION HISTORY
Table 30. Document Revision History
Date April 2001 18-May-2001 22-Jun-2001 6-Jul-2001 30-Jan-2002 01-Mar-2002 12-Mar-2002 19-May-2004 19-Aug-2004 Version -01 -02 -03 -04 -05 -06 -07 8.0 9.0 First Issue Document type: from Product Preview to Preliminary Data PLCC32 package added Note 2 changed (Table 15., Absolute Maximum Ratings) Document promoted from Preliminary Data to Full Data Sheet RFU pins must be left disconnected Specification of PLCC32 package mechanical data revised TSOP32 package added. Part numbering information updated. Flow-chart illustrations, in Appendix, updated. Document reformatted Pins 2 and 5 of the TSOP32 Connections illustration corrected Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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