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MK2771-15
VCXO AND SET-TOP CLOCK SOURCE
Description
The MK2771-15 is a low-cost, low-jitter, high-performance VCXO and clock synthesizer designed for set-top boxes. The on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3 V input voltage to cause the output clocks to vary by 100 ppm. Using ICS' patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 13.5 MHz pullable crystal input to produce multiple output clocks including two selectable processor clocks, a selectable audio clock, two communications clocks, and three fixed clocks. All clocks are frequency locked to the 27.00 MHz output (and to each other) with zero ppm error, so any output can be used as the VCXO output.
Features
* * * * * * * * * * * *
Packaged in 28-pin SSOP Available in Pb-free package Ideal for systems using Oak's MPEG decoders On-chip patented VCXO with pull range of 200 ppm VCXO tuning voltage of 0 to 3 V Processor frequencies include 33.3, 40, 50, 66.6, 81, and 100 MHz Audio clocks of 8.192 MHz, 11.2896 MHz, 12.288 MHz and 18.432 MHz Zero ppm synthesis error in all clocks (all exactly track 27 MHz VCXO) Uses an inexpensive 13.5 MHz pullable crystal Full CMOS output swings with 25 mA output drive capability at TTL levels Advanced, low-power, sub-micron CMOS process 5 V operating voltage with 3.3 V capable I/O
Block Diagram
VDD VDDIO
PCS2:0 ACS1:0 SC VIN X1 13.5 MHz pullable crystal X2
3 2 Clock Synthesis Circuitry Voltage Controlled Crystal Oscillator
2
Processor Clocks Audio Clock
2
Comm. Clocks 54.00 MHz
divide by 2 divide by 2
27.000 MHz 13.500 MHz
GND
MDS 2771-15 F I n t e gra te d C i r c u i t S y s t e m s
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525 Race Stre et, San Jo se, CA 9 5126
Revision 032204 te l (40 8) 2 97-12 01
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MK2771-15 VCXO AND SET-TOP CLOCK SOURCE
Pin Assignment
PCS0 X2 X1 VDD VDD VIN VDDIO VDD SC GND PCLK1 PCLK2 PCS1 ACLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ACS1 ACS0 54M 27M GND CCLK1 VDD VDD PCS2 GND GND CCLK2 13.5M DC
Processor Clock Select Table (MHz)
PCS2 PCS1 PCS0 PCLK1 PCLK2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
27.500 33.333 33.326 50.000 32.400 40.000 TEST TEST
OFF 66.666 83.314 100.000 81.000 33.333 TEST TEST
Audio Clock Table
ACS1 ACS0 ACLK (MHz)
0 0 1 1
0 1 0 1
8.192 11.2896 12.288 18.432
Comm Clock Table (MHz)
SC CCLK1 CCLK2
0 M 1
18.432 11.0592 11.0592
24.576 18.432 24.576
0 = connect directly to ground 1 = connect directly to VDDIO M = leave floating or unconnected
MDS 2771-15 F In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 032204 tel (4 08) 297-1 201
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MK2771-15 VCXO AND SET-TOP CLOCK SOURCE
Pin Descriptions
Pin Number 1 2 3 4, 5, 8 6 7 9 10, 18, 19, 24 11 12 13 14 15 16 17 20 21, 22 23 25 26 27 28 Pin Name PCS0 X2 X1 VDD VIN VDDIO SC GND PCLK1 PCLK2 PCS1 ACLK DC 13.5M CCLK2 PCS2 VDD CCLK1 27M 54M ACS0 ACS1 Pin Type Input Pin Description
Processor clock select 0. Selects PCLKs on pins 11 and 12. See table above. Internal pull-up resistor. XO Crystal connection. Connect to a pullable 13.5 MHz crystal. XI Crystal connection. Connect to a pullable 13.5 MHz crystal. Power Connect to +5 V. Input Voltage input to VCXO. Zero to 3 V signal which controls the frequency of the VCXO. Power Connect to +3.3 V or +5 V. Amplitude of inputs must, and outputs will, match this. Tri-level input Communications clock select pin. Biased to M level if floating Power Connect to ground. Output Output Input Output -- Output Output Input Power Output Output Output Input Input Processor clock output number 1. Determined by status of PCS2:0. Processor clock output number 2. Determined by status of PCS2:0. Processor clock select 1. Selects PCLKs on pins 11 and 12. See table above. Internal pull-up resistor. Audio clock output. Determined by status of ACS1, ACS0 per table above. Don't Connect anything to this pin. 13.50 MHz VCXO clock output. Communications clock output 2 determined by status of SC per table above. Processor clock select 2. Selects PCLKs on pins 11 and 12. See table above. Internal pull-up resistor. Connect to +5 V. Communications clock output 1 determined by status of SC per table above. 27.00 MHz VCXO clock output. 54.00 MHz VCXO clock output. Audio clock select 0. Selects ACLK on pin 14. See table above. Internal pull-up resistor. Audio clock select 1. Selects ACLK on pin 14. See table above. Internal pull-up resistor.
MDS 2771-15 F In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 032204 tel (4 08) 297-1 201
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MK2771-15 VCXO AND SET-TOP CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2771-15. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND) Inputs and Clock Outputs (referenced to GND) Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Operating Voltage Input High Voltage, X1 pin only Input Low Voltage, X1 pin only Input High Voltage, except SC and PCS2 Input Low Voltage, except SC and PCS2 Input High Voltage, SC and PCS2 only Input Low Voltage, SC and PCS2 only Output High Voltage Output Low Voltage Output High Voltage, CMOS Level Operating Supply Current Short Circuit Current
Symbol
VDD VDDIO VIH VIL VIH VIL VIH VIL VOH VOL VOH IDD + IDDIO (3.3 V) IOS
Conditions
All inputs/outputs
Min.
4.75 3.15 3.5 2
Typ.
Max.
5.25 5.25
Units
V V V V V
2.5 2.5 1.5
0.8 VDDIO-0.5 0.5 IOH = -25 mA IOL = 25 mA IOH = -8 mA No load, Note 1 Each output 2.4 - VDDIO-0.4 46+27 100 - 0.4
V V V V V V mA mA
MDS 2771-15 F In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 032204 tel (4 08) 297-1 201
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MK2771-15 VCXO AND SET-TOP CLOCK SOURCE
Parameter
Input Capacitance, except X1 Frequency Synthesis Error VIN, VCXO Control Voltage
Symbol
CIN
Conditions
Except X1, X2 All clocks
Min.
Typ.
7
Max.
0
Units
pF ppm V
0
3
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V, Ambient Temperature 0 to +70 C
Parameter
Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter, short term VCXO Pullability
Symbol
tOR tOF tOD tja tja
Conditions
0.8 to 2.0 V, no load 2.0 to 0.8 V, no load At VDDIO/2
Min.
13.500000
Typ.
1.5 1.5
Max.
Units
MHz ns ns
40
50 300
60
% ps
Note 2
-100
100
ppm
Note 1: With PCLK at 100 MHz. Note 2: With a pullable crystal that conforms to ICS' specifications.
Pullable Crystal Specifications
Frequency Correlation (load) Capacitance CO/C1 ESR Operating Temperature Initial Accuracy Temperature plus Aging Stability 13.500000 MHz 14 pF 240 max. 35 max. 0 to 70C 20 ppm 50 ppm
MDS 2771-15 F In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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MK2771-15 VCXO AND SET-TOP CLOCK SOURCE
Package Outline and Package Dimensions (28-pin SSOP)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
28
INDEX AREA
E1
E
12 D
A A1 A2 b c D E E1 e L
1.35 1.75 0.102 0.254 -1.50 0.203 0.305 0.191 0.254 9.804 10.008 5.791 6.198 3.810 3.988 .635 Basic 0.406 1.270 0 8
0.053 0.069 0.004 0.010 -.059 0.008 0.012 0.007 0.010 0.386 0.394 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8
A2 A1
A c
- Ce
b SEATING PLANE
aaa C
L
Ordering Information
Part / Order Number
MK2771-15R MK2771-15RTR MK2771-15RLF MK2771-15RLFTR
Marking
MK2771-15 MK2771-15 MK2771-15LF MK2771-15LF
Shipping packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
Note: "LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2771-15 F In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 032204 tel (4 08) 297-1 201
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