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MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
October 1987 Revised May 2002
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.
Features
s Wide supply voltage range: 3.0V to 15V s Guaranteed noise margin: 1.0V s High noise immunity: 0.45 VCC (typ.) s Low power: TTL compatibility: Fan out of 2 driving 74L s Low power consumption: 10 nW/package (typ.) s The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Order Number MM74C86M MM74C86N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Truth Table
Inputs A L L H H
H = HIGH Level L = LOW Level
Output B L H L H Y L H H L
Top View
(c) 2002 Fairchild Semiconductor Corporation
DS005887
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MM74C86
Absolute Maximum Ratings(Note 1)
Voltage at any Pin (Note 1) Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Package Small Outline Operating Range (VCC) 700 mW 500 mW 3.0V to 15V
Absolute Maximum (VCC) Lead Temperature (Soldering, 10 seconds)
18V 260C
-0.3V to VCC + 0.3V -55C to +125C -65C to +150C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation.
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5.0V, IO = +10 A VCC = 10V, IO = +10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = 360 A VCC = 5.0V, VOUT = 0V TA = 25C VCC = 10V, VOUT = 0V TA = 25C VCC = 5.0V, VOUT = VCC TA = 25C VCC = 10V, VOUT = VCC TA = 25C 2.4 0.4 VCC-1.5 0.8 -1.0 0.005 -0.005 0.01 15 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V A A A V V V V Min Typ Max Units
CMOS/LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) -1.75 -8.0 1.75 8.0 -3.3 -15 3.6 16 mA mA mA mA
AC Electrical Characteristics (Note 2)
TA = 25C, CL = 50 pF, unless otherwise specified Symbol Parameter tpd CIN CPD Propagation Time to Logical "1" or "0" Input Capacitance Power Dissipation Capacitance VCC = 5.0V VCC = 10V (Note 3) Per Gate (Note 4) Conditions Min Typ 110 50 5.0 20 Max 185 90 Units ns pF pF
Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note-- AN-90.
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MM74C86
Typical Performance Characteristics
Propagation Delay Time vs Load Capacitance
Test Circuits and Waveforms
Delays Measured with Input tr, tf = 20 ns
FIGURE 1. AC Test Circuit
FIGURE 2. Switching Time Waveforms
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MM74C86
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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