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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
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Advanced, Catalog Speech Processor for High-Quality Sound, Capable of Unlimited Speech Duration Using External Memory Operates up to 12.32 MIPS Supports High-Quality Algorithms Such as MELP (1.0 Kbps - 3.5 Kbps at 8 kHz), CELP (3.0 Kbps - 11.2 kHz at 8 kHz Sampling Rate), ADPCM, Single Channel FM With CELP or MELP Speed and Pitch Shifting in MELP for Various Voice Effects Six Level Digital Gain Control 4 User Configurable I/O's
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Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Three Reduced Power Standby Modes, Less Than 10 A in Deep-Sleep Mode Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Direct Speaker Drive (32 ) (PDM) Interrupt Driven, 4- or 8-Bit Parallel Data Transfer Protocol Available in Die Form or 64-Pin PM Package
description
The MSP53C691 is a standard slave synthesizer from Texas Instruments that accepts compressed speech data from other microprocessors/microcontrollers and converts it to speech. This allows the TI MSP53C691 to be used with a master microprocessor/microcontroller in various speech-related products such as security systems, learning aids, games, and toys. High quality, low bit-rate coders, easy interface with the master microcontroller, digital gain control, low power sleep mode, and low voltage operation makes this device ideal for products requiring long duration speech, less development cycle times, and peripheral device control through the slave device. This device supports several speech synthesis algorithms that permit tradeoffs to meet the price performance requirements of various markets. The MSP53C691 implements a unique feature of playing a single channel FM music along with CELP or MELP speech data concurrently. This feature allows the user to speak a certain phrase in MELP or CELP with single channel music in the background. The MSP53C691 is optimized to support a 4-bit wide data transfer protocol. The device has two status bits and three control bits that control the communication protocol between the master and the slave. The MSP53C691 also has 1 bit (command/data) which differentiates between a command or speech data feeding into the slave. In 4-bit mode, various commands are sent to the slave during speech to perform various tasks. The MSP53C691 also supports the 8-bit wide data transfer but the support for commands is disabled during speaking-a-phrase. When speaking-a-phrase in 8-bit mode is complete, the MSP53C691 switches back to the 4-bit mode to receive the next command. Switching between 4-bit mode or 8 bit mode is permitted between speech data files.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
pin assignments
MSP53C691 PM PACKAGE (TOP VIEW)
V SS NC NC NC NC NC NC NC NC NC NC NC NC NC VDD VDD
R/W STROBE OUTRDY INRDY
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
NC V SS VSS DACP VDD DACM VDD PD4 PD5 PD6 PD7 DATA0 DATA1 DATA2 DATA3 DATA/COMMAND (DATA4) DATA5 DATA6 DATA7
TEST SCANOUT SYNC SCANCLK SCANIN RESET PLL OSCIN OSCOUT VSS
10 11 12 13 14 15
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC - No internal connection NOTE: Pin 35 is DATA4 in 8-bit mode, or DATA/COMMAND in 4-bit mode.
2
NC NC NC NC NC NC NC NC NC NC NC NC NC NC V DD
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
functional block diagram
VSS 4 Scan Interface Break Point Emulation OTP Program Serial Comm. Power (EP)ROM Test-Area (reserved) User ROM INT vectors 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF VDD 5 PG0 SCANIN G port O Data 0x2C MASTER/SLAVE
SCANOUT SCANCLK
Comparator 1 Bit: PD5 vs PD4 + - PD0 INRDY
SYNC TEST
SLAVE LOGIC
Core DACP DACM DAC 32 PDM Initialization Logic 0x30 Instr. Decoder PCU RESET CU TIMER1 OSC Reference Resistor Trimmed 32 kHz nominal OSCIN OSCOUT Crystal Referenced 32.768 kHz PLL PLL Filter or or Prog. Counter Unit Computational Unit PD3 PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F 0x3D 0x38 C port I/O Data 0x10 Control 0x14 PA0-7 PC0-7 D port I/O Data 0x18 PD2
PD1 Int 3
OUTRDY
Control 0x1C Int 4
STROBE R/W
PD4-7
TIMER2
Clock Control Gen. Control
Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
BUS DRIVER DATA0-7
A port I/O RAM 640 x 17 bit (data) Data 0x00 Control 0x04
LATCH
0x000 to 0x027F
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
Terminal Functions
NAME DATA0-DATA3 DATA4 or DATA/COMMAND DATA5-DATA7 INRDY PIN NO. 39-36 35 PAD NO. 25-22 21 I/O I/O I/O DESCRIPTION Data bits 0 through 3 (in 4-bit or 8-bit mode) Data bit 4 (in 8-bit mode) Data/command control bit (in 4-bit mode). Low signal indicates command and high signal indicates data. Data bits 5 through 7 (8-bit mode only) Not used (4-bit mode only) An output signal from the slave to the microcontroller. A low signal indicates that the MSP53C691 is ready to accept data or command. A high signal indicates that the MSP53C691 is busy and the microcontroller must not write any data or command to it. An output signal from the slave to the microcontroller. A low signal indicates that the MSP53C691 is ready to send data or command to the microcontroller. General-purpose I/O bus An input signal to the slave from the microcontroller. Read/write select signal which is set high for read operations or set low for write operations by the microcontroller. An input signal to the slave from the microcontroller. STROBE sequences read or write operations in conjunction with the R/W signal. This signal is pulsed high-low-high for read or write operations sequencing. Reference Oscillator Signals OSCOUT OSCIN PLL SCANIN SCANOUT SCANCLK SYNC TEST DACP DACM RESET VDD VSS 15 14 13 11 8 10 9 7 47 45 12 1, 2, 31, 44, 46 16, 48, 49, 64 15 14 13 39 35 38 37 36 33 31 12 1, 2, 17, 30, 32 16, 34, 35, 36 O I O I O I I I O O I -- -- Output of resistor/crystal oscillator Input to resistor/crystal oscillator Output of phase-lock-loop filter Scan Port Control Signals Scan port data input Scan port data output Scan port clock Scan port synchronization C604: test modes Digital-to-Analog Sound Output Digital-to-analog plus output (+) Digital-to-analog minus output(-) Initialization Device initialization Power Signals Processor power, 5 V nominal supply voltage Ground pin
34-32 6
20-18 6
I/O O
OUTRDY PD4-PD7 R/W STROBE
5 43-40 3 4
5 29-26 3 4
O I/O I I
All pins must be N.C. Marked pins are VDD and VSS connections which service the DAC circuitry. These pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required.
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
MSP53C691 (4-bit mode) Number of data lines Number of control lines Number of status lines Number of general-purpose I/O lines Support for commands (while speaking) VDD VDD 4 3 (strobe, R/W, data/command) 2 (INRDY, OUTRDY) 4 Yes
MSP53C691 (8-bit mode) 8 2 (strobe, R/W) 2 (INRDY, OUTRDY) 4 No
100 k (each) Master
4.7 k 100 k
4.7 k 4.7 k MSP53C691 INRDY OUTRDY R/W STROBE
DATA(0-3)
4
DATA(0-3) DATA/COMMAND RESET
NOTE: STROBE R/W RESET DATA0-DATA3 PD4-PD7 DACP DACM DATA/COMMAND
Active low strobe signal from microcontroller Read/write signal from microcontroller Active low reset signal from microcontroller Data bits 0 through 3 General-purpose I/O bus Output to speaker/amplifier Output to speaker/amplifier This bit determines if the data sent by the microcontroller is data or command.
Figure 1. MSP53C691 Interfacing Diagram--4-Bit Mode
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
VDD VDD 100 k (each) Master 4.7 k 4.7 k 4.7 k MSP53C691 INRDY OUTRDY R/W STROBE DATA (0-7) DATA (0-7) RESET
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NOTE: STROBE: R/W: RESET INRDY: OUTRDY: DATA0-DATA7 PD4-PD7 DACP DACM
Active low strobe signal from microcontroller Read/write signal from microcontroller Active low reset signal from microcontroller. Active low indicates that the MSP53C691 is ready to accept data. Active low indicates that the MSP53C691 is ready to send data. Data bits 0 through 7 General-purpose I/O bus Output to speaker/amplifier Output to speaker/amplifier
Figure 2. MSP53C691 Interfacing Diagram--8-Bit Mode
read operation by the master
The process for the read operation by the master is the same in either 4-bit or 8-bit mode. The read operation by the master happens when the slave wants to send something to the master. The read process is initiated by the slave by pulling OUTRDY low when it is ready. The following events take place during the read operation:
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The MSP53C691 puts the data to be sent to the master on the internal bus. The MSP53C691 sets OUTRDY low to indicate that it is ready to send data to the microcontroller. The microcontroller sets R/W high to indicate a read operation. The microcontroller sets STROBE low. The data is available on the external data-bus at this point. The microcontroller reads the data from the bus. The microcontroller sets STROBE high. The MSP53C691 also pulls OUTRDY high at the rising edge of STROBE. The data is taken from the external data-bus after STROBE goes high.
The microcontroller should latch or read in the data while STROBE is low. When the microcontroller sets STROBE high, the MSP53C691 sets OUTRDY high to indicate that the data has been successfully transferred. Figure 3 shows the sequence of events of the read operation.
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
read operation by the master (continued)
a) Sequence of events for a single read operation: OUTRDY R/W STROBE DATA COMMAND/DATA
b) Read--Two speech data transfer sequences: OUTRDY R/W STROBE DATA COMMAND/DATA
Figure 3. Data Transfer - Read
write operation by the master
The process for the write operation by the master is the same in either 4-bit or 8-bit mode. The write operation by the master happens when the slave is ready to request data or command from the master. The write process is initiated by the slave by pulling INRDY low when the slave is ready to receive data. The following events take place during the write operation:
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The MSP53C691 sets INRDY low to indicate that it is ready to receive data from the microcontroller. The microcontroller sets R/W low to indicate a write operation. The microcontroller puts the data in the external data-bus. The microcontroller sets STROBE low after the data is valid. The microcontroller sets STROBE high after a minimum of 300 ns. The MSP53C691 also pulls INRDY high at the rising edge of STROBE. The data is latched in the MSP53C691 at the rising edge of STROBE.
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
write operation by the master (continued)
When the microcontroller sets STROBE high, the MSP53C691 sets INRDY high to indicate that the MSP53C691 is not ready to receive any more data.
a) Sequence of events for a single write operation
R/W STROBE INRDY DATA COMMAND/DATA
b) Write--Two speech data transfer sequences R/W STROBE INRDY DATA COMMAND/DATA
Figure 4. Data Transfer - Write
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS . 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
recommended operating conditions
MIN Supply voltage, VDD (with respect to VSS) CPU clock rate, f(CPU) (as programmed) Load resistance between DACP and DACM, R(DAC) Operating free-air temperature, TA Device functionality 3 64 32 0 70 MAX 5.2 12,320 UNIT V kHz C
timing requirements
MIN t(RESET) tw1 tw2 Reset pulsed low, while 'C691 has power applied Pulse width required prior to a negative transition at pin (PD3 or PD5 interrupt) Pulse width required prior to a positive transition at pin (PD2 or PD4 interrupt) 100 2 2 MAX UNIT ns 1/FCPU 1/FCPU
RESET
t(RESET)
Figure 5. Initialization Timing Diagram
tw1 (PD3, PD5, or F port)
tw1 tw2 (PD2, or PD4)
tw2
Figure 6. MSP53C691 External Interrupt Pin Pulse Width Requirements tw1 and tw2
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MSP53C691 MIXED-SIGNAL PROCESSOR
SPSS030A - DECEMBER 2000 - REVISED FEBRUARY 2001
dc electrical characteristics over recommended operating free-air temperature range, TA = 0C - 70C (unless otherwise noted)
PARAMETER VDD = 3 V RESET Threshold changes VDD = 5.2 V VDD = 3 V VDD = 4.5 V VDD = 5.2 V VDD = 3 V VDD = 4.5 V VDD = 5.2 V VOH = 4 V TEST CONDITIONS Positive going threshold Negative going threshold Hysteresis Positive going threshold Negative going threshold Hysteresis 2 3 3.5 0 0 0 VIH High-level High level input voltage MIN TYP 2.4 1.8 0.6 3.3 2.9 0.4 3 4.5 5.2 1 1.5 1.7 -2 mA V V V V MAX UNIT
VIL
Low-level Low level input voltage High-level output current per pin of I/O port Low-level output current per pin of I/O port High-level output DAC current Low-level output DAC current Input leakage current Standby current Operating current Supply current Input offset voltage F port pullup resistance Trim deviation Voltage deviation Temperature deviation Resistance deviation
IOH
IOL IOH (DAC) IOL (DAC) Ilkg I(STANDBY) IDD I(SLEEP-deep) I(SLEEP-mid) I(SLEEP-light) VIO R(PULLUP) f(RTO t i ) (RTO-trim) f(RTO lt) (RTO-volt) f(RTO t ) (RTO-temp) f(RTO ) (RTO-res)
VDD = 4.5 V
VOL = 0.5 V VOH = 4 V VOL = 0.5 V
5
mA
-10 20 1 0.05 10 10 60 100 50
mA mA A A mA A mV k
Excludes OSCIN RESET is low VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 5 V VDD = 4.5 V, TA = 25C, f(RTO) = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 k, VDD = 3.5 to 5.2 V, f(RTO) = 8.192 MHz (PLL setting = 7 Ch) R(RTO) = 470 k, R(RTO) = 470 k, FCLOCK = 12.32 MHz DAC off, ARM set, DAC off, DAC off, ARM set, ARM clear, OSC disabled OSC enabled OSC enabled
15 0.05 40 60 25 70 150 1% TA = 25C, 0 03 0.03 1 3% 1 5 1.5
Vref = 1 to 4.25 V
%/V %/C %/R
VDD = 4.5 V, TA = 0 to 70C, f(RTO) = 8.192 MHz (PLL setting = 7 Ch) VDD = 4.5 V, TA = 25C, ROSC = 470 k at 1%, f(RTO) = 8.192 MHz (PLL setting = 7 Ch)
Typical voltage and current measurements taken at 25C, The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored. This parameter cannot exceed 15 mA total per internal VDD pin. Port C and port D share 1 internal VDD. Ports A and G0 are used internally.
external component absolute values
PARAMETER R(RTO) C(PLL) RTO external resistance PLL external capacitance TEST CONDITIONS TA = 25C, TA = 25C, 1% tolerance 10% tolerance MIN MAX 470 3300 UNIT k pF
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MSP53C691 MIXED-SIGNAL PROCESSOR
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MECHANICAL DATA
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
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Copyright 2001, Texas Instruments Incorporated

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