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NJU6678V
104-common x 132-segment BIT MAP LCD DRIVER
GENERAL DESCRIPTION The NJU6678V is a 104-common x 132-segment bit map LCD driver to display graphics or characters. It contains 21,120 bits display data RAM, microprocessor interface circuits, instruction decoder, and common and segment drivers. An image data from CPU through the serial or 8-bit parallel interface are stored into the 21,120 bits internal display data RAM and are displayed on the LCD panel through the commons and segments drivers. The NJU6678V displays 104 x 132 dots graphics or 8-character 6-line by 16 x 16 dots character. The NJU6678V contains a built-in OSC circuit for reducing external components. And it features Partial Display Function containing selectable active display block(s) (two blocks max.) and optimizing the duty cycle ratio. This function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resister. As result, it reduces the operating current. The operating voltage from 2.5V to 3.3V and low operating current are suitable for small size battery operation items. PACKAGE OUTLINE
NJU6678VCL
FEATURES Direct Correspondence of Display Data RAM to LCD Pixel Display Data RAM - 21,120 bits ;(1.5 times over than display size) LCD drivers - 104-common and 132-segment Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU Serial Interface Partial Display Function Two limited active display blocks setting. Duty ratio set automatically. . Easy Vertical Scroll by setting the start line address of over size display data RAM Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias Common Driver Order Assignment by mask option Version C0 to C103(Pin name) C103(Pin NJU6678VA Com0 to Com103 Com0 Com103 NJU6678VB Com103 to Com0 Com103 Com0 Useful Instruction Sets Display ON/OFF Cont, Display Start Line Set, Page Address Set, Column Address Set, Status Read, Display Data Read/Write, Inverse Display, All On/Off, Partial Display, Bias Select, n-Line Inverse, Voltage Booster Circuits Multiple Select(Maximum 5-time), Read Modify Write, Power Saving, ADC Select, etc. Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum, Voltage boosting polarity:Negative voltage(V DD Common)),Regulator, Voltage Follower (x 4) voltage(VDD Common)),Regulator, Precision Electrical Variable Resistance Low Power Consumption Operating Voltage --- 2.5V to 3.3V LCD Driving Voltage --- 6.0V to 17V Package Outline --- TCP / Bumped Chip C-MOS Technology (Substrate:N) (Substrate:N)
2003 Ver.4.9
NJU6678V
PAD LOCATION
S10 2 S10 3
S104 S105
S28 S29
S27 S26
Y
S130 S131 C103 C102
X
S1 S0 C5 1 C5 0
C53 C52
C1 C0
Chip Center : X=0um,Y=0um Chip Size : X=5.36mm,Y=5.31mm Chip Thickness : 675um + 30um Bump Size : 45um x 83um Pad pitch : 60um(Min) Bump Height : 15um TYP. Bump Material : Au Voltage boosting polarity :Negative voltage (VDD Common) Substrate :N
VD D V1 V2 V3 V4 V5 VR C1 C1 C2 C2 + C3 C3 C4 C4 + V OU T VS S D7( SI) D6( S CL) D5 D4 D3 D2 D1 D0 RD WR A0 CS O S C2 O S C1 T1 T2 VSS RE S CE L 68 P/S VD D D UM MY7 D UM MY6 D UM MY5 D UM MY4 D UM MY3 D UM MY2 D UM MY1 D UM MY0
+ +
NJU6678V
TERMINAL DESCRIPTION
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Terminal DUMMY0 DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 VDD P/S SEL68 RES V SS T2 T1 OSC 1 OSC2 CS A0 WR RD D0 D1 D2 D3 D4 D5 D 6(SCL) D 7(SI) V SS V OUT C4
+
Chip Size 5.36 x 5.31mm (Chip Center X=0um,Y=0um)
X= um -2250 -2190 -2130 -2070 -2010 -1950 -1890 -1830 -1747 -1666 -1596 -1487 -1417 -1347 -1238 -1168 -1049 -979 -861 -791 -667 -510 -289 -69 152 372 592 813 1033 1191 1261 1331 1401 1471 1541 1611 1681 1751 1821 1891 1961 2031 2101 2171 2241 2311 2523 2523 2523 2523 Y= um -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2370 -2310 -2250 -2190 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Terminal C4 C5 C6 C7 C8 C9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C 17 C 18 C 19 C 20 C 21 C 22 C 23 C 24 C 25 C 26 C 27 C 28 C 29 C 30 C 31 C 32 C 33 C 34 C 35 C 36 C 37 C 38 C 39 C 40 C 41 C 42 C 43 C 44 C 45 C 46 C 47 C 48 C 49 C 50 C 51 S0 S1 X= um 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 Y= um -2130 -2070 -2010 -1950 -1890 -1830 -1770 -1710 -1650 -1590 -1530 -1470 -1410 -1350 -1290 -1230 -1170 -1110 -1050 -990 -930 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810
C4C3+ C3
-
C2+ C2C1
+
C1VR V5 V4 V3 V2 V1 VDD C0 C1 C2 C3
NJU6678V
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Terminal S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 28 S 29 S 30 S 31 S 32 S 33 S 34 S 35 S 36 S 37 S 38 S 39 S 40 S 41 S 42 S 43 S 44 S 45 S 46 S 47 S 48 S 49 S 50 S 51 X= um 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 Y= um 870 930 990 1050 1110 1170 1230 1290 1350 1410 1470 1530 1590 1650 1710 1770 1830 1890 1950 2010 2070 2130 2190 2250 2310 2370 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Terminal S 52 S 53 S 54 S 55 S 56 S 57 S 58 S 59 S 60 S 61 S 62 S 63 S 64 S 65 S 66 S 67 S 68 S 69 S 70 S 71 S 72 S 73 S 74 S 75 S 76 S 77 S 78 S 79 S 80 S 81 S 82 S 83 S 84 S 85 S 86 S 87 S 88 S 89 S 90 S 91 S 92 S 93 S 94 S 95 S 96 S 97 S 98 S 99 S 100 S 101 X= um 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 Y= um 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497
NJU6678V
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Terminal S 102 S 103 S 104 S 105 S 106 S 107 S 108 S 109 S 110 S 111 S 112 S 113 S 114 S 115 S 116 S 117 S 118 S 119 S 120 S 121 S 122 S 123 S 124 S 125 S 126 S 127 S 128 S 129 S 130 S 131 C 103 C 102 C 101 C 100 C 99 C 98 C 97 C 96 C 95 C 94 C 93 C 92 C 91 C 90 C 89 C 88 C 87 C 86 C 85 C 84 X= um -2190 -2250 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 Y= um 2497 2497 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 Terminal C 83 C 82 C 81 C 80 C 79 C 78 C 77 C 76 C 75 C 74 C 73 C 72 C 71 C 70 C 69 C 68 C 67 C 66 C 65 C 64 C 63 C 62 C 61 C 60 C 59 C 58 C 57 C 56 C 55 C 54 C 53 C 52 X= um -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 Y= um -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370
NJU6678V
BLOCK DIAGRAM
C0 VS S V DD V1 to V5 5 COM Driver S EG Driver COM Driver C51 S0 S131 C103 C52
C1+ C1C2+ C2C3+ C3C4+ C4-
Shi ft V oltage Generator Reg is t er
Shift Re gis t e r COM SEG Timing Generator
D isp lay
Da ta
La t ch
Output Assignment
Register
VR T1,T2
Row Addr ess Dec oder
Line Address Decoder
C ount er Line
Display Data RAM
160 x 132
Buffer
R egis ter
Culumn Address Decoder Display Culumn A ddress Counter Timing Generator Culumn A ddress Register OSC1 Mu lt ip lexe r OSC. OS C2
Instruction Decoder
Pa ge
Addr ess
I/O
Sta t us
BF
Bus
Ho lde r
In t e rna l
Bu s
Res et
MP U
I n te r fa ce
RES CS A0
RD
SEL68 WR P/S
D0 to D7 (SI,SCL)
Start Line Regis ter
NJU6678V
TERMINAL DESCRIPTION No. 1 to 8 9,46 13,30 45 44 43 42 41 Symbol
DUMMY0 to DUMMY7
I/O
Function Dummy Terminals. These are open terminals electrically.
VDD VSS V1 V2 V3 V4 V5
Power
Power Supply Terminal (+2.5V - +3.3V) LCD Driving Voltage Supplying Terminals. In case of the external power supply operation without internal power supply operation, each level of LCD driving voltage is supplied from outside fitting with following relation. V DD>V1>V2>V3>V4>V5>VOUT In case of the internal power supply, LCD driving voltages V1-V4 depending on the Bias selection are supplied as shown in follows;
Bias
1/4Bias 1/5Bias 1/6Bias 1/7 Bias 1/8Bias 1/9Bias 1/10Bias 1/11 Bias
GND Ground Terminal (0V)
Power
V1 V 5+ 3 / 4 V L C D V 5+ 4 / 5 V L C D V 5+ 5 / 6 V L C D V 5+ 6 / 7 V L C D V 5+ 7 / 8 V L C D V 5+ 8 / 9 V L C D V 5+ 9/10V L C D V 5+ 10/11VLCD
V2 V 5+ 2 / 4 V L C D V 5+ 3 / 5 V L C D V 5+ 4 / 6 V L C D V 5+ 5 / 7 V L C D V 5+ 6 / 8 V L C D V 5+ 7 / 9 V L C D V 5+ 8/10V L C D V 5+9/11V L C D
V3 V 5+ 2 / 4 VLCD V 5+ 2 / 5 VLCD V 5+ 2 / 6 VLCD V 5+ 2 / 7 VLCD V 5+ 2 / 8 VLCD V 5+ 2 / 9 VLCD V 5 +2/10V L C D V 5+2/11V L C D
V4 V 5 + 1 / 4 VLCD V 5 + 1 / 5 VLCD V 5 + 1 / 6 VLCD V 5 + 1 / 7 VLCD V 5 + 1 / 8 VLCD V 5 + 1 / 9 VLCD V 5+ 1/10V L C D V5 +1/11V L C D
(VLCD=VDD-V5) 38,39 36,37 34,35 32,33 31 40 15 14 C1 ,C1 C2 +,C2C3 +,C3C4 +,C4+ -
O
Capacitor connecting terminals for Internal Voltage Booster.Boosting time is programmed by instruction (2 to 5 times )
VOUT VR T1 T2
O I I
Boosted voltage output terminal. Connects the capacitor between VOUT terminal and VSS . VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5 level is adjusted by external resistors. LCD bias voltage control terminals.
T1 L H H T2 L/H L H Voltage booster Cir. Available Not Avail. Not Avail. Voltage Adj. Available Available Not Avail. V/F Cir. Available Available Available
22 to 29
D0 to D7
(SI) (SCL)
I/O Data Input/Output terminals. In Pararel Interface Mode (P/S="H") I/O terminals of 8-bit bus. In Serial Interface Mode (P/S="L") D7: Input terminal of serial data ( SI ). D6: Input terminal of serial data clock ( SCL ). D0 to D5 terminals are Hi-impedance. When CS="H", D0 to D7 terminals are Hi-impedance. I Data discremination signal input terminal. The signal from MPU discreminates transmoitted data between Display data and Instruction.
A0 Distin. H Display Data L Instruction
19
A0
12 18
RES CS
I I
Reset terminal. Reset operation is executing during "L" state of RES. Chip select signal input terminal. Data Input/Output are available during CS ="L".
NJU6678V
No 21 Symbol RD(E) I/O I Function RD(80 type) or E(68 type) signal input terminal. ( SEL68="L" ) RD signal from 80 type MPU input terminal. Active "L". D0 to D7 terminals are output during "L" level. ( SEL68="H" ) Enable signal from 68 type MPU input terminal. Active "H". WR(80 type) or R/W(68 type) signal input terminal ( SEL68="L" ) WR signal from 80 type MPU input terminal. Active "L". The data transmitted during WR="L" are fetched at the rising edge of WR. ( SEL68="H" ) R/W signal from 68 type MPU input terminal.
R/W State H Read L Write
20
WR(RW)
I
11
SEL68
I
MPU interface type selection terminal. This terminal must connect to V DD or VSS.
SEL68 State H 68 Type L 80 Type
10
P/S
I
Parallel or Serial interface selection signal input terminal.
P/S "H" "L"
Chip Select
Data/Command
Data D 0 to D 7 SI(D7)
Read/Write serial Clock
CS CS
A A0
RD,WR -
SCL(D 6)
In case of serial interface( P/S="L") RAM data and status read operation do not work in mode of the serial interface. RD and WR terminals must fix to "H" or "L". D0 to D5 terminals are Hi-impedance. 16 17 47 to 98 OSC1 OSC2 C0 to C51 I External clock input terminal. In Internal oscillation operation, OSC1 and OSC2 terminals should be Open.In External clock operation, the external clock input to OSC1 terminal. LCD driving signal output terminals. Common output terminals:C 0 to C103 Segment output terminals:S 0 to S131 Common output terminal Following output voltage is selected by the combination of signal and Common scanning data.
Scan data FR H L H L Output Voltage V5 VDD V1 V4
O
alternating (FR)
99 to 230
S0
toS131
O
H
L
Segment output terminal Following output voltage is selected by the combination of signal and display data in the DD RAM. 282 to 231 C52 to C103 O
RAM Data H FR H L H L Output Voltage Normal V DD V5 V2 V3 Reverse V2 V3 V DD V5
alternating (FR)
L
NJU6678V
Functional Description (1) Description for each blocks (1-1) Busy Flag (BF) The Busy Flag (BF) is set to logical "1" in busy of internal execution by an instruction, and any instruction excepting for the "Status Read" is disable at this time. Busy Flag is outputted through D7 terminal by "Status D7 Read" instruction. Although another instructions should be inputted after check of Busy Flag, no need to check Busy flag if the system cycle time (t CYC) as shown in AC Characteristics is secured completely. (tCYC) . (1-2)Display Start Line Register The Display Start Line Register is a register to set a display data RAM address corresponding to the COM0 COM0 display line (the top line normally) for the vertical scroll on the LCD, Page address change and so forth. The Display Start Line Address set instruction sets the 8-bit display start address into this register. (1-3) Line Counter Line Counter is reset when the internal FR signal is switched and outputs the line address of the display data RAM by count up operation synchronizing with common cycle of NJU6678V . NJU6678V. (1-4) Column Address Counter Column Address Counter is the 8-bit preset-able counter to point the column address of the display data RAM (DD RAM) as shown in Figure 1. The counter is incremented automatically after the display data read/write instructions execution. When the Column address counter reaches to the maximum existing address by the increment operations, the count up operation (increment) is frozen. However, when new address is set to the column address counter again, it restarts the count up operation from a set address. The operation of Column Address Counter is independent against Page Address Register. By the address inverse instruction (ADC select) as shown in Figure 1, Column Address Decoder reverses the correspondence between Column address and Segment output of display data RAM. (1-5) Page address Register Page Address Register assigns the page address of the display data RAM as shown in Figure 1. In case of accessing from the MPU with changing the page address, Page Address Set instruction is required. (1-6) Display Data RAM The Display data RAM (DD RAM) is the bit map RAM consisting of 21,120 bits to store the display data corresponding to the LCD pixel on LCD panel. The DD RAM data and the state of the LCD: In Normal Display : "1"=Turn-On Display, "0" =Turn-Off Display In Reveres Display : "1"=Turn-Off Display, "0" =Turn-On Display DD RAM output 132 bits parallel data addressed by line address counter then the data latched in the display data latch. Asynchronous data access to the DD RAM is available due to the access to the DD RAM from the CPU and latch to the display data latch operation are done independently.
(1-7) Common Driver Assignment This circuit determines the scanning direction of the common output. Table 1
COM Outputs Terminals PAD No.
Pin name
47 C0 COM0 C O M 103
98 C 51 C O M 51 C O M 52
231 C 103 C O M 103 COM0
282 C52 C O M 52 C O M 51
Ver.A Ver.B
The Mask fixes the common scanning direction between version A and B that can not be changed by the instruction.
NJU6678V
Page Address DATA D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,0,0) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,0,1) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,1,0) D3 D4 D5 D6 D7 D0 D1 : : : : : : : : D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,1,1,1,0) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,1,1,1,1) D3 D4 D5 D6 D7 D0 D1 : : : : : : : : D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (1,0,0,1,1) D3 D4 D5 D6 D7 | Column Address A D C D 0= " 0 " D 0= " 1 " 00 83 0 | 01 82 1 | 02 81 2 | 03 80 3 | 04 | 05 | 06 | 07 | 08 | 09 | | | | | | | 80 03
128
Display Pattern
Line Address
For example the Display start line is 10 H
00 01 02 Pege 0 03 04 05 06 07 08 09 0A 0B Pege 1 0C 0D 0E 0F 10 11 12 13 Pege 2 14 15 16 17 18 19 : : : : : : : : 6E 6F 70 71 72 Pege 14 73 74 75 76 77 78 79 7A Pege 15 7B 7C 7D 7E 7F 80 81 : : : : : : : : 96 97 98 99 9A 9B Pege 19 9C 9D 9E 9F | | | 83 00
131
Cn Out C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 : : : : C94 C65 C96 C97 C98 C99 C100 C101 C102 C103
7A 7B 7C 7D 7E 7F 09
122
81 82 02 01
129 130
7F 7E 7D 7C 4 5 6 7
7B 7A 8 9
08
123
07
124
06
125
05
126
04
127
Segment Output
Fig.1 Correspondence with Display Data RAM Address
NJU6678V
(1-8) Reset Circuit When the input signal to RES terminal goes to "L", the reset circuit executes initialization as below; The Initialization state (default) 1 Display Off 2 Normal Display (not inverse) 3 ADC Select : Normal (ADC Instruction D0 ="0") D0 4 Read Modify Write Mode Off 5 Voltage Booster off, Voltage Regulator off, Voltage follower off 6 Static Drive Off 7 Driver Output Off 8 Clear the data of serial interface register 9 Set the Column Address Counter to 00H 00H 10 Set the Display Start Line Register to 00H 00H 11 Set the Page Address Register to page "0" 12 Set the EVR register to FFH FFH 13 Set the Partial Display(1/104 duty) 14 Set the Bias select(1/11 Bias) 15 Set the Voltage Booster(5 times) 16 Set the n-line inverse register to 0H 0H The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization as shown in " the MPU interface " in the Application Circuit section. The "L" level input signal as reset signal must keep the period over than 10us as shown in DC Characteristics. The NJU6678V takes 1us for the reset operation after the rising edge of the RES signal. The reset operation by RES ="L" initializes each resister setting as above reset status, but the internal oscillation circuit and output terminals (D0 to D7) are not affected. To avoid the lock-up, the reset operation by the RES terminal must be required every time when power terns on. The reset operation by the reset instruction, function 9 to 16 operations mentioned above is performed. The RES terminal must be keep "L" level when the power terns on in not use of the built-in LCD power supply circuit for no affect to the internal execution. (1-9) LCD Driving Circuit (a) LCD Driving Circuits LCD driver is 236 sets of multiplexer consisting of 132 segments and 104 commons drivers to output LCD driving voltage. The common driver outputs the common scan signals formed with the shift register. The segment driver outputs the segment driving signal determined by a combination of display data in the DD RAM, common timing, FR signal, and alternating signal for LCD. The output wave forms of segment/common are shown in LCD DRIVING WAVEFORM. WAVEFORM. (b) Display Data Latch Circuits Display Data Latch Circuit latches the 132-bit display data outputted from the DD RAM addressed by the Line address counter to LCD driver at every common signal cycle temporarily. The original data in the DD RAM is not changed because of the Normal/Reverse display, Display On/Off, Static drive On/Off instruction processes only stored data in this Display Data Latch Circuit. (c) Signal forming to Line Counter and Display Data Latch Circuit The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the internal display clock (CL). The display data of 132 bits from Display Data RAM pointed by the line address synchronizing with the internal display clock are latched into the Display Data Latch Circuit and are outputted to LCD
driving circuits.
The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent operation with an access to the display data RAM from MPU. (d) Display Timing Generation Circuit The display timing generation circuit generates the internal timing of the display system by the master clock and the internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the LCD Driving circuit.
NJU6678V
(e)Common Timing Generator The Common Timing Generator generates the common timing signal from the display clock (CL ). -2-frame alternating drive mode
103 104 1 2 3 4 5 6 7 8 101 102 103 104 1 2 3 4 5
C L
F R
C 0
VDD V1 V4 V5 VDD V1 V4 V5
C 1
R MD T A AA VDD V2 V3 V5
Sn
Fig.2 -n-line inverse drive mode (n=7, line inverting register sets to 6)
103 104 1 2 3 4 5 6 7 8 101 102 103 104 1 2 3 4 5
C L
F R
C 0
VDD V1 V4 V5 VDD V1 V4 V5
C 1
R MD T A AA VDD V2 V3 V5
Sn
Fig.3
NJU6678V
(f) Oscillation Circuit The Oscillation Circuit is a low power type CR oscillator using an internal resistor and capacitor. The oscillator output is using for the display timing clock and for the voltage booster circuit. And the display clock(CL) is generated from this oscillator output frequency by dividing. -The relation between duty and divide Table 2
Duty Divide 1/8 1/50 1/16 1/25 1/24 1/16 1/32 1/12 1/40 1/10 1/48,56 1/8 1/64,72 1/6 1/80,88 1/5 1/96,104 1/4
(g) Power Supply Circuit The internal power supply circuit generates the voltage for driving LCD. It consists of voltage booster circuits (from 2 times to 5 times), voltage regulator circuits, and voltage followers. The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4,V5 and VOUT for the LCD V1 V2 V3 V4,V5 VOUT should be supplied from outside, terminals C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, and VR should be open. The status of internal power supply is selected by T1 and T2 terminal. Furthermore the external power supply operates T1 T2 with some of internal power supply function. Table 3
T1 L H H T2 L/H L H Voltage Booster ON OFF OFF Voltage Adj. ON ON OFF Buffer(V/F) ON ON ON Ext.Pow Supply VOUT V5,VOUT Open Open Open C1+,C1- to C4+,C4VR Term.
When (T1, T2)=(H, L), C1+, C1-, C2+, C2-,C3+, C3-, C4+, C4- terminals for voltage booster circuits are open be(T1 T2 cause the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal should be VOUT supplied from outside. When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster circuits (T1 T2 and Voltage adjust circuits do not operate.
The internal power supply Circuits is designed specially for a small-size LCD like as normal cellular phone size LCD panel. When NJU6678V apply to the large size LCD panel application (large capacitive load), external power supply is required to keep good display condition.. To keep good display condition, external component of the capacitors connecting to the V1 to V5 terminals and voltage booster circuits and the feedback resistors for the V5 operational amplifier must fix each optimized constant after checking various display patterns on LCD panel actually in the application.
NJU6678V
Power Supply applications (1) Internal Power Supply Example. (2) Only VOUT Supply from outside Example. VOUT All of the Internal Booster, Voltage Regulator, Internal Voltage Regulator, Voltage Follower using Voltage Follower using. Internal power supply ON (Instruction) (T1,T2) = (H,L) Internal power supply ON (instruction) (T1,T2)=(L,L)
VDD
+
VDD T 1
+
T 1 V1 T 2
V1
+
T 2
+
V2 V3
C1+ C1C2+
V2 V3
+
+
+
+
+
+
V4
+
C2+
V4
+
V5
+
C3+ C3C4+ C4+
V5 VO UT VSS VDD
VOUT VSS VDD
VR
V5
VR
V5
(3) VOUT and V5 supply from outside Example. VOUT Internal Voltage Follower using. Internal power supply (Instruction) (T1,T2) =(H,H)
(4) External Power Supply Example All All of V1 to V5 and VOUT supply from outside VOUT Internal power supply (Instruction) (T1,T2) =(H,H)
VDD
+
VDD T 1 T 1 V1 T 2 V2 V3 V4 V5 VOUT VSS T2
V1
+
V2 V3
+
+
V4 V5 VOUT VSS
: These switches should be open during the power save mode.
NJU6678V
(2) Instruction
The NJU6678V distinguishes the data on the data bus D0 to D7 as an instruction by combination of A0, RD, and WR(R/ W) signals. The decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. Therefore, no busy flag check required normally. In case of the serial interface, the data input as MSB(D7) first serially. Table.4 shows the instruction codes of the NJU6678V. NJU6678V.
Table 4. Instruction Code
Instruction
A0 RD WR
(*:Don't Care)
D
1
Code D
7
D
6
D
5
D
4
D
3
D
2
D
Description
0
(a)
Display ON/OFF Display Start Line Set High Order 4bits Display Start Line Set Lower Order 4bits
0 0
1 1
0 0
1 0
0 1
1 0
0 1
1
1
1
0/1
LCD Display ON/OFF 0:OFF 1:ON Determine the Display Line of RAM to the COM0. (Set the Higher order 4bits) Determine the Display Line of RAM to the COM0. (Set the Lower order 4bits) Set the Higher order 1bit page of DD RAM to the Page Address Register Set the Lower order 4 bit page of DD RAM to the Page Address Register Set the Higher order 4 bits Column Address to the Reg. Set the Lower order 4 bits Column Address to the Reg. Read out the internal Status Write the data into the Display Data RAM Read the data from the Display Data RAM
(b)
High Order Address Lower Order Address * * *
Hi.
0
1
0
0
1
1
0
(c)
Page Address Set High Order 1bits Page Address Set Lower Order 4bits
0
1
0
0
1
0
0
0
1
0
1
1
0
0
Lower Order Page Address High Order Column Add. Lower Order Column Add. 0 0 0 0
(d)
Column Address Set High Order 4bits Column Address Set Lower Order 4bits
0 0 0 1 1 0
1 1 0 1 0 1
0 0 1 0 1 0
0 0
0 0
0 0
1 0
(e) (f) (g) (h)
Status Read Write Display Data Read Display Data Normal or Inverse ON/OFF Set Static Drive ON /Normal Display Sub instruction table mode (k)Partial Display 1st Block, Set Start display unit 1st Block, Set The number of display units 2nd Block, Set Start display unit 2nd Block, Set The number of display units Partial display on (l)n-line Inverse Drive Set
Status
Write Data Read Data 1 0 1 0 0 1 1
0/1
Inverse the ON and OFF Display 0:Normal 1:Inverse Whole Display Turns ON 0:Normal 1:Whole Disp. ON Set the Sub instruction table.
(i) (j)
0 0
1 1
0 0
1 0
0 1
1 1
0 1
0 0
1 0
0 0
0/1
0
0 0
1 1
0 0
0 0
0 0
0 0
0 1
Start display unit number of display units Start display unit number of display units 0 0 0 0
Set the Start display unit of 1st Block. Set the number of display units of 1st Block. Set the Start display unit of 2nd Block. Set the number of display units of 2nd Block. It comes off the mode to set and a display is executed.
0 0
1 1
0 0
0 0
0 0
1 1
0 1
0
1
0
0
1
0
0
Sub Inst.
Register Set Higher order 2 bits Register Set Lower order 4 bits n-line Inverse Drive Set is executed. (m)EVR Register Set EVR Register Set Higher order 4 bits EVR Register Set Lower order 4 bits EVR Register Set is executed.
0 0 0
1 1 1
0 0 0
0 0 0
1 1 1
0 1 1
1 0 1
*
*
higher order
Set the number of inverse drive line. Set the number of inverse drive line.
Lower order 0 0 0 0
The execution of the line inverse drive.
0
1
0
1
0
0
0
EVR Data Higher order EVR Data Lower order 0 0 0 0 0 0 0 1
Set the V 5 output level to the EVR register. (Higher order 4 bits) Set the V 5 output level to the EVR register. (Lower order 4 bits) The execution of the EVR. It ends the setting of sub instruction table.
0
1
0
1
0
0
1
0 0
1 1
0 0
1 0
0 1
1 1
0 1
(n)
End of sub instruction table mode
NJU6678V
(2-1) Explanation of Instruction Code (a) Display On/Off It executes the ON/OFF control of the whole display without relation to the DD RAM or any internal conditions.
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D
D 0:Display Off 1:Display On
(b) Display Start Line It sets the DD RAM line address corresponding to the COM0 terminal (normally assigned to the top display line). In this instruction execution, the display area is automatically set by the lines that correspond to the display duty ratio to the upward direction of the line address. Changing the line address by this instruction performs smooth scrolling to a vertical direction. In this time, the DD RAM data are unchanged.
A0 0
0
RD 1
1
WR 0
0
D7 0
0
D6 1
1
D5 0
1
D4 1
0
D3 A7
A3
D2 A6
A2
D1 A5
A1
D0 A4
A0
A7 0 0
A6 0 0
A5 0 0
A4 0 0 : :
A3 0 0
A2 0 0
A1 0 0
A0 0 1
1
0
0
1
1
1
1
1
Line Address(HEX) 00 01 : : 9F
(c) Page Address Set When MPU access to the DD RAM, a page address is set by page Address Set instruction before writing the data. (Note: the change of page address is not affected to the display.)
A0 0
0
RD 1
1
WR 0
0
D7 0
1
D6 1
1
D5 0
0
D4 0
0
D3 *
A3
D2 *
A2
D1 *
A1
D0 A4
A0
(*:Don't Care)
A4 0 0
A3 0 0
A2 0 0 : :
A1 0 0
A0 0 1
Page 0 1 : :
1
0
0
1
1
19
NJU6678V
(d) Column Address When MPU accesses to the DD RAM , the row address set by Page Address Set instruction is required with the column address before writing the data. The column address set requires twice address set which are higher order 4 bits address set and lower order 4 bits. When the MPU access to the DD RAM continuously, the column address increments automatically from the set address after each data access. Therefore, the MPU can transmit only the Data continuously without setting the column address at every transmission time. The increment of column address is stopped at the maximum column address plus 1 limited by each display mode. When the column address count up is stopped, the row address is not changed.
A0 0
0
RD 1
1
WR 0
0
D7 0
0
D6 0
0
D5 0
0
D4 1
0
D3 A7
A3
D2 A6
A2
D1 A5
A1
D0 A4
A0
Higher Order Lower Order
A7 0 0
A6 0 0
A5 0 0
A4 0 0
A3 0 0 : :
A2 0 0
A1 0 0
A0 0 1
Column Address(HEX) 0 1 : :
1
0
0
0
0
0
1
1
83
(e) Status Read This instruction reads out the internal status of "BUSY", "ADC", "ON/OFF" and "RESET" described as follows.
A0 0
RD 0
WR 1
D7
D6
D5
ON/OFF
D4
RESET
D3 0
D2 0
D1 0
D0 0
BUSY A D C
BUSY
: BUSY=1 indicate the operating or the Reset cycle. All instructions can be input after the BUSY status change to "0". : Indicate the output correspondence of column (segment) address and segment driver. 0 :Counterclockwise Output (Inverse) 1 :Clockwise Output (Normal)
ADC
(Note) The data "0=Inverse" and "1=Normal" of ADC status is inverted with the ADC select Instruction of "1=Inverse" and "0=Normal". ON/OFF : Indicate the whole display On/Off status. 0 : Whole Display "On 1 : Whole Display "Off" (Note) The data "0=On" and "1=Off" of Display On/Off status is inverted with the Display On/Off instruction data of "1=On" and "0=Off". RESET : Indicate the initializing by RES terminal signal or reset instruction. 0 : Not Reset status 1 : In the Reset status
NJU6678V
(f) Write Display Data It writes the data on the data bus into the DD RAM. column address increments automatically after data writing, therefore, the MPU can write the data into the DD RAM continuously without the address setting at every writing time once the starting address is set.
A0 1 RD 1 WR 0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE DATA
(g) Read Display Data This instruction reads out the 8-bit data from DD RAM addressed by the column and the page address. The column address automatically increments after the 8-bit data read out, therefore, the MPU can read the data from the DD RAM continuously without the address setting at every reading time once the starting address is set. Note that the dummy read is required just after setting the column address (see "(4-4) Access to the DD RAM and the Internal Register"). In the serial interface mode, the display data is unable to read out.
A0 1 RD 0 WR 1 D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
(h) Normal or Inverse On/Off Set It changes the display condition of normal or reverse for entire display area. The execution of this instruction does not change the display data in the DD RAM.
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D
D 0 : Normal 1 : Inverse
RAM data "1" correspond to "On" RAM data "0" correspond to "On"
(i) Static Drive This instruction turns all the pixels ON regardless the data stored in the DD RAM. In this time, the data in DD RAM are remained and unchanged. This instruction is executed prior to the "Normal or Inverse On/Off Set" Instruction.
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D
D 0 : Normal Display 1 : Whole Display turns On When the "Static Drive ON" instruction is executed at Display OFF status, the NJU6678V operates in Power Save Mode. (Refer " Power Save Mode ")
NJU6678V
(j) Sub Instruction table mode This instruction switches the instruction table from the main to the sub. The sub instruction table contains instructions of partial display, n-line inverse drive set and EVR register set as mentioned in (k), (l) and (m). The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The instruction of end of sub instruction table mode (n) switches the instruction table from the sub to the main. If any main instructions are written in the sub instruction mode, the NJU6678V will malfunction.
A0 0
RD 1
WR 0
D7 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
-Set sub Instruction table flow is shown below:
Sub Instruction table mode
Switches to Sub instruction table mode.
Set sub instructions.
End of Sub Instruction table mode.
Switches to Main instruction mode.
(k) Partial Display It selects two active display areas on the LCD Panel partially. The display area is divided to 13 units with four commons each and selected two display blocks by setting Unit number and number of Unit required (not overlap, not over than 13 units) to display on the LCD panel. These two display blocks are assigned optionally on the LCD panel. Duty selects an adapted ratio number corresponding to the total number of two display blocks automatically. Partial Display function adjusts the LCD driving voltage, Voltage boosting times and E.V.R level by the instruction to generate the optimum LCD driving voltage for display quality. As result, the operating current is reduced. * Display Unit Structure
U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 (8 c m o o m ns) (8 c m o o m ns)
104-common
132-segment
NJU6678V
Partial display instruction When Partial Display functions, both of Top Unit Number of display area (the Start Unit) and the number of the effective continuous unit (Display Unit) from the Start Unit for the first display block and the second. Attention that the first display block and the second definition must not be overlap of display area and not be over than 13 units in total. In case of whole display (1/104 duty), the first display block defines Start Unit=0 (0,0,0,0) and Display Unit = 13 (1,1,0,1) for all of display area selection. In this time, the definition of the second display block is ignored. In case of only the first block display, the second display block defines Start Unit=0 (0,0,0,0) and Display Unit = 0 (0,0,0,0) for no display area.
A0 0 RD 1
1
WR 0
0
D7 0
0
D6 0
0
D5 0
0
D4 0
1
D3 D
D
D2 D
D
D1 D
D
D0 D
D
Start unit The display unit number Start unit The display unit number
1st Block
0
0
1
0
0
0
1
0
D
D
D
D
2nd Block
0 1 0 0 0 1 1 D D D D
By input following instruction, the duty ratio is changed automatically and executes the partial display function.
0 1 0 0 1 0 0 0 0 0 0
Partial display on
D :unit number (Hex.)
Notes) Attention followings due to prevent from mulfunction * The input order of Partial Display instructions must follow above. * Prohibits the overlap of the 1st partial display block and the 2nd. * The Start Unit of the 1st partial display block must not be over 12. * The total Display Unit Number (the sum of the 1st and 2nd partial display block Unit Num ber) must not be over 13. * On the LCD panel, no active display area inserts between the 1st display block and the 2nd . However, the display data of the 1st display block and the 2nd must store continuously in the display data RAM.
NJU6678V
Example of the Partial Display setting. UNIT 0 UNIT 1 UNIT 2 UNIT 3 UNIT 4 UNIT 5 UNIT 6 UNIT 7 UNIT 8 UNIT 9 UNIT 10 UNIT 11 UNIT 12 1st Block
2nd Block
active display-block
The above partial display condition is set as follows: 1)Set sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
Set sub instruction mode.
2)Set partial display conditions
A0 0
0
RD 1
1
WR 0
0
D7 0
0
D6 0
0
D5 0
0
D4 0
1
D3 0
0
D2 0
0
D1 0
1
D0 0
0
1st Block, Set start unit to "0" 1st Block, Set the display unit number to "2" 2nd Block, Set start unit to "4" 2nd Block, Set the display units number to "5" Execute Partial display.
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
The Duty is changed to 1/56 automatically.
3)End sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
End sub instruction mode. Back to main instruction mode.
Duty is changed automatically when Partial Display execution. But LCD Driving Voltage, Bias, Driving form like as 2-frame alternating driving or n-line inverse are not changed. Therefore, Display Off should operate before Partial Display execution for prevention of unexpected display, and Voltage Booster Select instruction, E.V.R Register Set, Bias Select and n-line Inverse Driving Set should set optimum conditions for good display in the mean time of Partial Display instruction execution. The optimum conditions should fix refering the result of actual display eveluation.
NJU6678V
-Set Partial Display flow is shown below:
Internal Power Supply OFF Sub Instruction Table Mode Set a Start Unit of the first display unit Set a number of Display Unit of the first Set a Start Unit of the second display unit Set a number of Display Unit of the second Executes Partial Display function n-line Inverse Drive Set EVR Register Set End Sub Instruction Table Mode Bias Select Voltage Booster Times Select Wait Time Internal Power Supply ON
(l) n-line Inverse Drive Mode n-Line Inverse Register Set (refer +Functional Description Fig.3 n-line Inverse alternative drive mode) It sets a line number to inverse the polarity of common driver and segment. The instructions must be input in order of followings. These instructions are sub instruction sets and must be set after (j)Sub instruction table mode.
1)Set sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 Set sub instruction mode.
2)Set n-line Inverse number
A0 0
0
RD 1
1
WR 0
0
D7 0
0
D6 1
1
D5 0
1
D4 1
0
D3 *
A3
D2 *
A2
D1 A5
A1
D0 A4
A0
Higher order Low order
A5
0 0 1
A4
0 0 1
A3
0 0 : 1
A2
0 0 1
A1
0 0 1
A0
0 1 1
Inverse line
-(*) 2 : 64
(*:2-frame alternating drive mode.)
3)Execute the n-line Inverse
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
4)End sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 End sub instruction mode. Back to main instruction mode.
NJU6678V
(m) EVR Register Set It controls the voltage regulator circuit of the internal LCD power supply to adjust the LCD display contrast by changing the LCD driving voltage "V5". By data setting into the EVR register, the LCD driving voltage "V5" selects out of 201 steps of regulated voltage. The voltage adjustable range of "V5" is fixed by the external resistors. For details, refer the section "(3-2) Voltage Adjust Circuits". 1)Set sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 Set sub instruction mode.
2)Set EVR Register
A0 0
0 A7 0
RD 1
1 A6 0
WR 0
0 A5 1
D7 1
1 A4 1 : :
D6 0
0 A3 0
D5 0
0 A2 1
D4 0
1 A1 1
D3 A7
A3 A0 1
D2 A6
A2
D1 A5
A1 V LCD Low : :
D0 A4
A0
1
1
1
1
1
1
1
1
High
VLCD=V DD-V 5 LCD=V DD-V When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1). 3)Execute the EVR
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
4)End sub instruction mode
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 End sub instruction mode. Back to main instruction mode.
(n) End of Sub instruction table mode "End of sub instruction table mode" instruction switches instruction table from sub to main. (k)Partial display, (l)n-line inverse drive mode, and (m)EVR are sub instruction sets on the sub instruction table. The instruction of "END of sub instruction mode" must be set after these sub instruction sets. The NJU6678V may occur incorrect operation if any main instructions on the main instruction table are input in mode of sub instruction table.
A0 0 RD 1 WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
NJU6678V
(o) Bias Select This instruction sets the bias voltage.
A0 0
A2 0 0 0 0 1 1 1 1
RD 1
WR 0
A1 0 0 1 1 0 0 1 1
D7 1
D6 0
A0 0 1 0 1 0 1 0 1
D5 1
D4 1
Bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11
D3 *
D2 A2
D1 A1
D0 A0
(*:Don't Care)
(p) Boost Level Select This instruction sets the boost level (2 to 5 times). When "Partial Display Instruction" execution, the "Boost Level Select" also must be executed. If the external capasitors are connected as the lower than 5 times boost level, don't set the boost level by the instruction over than the boost level by conecting capasitors. If set the boost level over than it, the device will make malfunction.
A0 0
RD 1
WR 0
D7 0
D6 0
D5 1
D4 1
D3 0
D2 0
D1 A1
D0 A0
Command A1 0 0 1 1 A0 0 1 0 1
Booster Multiple 5times external 4times external 3times external 2times external capacitors capacitors capacitors capacitors connections connections connections connections 2-time 3-time 2-time 4-time 3-time 2-time 5-time 4-time 3-time 2-time
NJU6678V
(q) Read Modify Write/End This instruction sets the Read Modify Write controlling the page address increment. In this mode, the Column Address only increments when execute the display data "Write" instruction; but no change when the display data "Read" Instruction. This status is continued until the End instruction execution. When the End instruction is executed, the Column Adddress goes back to the start address before the execution of this "Read Modify Write" instruction. This function reduces the load of MPU for repeating display data change of the fixed area (ex. cursor blink).
A0 0 RD 1 WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Read Modify Write On 1 : End Note) In this "Read Modify Write" mode, out of display dara "Read"/"Write", any instructions except "Column Address Set" can be executed. - The Example of Read Modify Write Sequence
Page Address Set Column Address Set Set to the Start Address of Cursor Display
Read Modify Write
Start the Read Modify Write
Dummy Read The data is ignored Column Counter doesn't increase Data Read Column Counter doesn't increase Data inverse by MPU Data Write Dummy Read Data Read Data Write Dummy Read Data Read Data Write Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase
End NO Finish? YES
End the Read Modify Write
NJU6678V
(r) Reset This instruction executes the following initialization. The reset by the reset signal input to the RES terminal (hardware reset) is required when power turns on. This reset instruction does not use instead of this hardware reset when power turns on. Initialization 1 2 3 4 5 6 7 8
Set the Column Address Counter to 00H 00H Set the Display Start Line Register to 00H 00H Set the Page Address Register to page "0" Set the EVR register to FFH FFH Set the Partial Display(1/104 duty) Set the Bias select(1/11 Bias) Set the Voltage Booster(5 times) Set the n-line inverse register to 0H 0H The DD RAM is not affected by this initialization.
A0 0 RD 1 WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
(s) Internal Power Supply ON/OFF This instruction control ON and OFF for the internal Voltage Converter, Voltage Regulator and Voltage Follower circuits. For the Booster circuits operation, the oscillation circuits must be in operation. operation.
A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Internal Power Supply Off 1 : Internal Power Supply On The internal Power Supply must be Off when external power supply using. *1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer capacitors, VDD and VLCD. VDD VLCD. Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the (3-4) Fig.5)
NJU6678V
(t) Driver Outputs ON/OFF This instruction controlls ON/OFF of the LCD Driver Outputs.
A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 D
D 0 : LCD driving waveform output Off 1 : LCD driving waveform output On The NJU6678V implements low power LCD driving voltage generator circuit and requires the following Power Supply ON/OFF sequence.
- LCD Driving Power Supply ON/OFF Sequences The sequences below are required when the power supply turns ON/OFF. For the power supply turning on operation after the power-save mode, refer the "power save release sequence" mentioned after. Turn ON sequence
EVR Register Set Internal Power Supply ON or External Power supply ON (Wait Time) *1 Driver Outputs OFF Drivier Outputs ON NJU6678V Power OFF
Turn OFF sequence
Display OFF Whole Display ON
Internal Power Supply OFF or External Power Supply OFF
*1 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly, V1 V5 test by using the actual LCD module.
NJU6678V
(u) Power Save (complex comand) When Static Drive ON at the Display OFF status (inverse order also same), the internal circuits goes to the Power Save Mode and the operating current is dramatically reduced, almost same as the standby current. The internal status in the Power Save Mode is shown as follows; 1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation. 2: LCD driving is stopped. Segment and Common drivers output VDD level voltage. VDD 3: The display data and the internal operating condition are remained and kept as just before enter the Power Save Mode. 4: All the LCD driving bias voltage (V1 to V5) is fixed to the VDD level. VDD The power save and its release perform according to the following sequences. Power Save Sequence Display OFF Static Drive ON Driver Outputs OFF Power Save Release Sequence Normal Display Display ON (Wait Time) Driver Outputs ON
(Static Drive ON)
The NJU6678V constantly spends the current without the execution of the Driver Outputs OFF instruction. The LCD drive waveform is not output until the Driver Outputs ON instruction is executed. *1 In the Power Save sequence, the Power Save Mode starts after the Static Drive ON command is executed. *2 In the Power Save Release sequence, the Power Save Mode releases just after the Static Drive OFF instruction execution. The Display ON instruction is allowed to execute at any time after the Static Drive OFF instruction is completed. *3 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time cor V1 V5 rectly, test by using the actual LCD module. *4 LCD driving waveform is output after the exection of the Driver Outputs ON instruction execution. *5 In case of the external power supply operation, the external power supply should be turned off before the Power Save Mode and connected to the VDD for fixing the voltage. In this time, VOUT terminal also should be made VDD VOUT codition like as disconection or connection to VSS. VSS.
(v) ADC Select This instruction determines the correspondence of Column in the DD RAM with the Segment Driver Outputs. Segment Driver Output order is inversed when this instruction executes, therefore, the placement the NJU6678V against the LCD panel becomes easy.
R/W WR 0
A0 0
RD 1
D7 1
D6 0
D5 1
D4 0
D3 0
D2 0
D1 0
D0 D
D 0 : Clockwise Output (Normal)
Segment Driver S0 to S131 S0 S131
1 : Counterclockwise Output (Inverse) Segment Driver S131 to S0 S131 S0
NJU6678V
(3) Internal Power Supply (3-1) 5-time voltage booster circuits The 5-time voltage booster circuit outputs the negative Voltage(V DD Common) boosted 5 times of VDD-V SS from the Voltage(VDD VDD-VSS VOUT terminal with connecting the five capacitors between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+ and C4-, and VSS C1 C1 C2 C2 C3 C3 C4 C4 VSS and VOUT. The boosting time is selected out of 2 times to 5 by the combination of changing the external capacitors VOUT. connection and "Booster Level Select" instruction. (refer (2-1)Instruction (p)Voltage Boost time select) Voltage Booster circuits requires the clock signals from internal oscillation circuit or the external clock signal, therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is in operation. The boosted voltage of VDD-V OUT must be 17V or less. VDD-VOUT The boost voltage and the capacitor connection are shown below. The boosted voltage and VDD,VSS VDD,VSS VDD=+3V DD=+3V VSS= + 0V SS= VOUT=-VDD=-3V OUT=-V DD=-3V VOUT=-2VDD=-6V OUT=-2VDD=-6V VOUT=-3VDD=-9V OUT=-3VDD=-9V VOUT=-4VDD=-12V OUT=-4VDD=-12V 2-time voltage 3-time voltage 4-time voltage 5-time voltage
Example of the external capacitor connection to the voltage booster circuits 5-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ + + + +
4-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VT OU
+ + + +
3-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ + +
2-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ +
NJU6678V
(3-2)Voltage Adjust Circuits The boosted voltage of VOUT outputs V5 for LCD driving through the voltage adjust circuits. The output voltage of V5 VOUT is adjusted by Ra and Rb within the range of |V5| < |V OUT|. |VOUT|. The output is calculated by the following formula(1). VLCD = VDD-V 5 = (1+Rb/Ra)V REG VDD-V5 (1+Rb/Ra)VREG
(1)
The VREG voltage is a reference voltage generated by the built-in bleeder registance. VREG is adjustable by EVR VREG VREG functions (see section 3-3). For minor adjustment of V5, it is recommended that the Ra and Rb is composed of R2 as variable resistor and R1 and R3 as fixed resistors, constant should be connected to VDD terminal,VR and V5 ,as shown below. VDD
VDD VREG R a R 1 V R R 2
V5 VOUT
R 3
R b
Fig. 4
< Design example for R1, R2 and R3 /Reference > *R1+R2+R3=6M R1+R2+R3=6M (Determind by the current between VDD-V5) VDD-V5) *Variable voltage range by the R2. -7V to -11V (V LCD=VDD-V5 : 10V to 12V) (VLCD=VDD-V5 (Determind by the LCD electrical characteristics) *VREG=3V (In case of VDD=3V and EVR=FFh) VDD=3V R1,R2 and R3 are calculated by above conditions and the fomula of (1) to below; R1=1.5M R1=1.5M R2=0.3M R2=0.3M R3=4.2M R3=4.2M Note) V5 voltage is generated referencing with VREG voltage beased on the supply voltage (V DD and VSS) as shown (VDD VSS) in above figure. Therefore, VLCD (V DD-V5) is affected including the gain (Rb/Ra) by the fluctuation of VREG voltage VLCD (VDD-V5) VREG based on the supply voltage. The power supply voltage should be stabilized for V5 stable operation.
NJU6678V
(3-3) Contrast Adjustment by the EVR function The EVR selects the VREG voltage out of the following 201 conditions by setting 8-bit data into the EVR register. With VREG the EVR function, VREG is controlled, and the LCD display contrast is adjusted. The EVR controls the voltage of VREG VREG VREG by instruction and changes the voltage of V5. A step with EVR is set like table shown below. 37H 4FH 37H to 4FH available for use. If keeping 3% precision, sets EVR over 4FH. 4FH
EVR register (0,0,1,1,0,1,1,1) : (0,1,0,0,1,1,1,1) : : (1,1,1,1,1,1,0,1) (1,1,1,1,1,1,1,0) (1,1,1,1,1,1,1,1) V REG[ V ] (100/300) x (VDD -V S S) : (124/300) x (VDD -V S S) : : (298/300) x (VDD -V S S) (299/300) x (VDD -V S S) (300/300) x (VDD -V S S) V LCD Low : : : : : : High
3FH : 4FH : : FDH F EH FFH
In use of the EVR function, the voltage adjustment circuit must turn on by the power supply instruction.
Adjustable range of the LCD driving voltage by EVR function The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors VDD Ra and Rb. [ Design example for the adjustable range / Reference ] - Condition VDD=3.0V, VSS=0V VDD=3.0V, VSS=0V Ra=1M Rb=4M Ra=1M , Rb=4M ( Ra:Rb=1:4 ) The adjustable range and the step voltage are calculated as follows in the above condition. In case of setting 4FH in the EVR register, 4FH VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(124/300) x 3.0] = 6.2V In case of setting FFH in the EVR register, FFH VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(300/300) x 3.0] = 15.0V
Min.4FH
Max.FFH 15.0 [V]
Adjustable Range Step Voltagre
6.2
-------------------
50
[mV]
* In case of VDD=3V VDD=3V
NJU6678V
(3-4) LCD Driving Voltage Generation Circuits The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the V5 voltage with the internal bleeder resisV1,V2,V3,V4 V5 tance and is supplied to the LCD driving circuits after the impedence conversion by the voltage follower. As shown in Figure 5, five external capacitors are required to connect to each LCD driving voltage terminal for voltage stabilization. The value of capacitors (C5 to C9) should be determined after the actual LCD panel display evaluation. (C5 C9
Using the internal Power Supply
Using the external Power Supply
VSS
VSS C 1+ C 1C 2+ C 2C 3+ C 3C 4+ *2 C 4V O UT
C1 COU T
+
C 1+ C 1-
+
C2
+
C 2+ C 2-
C3
+
C 3+ C 3-
C4
+
C 4+ C 4V OU T
NJU6678V
NJU6678V
R3 V5 *1 VR VR V5
R2
R1 VD D
V DD V1
+ + + + +
C5 C6 C7 C8 C9
V1 V2 V3 V4 V5
E xternal Voltage Generator
V2 V3 V4 V5
Reference set up valueVLCD=VDD-V5 = 10 to 12V valueVLCD=VDD-V5
COUT C1 to C4, C9 C5 to C8 R1 R2 R3 to 1uF to 1uF 0.1 to 0.47uF 1.5M 0.3M 4.2M
Fig.5 *1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal. *2 Following connection of VOUT is required when external power supply using. VOUT When VSS > V5 --- VOUT=V5 VSS V5 VOUT=V5 When VSS < V5 --- VOUT=VSS VSS V5 VOUT=VSS
NJU6678V
(4) MPU Interface (4-1) Interface type selection Two MPU interface types are available in the NJU6678V : by 1) 8-bit bi-directional data bus (D7 to D0), 2) serial data NJU6678V: input (SI:D7). The interface type (the 8 bit parallel or serial interface) is determined by the condition of the P/S terminals connecting to "H" or "L" level as shown in Table 5. In case of the serial interface, neither the status read-out nor the RAM data read-out operation is allowed. Table 5
P/S H L Type Parallel Serial CS CS CS A0 A0 A0 RD RD WR WR SEL68 SEL68 D7 D7 SI D6 D6 SCL D 0 to D5 D 0 to D5 Hi-Z
Parallel Interface The NJU6678V interfaces the 68- or 80-type MPU directly if the parallel interface (P/S="H") is selected. The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to "H" or "L" as shown in table 6. Table 6
SEL68 H L Type 68 type MPU 80 type MPU CS CS CS A0 A0 A0 RD E RD WR R/W WR D0 to D7 D0 to D7 D0 to D7
(4-2) Discrimination of Data Bus Signal The NJU6678V discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and (RD,WR) signals as shown in Table 7. Table 7
Common
A0 H H L L
68 type R/W H L H L
80 type RD WR L H H L L H H L
Function Read Display Data Write Display Data Status Read Write into the Register(Instruction)
(4-3) Serial Interface.(P/S="L") The serial interface of the NJU6678V consists of the 8-bit shift register and 3-bit counter. In case the chip is selected (CS=L), the input to D7(SI) and D6(SCL) becomes available, and in case that the chip isn't selected, the shift register and the counter are reset to the initial condition. The data input from the terminal(SI) is MSB first like as the order of D7, D6, *** D0 by a serial interface, it is ***D0 entered into with rise edge of serial clock(SCL). The data converted into parallel data of 8-bit with the rise edge of 8th serial clock and processed. It discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (8 X n)th of serial clock (SCL), it is recognized display data by A0=H" and instruction by A0="L". A0 input is read in the rise edge of (8 X n)th of serial clock (SCL) after chip select and distinguished. However,in case of RES="H" to "L" or CS="L" to "H" with trasfered data does not fill 8 bit, attention is necessary because it will processed as there was command input. Always, input the data of (8 X n) style. The SCL signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it.
C S
SI SL C A 0 1
D7 2
D6 3
D5 4
D4 5
D3 6
D2 7
D1 8
D0 9
D7
D 6 1 0
Fig. 6
NJU6678V
(4-4) Access to the Display Data RAM and Internal Register. The NJU6678V transfers data to the CPU through the bus holder with the internal data bus. In case of reading out the display data contents in the DD RAM, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data write cycle. Therefore, the limitation of the access to NJU6678V from MPU side is not access time (t ACC,tDS) of Display Data (tACC,tDS) RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the MPU becomes possible. In case of cycle time isn't met, the MPU inserts NOP operation only and becomes an equivalent to an execution of wait operation on the sutisfy condition in MPU. When setting an address, the data of the specified address isn't output immediately by the read operation after setting an address, and the data of the specified address is output at the the 2nd data read operation. Therefore, the dummy read is always necessary once after the address set and the write cycle. (See Fig. 7) The exsample of Read Modify Write operaion is mentioned in (2-1)Instruction -(q)The sequence of Inverse Display.
Write Operation
MU P W R DT AA N
N1 +
N+ 2
N3 +
Inter nal Ti min g
B sh u olde r
N
N+ 1
N2 +
N3 +
W R
Read Operation
MP U WR RD DA TA N
Address Set N
N
Dummy Read
n
Data Read n
n+1
Data Read n+1
Internal Timing
W R RD Column Address Bus holder
N N n
N+1 n+1
N+2 n+2
Fig.7 (4-6) Chip Select CS is the Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS="H" (Chip is not selected), the terminals of D0 to D7 are high impedance and A0, RD, WR, D7(SI) and D0 D7 D7 D6(SCL) inputs are ignored. If the serial interface is selected when CS="H", the shift register and the counter for the serial interface are reset. However, the reset signal is always input and executed in any conditions of CS.
NJU6678V
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Input Voltage Operating Temperature Storage Temperature SYMBOL VDD V5 V 1 to V4 V IN To p r T stg -55 to +100 (TCP) RATINGS -0.3 to +5.0 V D D- 17.0 to VD D +0.3 V 5 to VD D+ 0.3 -0.3 to VD D +0.3 -30 to +80 -55 to +125 (Chip)
(Ta=25 (Ta=25 C)
UNIT V V V V
C C
VDD
VDD
VSS
V5
Note 1) All voltage values are specified as VSS=0V. VSS=0V. Note 2) The relation of VDDV1V2V3V4V5>VOUT;VDD>VSSVOUT must be maintained. VDDV1V2V3V4V5>VOUT;VDD>VSS In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to NJU6678V at the mean time of turning on VDD power supply or after turned on VDD . VDD VDD In use of the voltage boost circuit, the condition that the supply voltage: 17.0V VDD-VOUT is necessary. 17.0V DD-V OUT Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the erectric characteristics conditions will cause malfunction and poor reliability. Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the VDD VSS voltage converter.
NJU6678V
ELECTRICAL CHARACTERISTICS (1)
PARAMETE Operating Voltage(1) OperatingVoltage(2) Input Voltage Output Voltage High Low High Low Level Level Level Level
SYMBOL
(VDD=2.5V to 3.3V, VSS=0V, Ta=-30 to +80C ) +80
CONDITIONS MIN. 2.5 VDD -17.0 TYP. MAX. 3.3 VDD -6.0 V DD
VDD-0.5VLCD
UNIT Note V V V V V V uA k uA uA 7 8 9 10 5 6
V DD V5 V 1,V 2 V 3,V 4 V IHC1 VILC1 VOHC11 VOLC11 ILIO RON1 RON2 ID D Q IDD12 IDD21 CIN fOSC tR tRW VLCD = VDD -V 5 D0...D7,A0, CS,RES,RD,WR,SEL68, P/S Terminals D0...D7 IOH=-0.5mA Terminals IOL= 0.5mA All Input terminals VLCD =15.0V VLCD =8.0V during Power save Mode Display V LCD=12.0V Accessing f CYC =200kHz A0,CS,RES,RD,WR,SEL68, P/S,T1,T2,D 0 ...D7 Ta=25C Ta=25C Ta=25C RES Terminal RES Terminal
VDD-0.5VLCD
V5 0.8V DD V SS 0.8V DD V SS - 1.0 2.0 3.0 0.05 15 600 10 26 1.0 10 32
V DD 0.2VDD V DD 0.2VDD 1.0 3.0 4.5 5 40 800
Input Leakage Current Driver On-resistance Stand-by Current Operating Current Input Terminal Capacitance Oscillation Frequency Reset tim e Reset "L" Level Pulse Width Output Volt.
pF 38 kHz us us
11 12
V OUT1 RTRI
V S S-Vout, 5-time voltage booster, V D D=3V V D D=3V;C OUT =1.0uF 5-time voltage booster Voltage Booster Circuit "OFF"
VD D-15.0V 4000
V D D-14.5V 6000
V
On-resistance
Adjustment range of LCD Voltage Driving Volt. Booster Voltage Follower Operating Current Voltage Reg.
VOUT2 Voltage Adjustment Circuit "OFF" V D D=3V, VLCD =12V COM/SEG Terminals Open No Access Display Checkered pattern V D D=3V,Ta=25C, V REG=4F to FFH
VD D-17.0V
VD D-6.0V
V 13
V5 IOUT1 IOUT2 IOUT3 V REG%
VD D-17.0V 160 35 25
VD D-6.0V 320 70 50 3
V
uA %
14
Note 5) Although the NJU6678V can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with MPU. Note 6) The operating voltage when using external power supply. Note 7) RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals RON (V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of Operating Voltage(2). Note 8,9) The value of after Driver Output On instruction execution. Note 8,9) Refers to the current consumption of the IC itself; external power supply is used for the LCD driving. In case of not use internal power supply circuit,meaning current of IC's. LCD driving power supply are external power supply. Note 8) Applicable in case of not accessing to the MPU. Note 9) The operating current when writing a vertical stripe pattern on the tcyc. Current consumption during the access is approximately proportional to the access frequency. When not accessed, it consumpts only IDD01 IDD01 Note 10) Apply to A0, D0-D7, RD,WR,CS,RES,SEL68,P/S,T1,T2 terminals. D0-D7 RD,WR,CS,RES,SEL68,P/S,T1,T2
NJU6678V
Note 11) tR ( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RES tR signal. Note 12) Apply minimum pulse width of the RES signal. To reset, the "L" pulse over tRW shall be input. . tRW Note 13) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage. Note 14) Each operating current shall be defined as being measured in the following condition.
Status SYMBOL IOUT1 IOUT2 IOUT3 T1 L H H T2 L/H L H Internal Oscillator Validity Validity Validity Operating Condition Voltage Voltage Booster Adjustment Validity Validity Invalidity Validity Invalidity Invalidity
External Voltage Supply (Input Terminal)
Voltage Follower Validity Validity Validity
Unuse Use(VOUT) Use(VOUT,V 5)
MEASUREMENT BLOCK DIAGRAM :IOUT1 :IOUT1
VDD VR V5
A
VS C S 1+ +
NJU6678 NJU6678V
C1-C2+ + + C 2- C3+ + C3 -C4+ + C4VU OT
T 1
T 2
:IOUT2 :IOUT2
VDD VR V5
A
VS C+ S 1
NJU6678 NJU6678V
C-C + 1 2 C2 C+ 3 C -C + 34 C4 VU OT
T 1
T 2
:IOUT3 :IOUT3
VDD VR V5
A
VS C+ S 1
NJU6678 NJU6678V
C-C + 1 2 C2 C+ 3 C -C + 34 C4 VU OT
T 1
T 2
NJU6678V
BUS TIMING CHARACTERISTICS - Read/Write operation sequence (80 Type MPU)
tCYC8 A 0,C S tAW8 tCCL tCCH tA H8
WR R, D
tDS8
tDH8
D0 to D7 ( rite) W
tf
tr
tA CC
tO H8
D0 to D7 ( ea R d)
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
PARAMETER Address Hold Time Address Set Up Time System Cycle WR Time RD
WR,"L"
A0,CS Terminals
SYMBOL tAH8 tAW8
tCYC8 (W)
MIN. 10 0 270 350 50 200 220 150 35 15 0
TYP.
MAX.
CONDITION
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
220
Control Pulse Width
RD,"L"
WR,"H"
WR,RD Terminals
RD,"H"
Data Set Up Time Data Hold Time RD Access Time Output Disable Time Rise Time, Fall Time
D0 to D7 Terminals
CS, WR, RD, A0, D0 to D7 Terminals
tCYC8 (R) tCCL(W) tCCL(R) tCCH(W) tCCH(R) tDS8 tDH8 tACC8 tOH8 tr,tf
160
120 50 15
CL=100pF
Note 15) All timing based on 20% and 80% of VDD voltage level. VDD
NJU6678V
- Read/Write operation sequence (68 Type MPU)
tCYC6 tE WL E tA W6 RW / tr tEWH tf tA H6
A0, S C tDS6 D0 to D7 ( rite) W tACC6 D0 to D7 ( ea R d) tO H6 tDH6
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
SYMBOL PARAMETER Address Hold Time tAH6 Address Set Up Time A0,CS,R/W tAW6 Terminals tCYC6(W) System Cycle Time(W) System Cycle Time(R) tCYC6(R) Read"H" Write"H" Enable Pulse Width Read"L" Write"L" Data Set Up Time Data Hold Time Access Time Output Disable Time
tEWH E Terminal tEWL tDS6 tDH6 tACC6 tOH6 tr,tf
D0 to D7 Terminals
A0, CS, R/W, E, D0 to D7 Terminals
MIN. 10 0 270 350 200 50 220 150 35 15 0
TYP.
MAX.
CONDITION UNIT
220
160
200 50 15
CL=100pF
ns ns ns ns ns ns ns ns ns ns ns ns ns
Rise Time, Fall Time
Note 16) All timing are based on 20% and 80% of VDD voltage level. VDD Note 17) tCYC6 shows the cycle of the E signal in active CS.
NJU6678V
- Write operation sequence (Serial Interface)
tCSS C S
tCS H
tSAS A 0
tSAH
tSCYC tSLW SL C tSHW
tS DS SI
tSDH
tf
tr
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
PARAMETER SYMBOL Serial Clock cycle tSCYC SCL SCL "H" pulse width tSHW Terminal SCL "L" pulse width tSLW Address Set Up Time tSAS A0 Terminal Address Hold Time tSAH Data Set Up Time tSDS SI Terminal Data Hold Time tSDH CS-SCL Time CS Terminal SCL, A0, CS, SI Terminals tCSS tCSH tr,tf MIN. 120 40 80 0 150 25 10 10 300 15 TYP. MAX. CONDITION UNIT ns ns ns ns ns ns ns ns ns ns
Rise Time, Fall Time
Note 18) All timing are based on 20% and 80% of VDD voltage level. VDD Note 19) When inputting an instruction continuously, keep 450nS as the cycle of SCL between the instructions as follows SCL 8th clock SCL 1st clock
SCL
Instruction N
450 ns SCL"L"pulse width (Between the instruction and next)
Instruction N+1
NJU6678V
LCD DRIVING WAVEFORM
0 VD D FR VSS VDD V1 V2 C OM 0 V3 V4 V5 VDD V1 V2 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 C OM 2 VDD V1 V2 V3 V4 V5 C OM 1 V3 V4 V5
1
2
3
4
1 21 3 00
0
1
2
3
4
5
1 21 3 0 0
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
SEG0
SEG1
SEG2
SEG3
SEG4
VDD V1 V2 SEG0 V3 V4 V5 VDD V1 V2 SEG1 V3 V4 V5
V5 V4 V3 V2 V1 COM0-SEG0 VD D
-V1 -V2 -V3 -V4 -V5
V5 V4 V3 V2 V1 COM0-SEG1 VD D
-V1 -V2 -V3 -V4 -V5
NJU6678V
APPLICATION CIRCUIT MPU Interface (examples) The NJU6678V is connectable to 80-type MPU or 68-type. In use of Serial Interface, it is possible to be controlled by the signal line with the more small being. *:SEL68 terminal shall be connected to VDD or VSS. VDD VSS. - 80 Type MPU
VCC A0 A0 VDD SEL68 A1 to A7 IORQ CS
Decoder NJU6678 NJU6678V
MPU
D0 to D7 RD WR GND RES
D0 to D7 RD WR RES VSS P/S
RESET
- 68 Type MPU
VCC VDD SEL68 A1 to A15 VMA CS
A0
A0
Decoder
MPU
D0 to D7 E R/W GND RES
NJU6678V NJU6678
D0 to D7 E R/W RES VSS P/S
RESET
- Serial Interface
VCC
A0
A0
VDD SEL68
A1 to A7
CS
Decoder MPU
Port1 Port2 SI SCL P/S GND RES RES VSS
NJU6678V NJU6678
VDD OR GND
RESET
NJU6678V
LCD Panel Interface Example
LCD Pan el (104 x 132)
C0
C 51
S0
S 131
C 103
C52
NJU6678 NJU6678V
BOTTOM VIEW
CAUTION The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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