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NJU7380
STEPPER MOTOR CONTROLLER
s GENERAL DESCRIPTION NJU7380 is a controller with transrator which convert from input step and direction pulse to driver's phase signal for full and half step. NJU7380 translates from pulse input signal (Serial interface) to phase signal input, so NJM3700 series dual channel bipolar drivers or NJM2672 dual H-bridge driver can be easily controlled by a micro processor . NJU7380 is also including Auto Current Down (ACD) circuit which is suitable for reducing power dissipation of power devices and motor. s PACKAGE OUTLINE
NJU7380E
s FEATURES * Operating Voltage VDD=4.75 5.25V * Absolute Maximum Voltage 7V * Half -step and Full - step Operation * Internal Phase Logic * Phase Logic Reset Terminal(RESET) * Internal Auto Current Down Function * Specially matched to NJM3775,NJM3777 and NJM2672. * C-MOS Technology * Package Outline EMP14
s PIN CONFIGURATIONS
1 2 3
14 13 12 11
4 5 6 7
10 9 8
1. DIR 2. STEP 3. HSM 4. RESET 5. Ct 6. SGND 7. PGND
8. MO 9. ACD 10. Dis2 11. Dis1 12. PB 13. PA 14. VDD
Fig. 1Pin Configurations
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NJU7380
s BLOCK DIAGLAM
VDD
POR
PA STEP DIR HSM RESET Phase Logic & ACD Logic PB Dis1
Dis2 Ct SGND ACD
MO PGND
Fig.2 Block Diagram
s PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin name DIR STEP HSM RESET MO Ct SGND PGND ACD DIS2 DIS1 P2 P1 VDD Description Direction command input for determining motor turning direction Motor steeping pulse input, phase logic operation triggered by negative edge of STEP signal Half/Full step mode switching input H level in full step mode and L level in half step mode Phase logic initial input Phase output initial status detection output A value of connected capacitor determines lock detection time (Ton) and auto resume time (Toff) SGND (Logic GND) and PGND (Analog GND) is not connect in the IC
SGND and PGND pins should be connected ground respectively.
Auto Current Down output terminal L level in active Step sequence output terminals P1/DIS1(P2/DIS2) determine a sequence output on Phase1(2) for driver IC P1(P2) determine a motor current direction on Phase1(2) for driver IC DIS1(DIS2) determine a phase current OFF mode at the half-step Logic power supply voltage terminal
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NJU7380
s ABSOLUTE MAXIMUM RATINGS PARAMETER RATINGS Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Power Dissipation +7.0 -0.3 VDD+0.3 10 -40 85 -40 +125 300 (Ta=25C) NOTE
SYMBOL [unit] VDD[V] VID[V] IO [mA] TOPR[C] TSTG [C] PD [mW]
Device itself
s RECOMMENDED OPERATING CONDITIONS VDD=4.75V5.25V s ELECTRICAL CHARACTERISTICS PARAMETER SYSMBOL Operating Current H Level Input Voltage L Level Input Voltage H Level Input Current L Level Input Current Phase Output Saturation Voltage DIS Output Saturation Voltage VR Detection Voltage MO Output Saturation Voltage Output Leak Current Power Down ON Time Turn ON Time Turn OFF Time Set-up Time Step-pulse Continuation Time IDD VIH VIL IIH IIL VP VDIS VVR VMO ILEAK TON TDON TDOFF TS VSPC (V+=5V, Ta=25C) TYP. MAX. UNIT 3.0 100 -100 200 4.0 1.5 150 -150 0.5 0.5 0.5 0.5 1 260 3 3 mA V V A A V V V V A ms s s ns ns
CONDITION IP=5mA IDIS=5mA IMO=5mA IMO=5mA VDD =7V CT=0.1F -
MIN. 3.5 140 400 800
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NJU7380
s APPLACATION INFORMATION
VCC +5V R1 R3 9 ACD 13 PA 11 Dis1 12 10 MO +5V R2 GND(VCC) 4x10k 9 Phase1 12 4 19 VCC VMM1 VMM1 MA1 MB1 10k + 10F VMM
4.7F
0.1F
STEP Direction Half Full Step RESET
2 1 3 4 5
14 VDD SETP DIR HSM
3 1
NJU 7380
10 Dis1 7 VR1 14 Phase2
RESET Ct SGND 6 PGND 7
NJM3775
MA2 MB1 C1 RC GND E1 11 5,6, 8 2 17,18 RS 0.47 RS 0.47 E2 C2 15 21
PB Dis2
20 22 STEPPER MOTOR Pin number refer to DIP package GND(VMM)
MO 8
12 Dis2 16 VR2 12k 4700pF
Fig.3 Typical stepper motor driver application with NJM3775.
s FUNCTIONAL DESCRIPTION NJU7380 is a transrator, intended to convert from input step and direction pulse to driver's phase signal for 2phase stepper motor driver. Motor control is simply attained only by the pulse generator because you use it by NJM3775 and the set. s LOGIC INPUT NJU7380 contains all phase logic necessary to control the motor in a proper way. If any of the logic inputs are left open, the circuit will accept it as a HIGH level. In order to make noise-proof nature into the maximum, it is necessary to connect an idle input terminal to VDD level. * STEP - Stepping pulse The built-in phase logic sequencer goes UP on every negative edge of the STEP signal (pulse). In full step mode, the pulse turns the stepping motor at the basic step angle. In half step mode, two pulses are required to turn the motor at the basic step angle. The DIR (direction) signal and HSM (half/full mode) are latched to the STEP negative edge and must therefore be established before the start of the negative edge. Note the setup time ts in Figure 4. * DIR - direction The DIR signal determines the step direction. The direction of the stepping motor depends on how the NJU7380 and NJM3775 are connected to the motor. Although DIR can be modified this should be avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See the timing chart in Figure 4.
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NJU7380
* HSM - half/full step mode switching This signal determines whether the stepping motor turns at half step or full step mode. The built-in phase logic is set to the half step mode when HSM is low level. Although HSM can be modified this should be avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See the timing chart in Figure 4. * RESET A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every eight pulses in the half step mode. RESET forces to initialize the phase logic to sequence start mode. When RESET is at L level, the phase logic is initialized and the energizing pattern of phase logic at sequence start is output. At this time, the STEP input of phase logic will be ignored during the RESET is at level. s POR - power on and reset function The internal power-on and reset circuit, which is connected to Vcc, resets the phase logic and turns off phase output when the power is supplied to prevent missteps. Each time the power is turned on, the energizing pattern of phase logic at sequence start is output. s MO - origin monitor At sequence start of the phase logic or after POR or external RESET, an L level output is made to indicate to external devices that the energizing sequence is in initial status. In a system using a stepping motor, the device sensor and the MO AND function enable a higher resolution detection of motor origin.
HSM,DIR
STEP,RESET
ts Vp
tp
td
Fig.4 Timing chart
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NJU7380
s TIMING CHART
DIR
POR 1 2 3 4 1 2 3 4 1
H H H
Fig.5-1 Full-step mode,forward 4-step sequence
HSM STEP
PA PB DISA DISB MO
OFF OFF ON ON ON
Fig.5-2 Full-step mode,reverse 4-step sequence
POR
1
2
3
4
1
2
3
4
1
DIR HSM STEP
L H H
PA PB
OFF OFF
DISA ON DISB ON MO ON
POR
1
2
3
4
5
6
7
8
1
Fig.5-3 Half-step mode,forward 8-step sequence
DIR HSM STE
H L H
PA PB
OFF OFF
DISA ON DISB ON MO ON
POR
1
2
3
4
5
6
7
8
1
Fig.5-4 Half-step mode,reverse 8-step sequence
DIR HSM STEP
L L H
PA PB DISA DISB MO
OFF OFF ON ON ON
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NJU7380
s ACD - auto current down function The ACD feature monitors step signals and sets the ACD pin output to H when the negative edge of a STEP signal is input. It then sets the ACD output to L after a time (TON) that is fixed by the capacitor that is connected to the Ct pin. By combining this pin with the VR pin that determines motor current for the NJM3775 motor, it is possible to reduce current when stopping the motor. If the next negative edge of a STEP is input during the time TON, an internal retrigger will operate, maintaining the ACD pin's H output. That is, after the final negative edge of a STEP is input, ACD H output is maintained during the time TON, after which it is set to L. The time TON must be long enough to securely stop the stepping motor. Approximately 100mS is usually sufficient for normal applications. The following expression determines the time TON.
Ton[ms]=3x109xCt[F]
STEP
PA PB AC D CT
Normal Revolution State TON ACD Operation State TON
TON=2x106xCT
Fig.6 ACD Operation Timing Diagram
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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