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| NJU7704/05 VOLTAGE DETECTOR ! GENERAL DESCRIPTION The NJU7704/05 is a low quiescent current voltage detector featuring high precision detection voltage. The detection voltage is internally fixed with an accuracy of 1.0%. The NJU7704/05 are useful for preventing malfunction of microcomputer or DSP etc. through detect a drop in voltage of battery or power supply. The delay function achieves set wait time when supply voltage is unstable. Moreover, the delay function can make a sequence that other devices in application work and stabilize before microcomputer or DSP works. Delay time can be set by an external capacitor. Manual reset function can output reset signal irrespective of detection voltage. NJU7704 is Nch. Open Drain and NJU7705 is a C-MOS output type. Small packaging makes NJU7704 and NJU7705 suitable for space conscious applications. ! FEATURES " High Precision Detection Voltage 1.0% " Low Quiescent Current 0.9A typ. " Detection Voltage Range 1.56.0V(0.1V Step) " Adjustable delay time with external capacitor " Manual Reset Active "L" : NJU770****A Active "H" : NJU770****B " Output Configuration NJU7704: Nch. Open Drain type NJU7705: C-MOS Output type " Package Outline SOT-23-5: NJU770*F SC88A : NJU770*F3 ! PIN CONFIGURATION 5 4 ! PACKAGE OUTLINE NJU7704/05F NJU7704/05F3 123 NJU770*F/F3 PIN FUNCTION 1.Cd 2.VSS 3.MR 4.VOUT 5.VDD Ver.2005-02-28 -1- NJU7704/05 ! EQUIVALENT CIRCUIT VDD VDD Delay Circuit VREF VOUT VREF Delay Circuit VOUT VSS VSS Cd MR Cd MR NJU7704***A NJU7704F**B VDD VDD Delay Circuit VREF VOUT VREF Delay Circuit VOUT VSS VDD Cd MR Cd MR NJU7705***A NJU7705***B ! DETECTION VOLTAGE RANK LIST Device Name VDET MR Logic NJU770*F3-/F15A 1.5V NJU770*F3-/F19A 1.9V NJU770*F3-/F02A 2.0V NJU770*F3/F21A 2.1V NJU770*F3-/F22A 2.2V NJU770*F3-/F23A 2.3V NJU770*F3-/F25A 2.5V NJU770*F3-/F27A 2.7V Active "L" NJU770*F3-/F28A 2.8V NJU770*F3-/F29A 2.9V NJU770*F3-/F03A 3.0V NJU770*F3-/F32A 3.2V NJU770*F3-/F39A 3.9V NJU770*F3-/F42A 4.2V NJU770*F3-/F43A 4.3V NJU770*F3-/F45A 4.5V NJU770*F3-/F06A 6.0V NJU770*F3-/F19B 1.9V Active "H" NJU770*F3-/F27B 2.7V NJU770*F3-/F28B 2.8V -2- Ver.2005-02-28 NJU7704/05 ! NJU7704 ! ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Input Voltage VDD Output Voltage VOUT Input Voltage of Cd pin VCd Input Voltage of MR pin VMR Output Current IOUT (Ta=25C) RATINGS UNIT +10 V V VSS-0.3+10 V VSS-0.3VDD+0.3 V VSS-0.3VDD+0.3 50 mA 350(*1) SOT-23-5 Power Dissipation PD mW 200(*2) SC88A 250(*1) Operating Temperature Topr -40 +85 C Storage Temperature Tstg -40 +125 C (*1) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers) (*2) : Device itself ! ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Detection Voltage VDET Hysteresis Voltage VHYS Quiescent Current Output Current Output Leak Current Detection Voltage Temperature Coefficient Delay Time Input Voltage of MR pin (Active "L") Input Voltage of MR pin (Active "H") Impedance of MR pin Operating Voltage (*3) ISS IOUT ILEAK VDET /Ta td VMR_H VMR_L VMR_H VMR_L RMR VDD (Ta=25C) MAX. UNIT +1.0% V 130 mV 1.5 A 2.0 mA 0.1 A 12 VDD 0.3 VDD VDD-1.5 3.0 ppm/C ms V V M TEST CONDITION VDD=VDET+1V Nch,VDS=0.5V VDD=VOUT=9V Ta=0+85C VDET=1.5V1.9V Version VDET=2.0V6.0V Version VDD=1.2V VDD=2.4V (2.7V Version) MIN. -1.0% 70 0.75 4.5 8 1.5 0 VDD-0.3 0 1.0 TYP. 90 0.7 0.9 2.0 7.0 100 10 2.0 VDD=VDET+1V, Cd=4.7nF 0.8 9 V RL=100k (*3): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT becomes 10% or less of the input voltage(VDD). Ver.2005-02-28 -3- NJU7704/05 ! TEST CIRCUIT " Circuit Operating Current TEST CIRCUIT ISS A V DD " Detection voltage/Minimum operating voltage V DET / V OPL RL V DD V OUT V MR V OUT V OUT V DD V NJM7704 V DD Cd V SS MR NJM7704 Cd V SS " MR pin Input voltage TEST CIRCUIT " Leak current / Output current TEST CIRCUIT RL V DD V DD Cd V OUT V MR V MR V V MR V OUT V DD Cd V DD V OUT ILEAK / IOUT A NJM7704 NJM7704 MR V OUT / V DS V SS V SS " Delay time TEST CIRCUIT Oscilloscope RL V DD V DD Cd Cd V OUT ch1 ch2 NJM7704 MR V SS -4- Ver.2005-02-28 NJU7704/05 ! TYPICAL APPLICATION 1 Power Supply Monitor Circuit (VDD line COMMON) V DD RL V DD V OUT Reset Signal INPUT Micro-Processor etc NJM7704 Cd Cd MR V SS 2 Power Supply Monitor Circuit (VDD line SEPARATE) V DD1 V DD2 RL V DD V OUT Reset Signal INPUT Micro-Processor etc NJM7704 Cd Cd MR V SS Ver.2005-02-28 -5- NJU7704/05 ! NJU7705 ! ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Input Voltage VDD Output Voltage VOUT Input Voltage of Cd pin VCd Input Voltage of MR pin VMR Output Current IOUT (Ta=25C) RATINGS UNIT +10 V V VSS-0.3+10 V VSS-0.3VDD+0.3 V VSS-0.3VDD+0.3 50 mA 350(*4) SOT-23-5 Power Dissipation PD mW 200(*5) SC88A 250(*4) Operating Temperature Topr -40+85 C Storage Temperature Tstg -40+125 C (*4) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers) (*5) : Device itself ! ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Detection Voltage VDET Hysteresis Voltage VHYS Quiescent Current ISS (Ta=25C) MAX. UNIT +1.0% V 130 mV 1.5 A 2.0 mA - TEST CONDITION VDD=VDET+1V Nch,VDS=0.5V Output Current IOUT Pch,VDS=0.5V 3.0 5.0 Detection Voltage Temperature VDET /Ta Ta=0+85C 100 ppm/C Coefficient Delay Time td VDD=VDET+1V, Cd=4.7nF 8 10 12 ms VMR_H 1.5 VDD Input Voltage of V MR pin (Active "L") 0 0.3 VMR_L VMR_H VDD-0.3 VDD Input Voltage of V MR pin (Active "H") 0 VDD-1.5 VMR_L Impedance of 1.0 2.0 3.0 RMR M MR pin Operating Voltage 0.8 9 V VDD RL=100k (*6) (*6): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT becomes 10% or less of the input voltage(VDD). VDET=1.5V2.9V Version VDET=2.6V6.0V Version VDD=1.2V VDD=2.4V (2.7V Version) VDD=4.8V (3.9V Version) VDD=6.0V (4.05.6V Version) VDD=8.4V (5.7V Version) MIN. -1.0% 70 0.75 4.5 2.0 2.5 TYP. 90 0.7 0.9 2.0 7.0 3.5 4.0 -6- Ver.2005-02-28 NJU7704/05 ! TEST CIRCUIT " Circuit Operating Current TEST CIRCUIT ISS A V DD " Detection voltage TEST CIRCUIT V OUT V DET V V DD V OUT V MR V OUT NJM7705 V DD Cd V SS MR NJM7705 Cd V SS " MR pin Input voltage TEST CIRCUIT " Nch Output current TEST CIRCUIT IOUT V DD V DD Cd V OUT V MR V MR V V MR V OUT V DD Cd V DD V OUT A NJM7705 NJM7705 MR V DS V SS V SS " Pch Output current TEST CIRCUIT " Delay time TEST CIRCUIT Oscilloscope V DS IOUT V DD V DD Cd V OUT A V DD MR Cd Cd V DD V OUT ch1 ch2 NJM7705 NJM7705 MR V SS V SS " Minimum operating voltage TEST CIRCUIT RL V OPL V V DD Cd V DD V OUT V MR V OUT NJM7705 V SS Ver.2005-02-28 -7- NJU7704/05 ! TYPICAL APPLICATION 1 Power Supply Monitor Circuit (VDD line COMMON) V DD V DD V OUT NJM7705 Cd Cd MR Reset Signal INPUT Micro-Processor etc V SS -8- Ver.2005-02-28 NJU7704/05 ! FUNCTIONAL DESCRIPTION (1) Basic Operation Supply voltage (VDD) Detection voltage (VDET) Minimum operation voltage (VOPL) VSS Hysteresis voltage (VHYS) Release voltage (VDET + VHYS) Output voltage (VOUT) (1) When supply voltage(VDD) drops below detection voltage(VDET), Output voltage(VOUT) changes "H" to "L" to alert reset state. (2) The reset state is kept while VDD is lower than release voltage. The release voltage is a sum of VDET and Hysterisis voltage (VHYS). Please refer to the (*7) below. (3) When VDD becomes higher than the release voltage and reset release delay time set by the external capacitors is past, then VOUT changes from "L" to "H" to resume normal state. VSS (*7) VHYS is to avoid unstable VOUT state caused by rapid voltage change at nearby VDET. Delay time (*8): C-MOS output product (NJU7705) : When VDD less than VOPL, VOUT is free of the shaded region. (2) Description of Delay Time Delay time can be set by the external capacitor. The delay time is given by the following: External delay capacitor (nF) = Required delay time : td(ms) / 10(ms) x 4.7(nF) NJU7704/05 Delay time vs Delay Capacitor (Cd) 10000 1000 Delay time : tdms 100 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 Delay Capacitor : CdnF Ver.2005-02-28 -9- NJU7704/05 (3) Description of Manual Reset Reset signal can output independently with MR. Logic of MR Operation Active "L" VMR= "L" => Reset "ON" Active "H" VMR= "H" => Reset "ON" If Manual Reset is not required, please connect MR terminal as following. Logic of MR Connection Active "L" Connect MR terminal to VDD or open Active "H" Connect MR terminal to GND or open [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2005-02-28 |
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