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| DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-- 65 MHz August 1998 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-- 65 MHz General Description The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode (< 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 227 Megabytes/sec bandwidth Up to 1.8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Transmitter Compatible with TIA/EIA-644 LVDS standard ESD rating > 7 kV Block Diagram DS90CF383 DS100033-1 Order Number DS90CF383MTD See NS Package Number MTD56 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1999 National Semiconductor Corporation DS100033 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +4V CMOS/TTL Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 4 sec) +260C Maximum Package Power Dissipation Capacity @ 25C MTD56 (TSSOP) Package: DS90CF383 1.63 W Package Derating: DS90CF383 ESD Rating (HBM, 1.5 k, 100 pF) 12.5 mW/C above +25C > 7 kV Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 -10 0 Nom 3.3 +25 Max 3.6 +70 2.4 100 Units V C V mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOD VOS VOS IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between complimentary output states Offset Voltage (Note 4) Change in VOS between complimentary output states Output Short Circuit Current Output TRI-STATE (R) Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case RL = 100, CL = 5 pF, Worst Case Pattern (Figures 1, 3) RL = 100, CL = 5 pF, 16 Grayscale Pattern (Figures 2, 3) f = 32.5 MHz f = 37.5 MHz f = 65 MHz f = 32.5 MHz f = 37.5 MHz f = 65 MHz 31 32 37 23 28 31 10 45 50 55 35 40 45 55 mA mA mA mA mA mA A VOUT = 0V, RL = 100 Power Down = 0V, VOUT = 0V or VCC VCM = +1.2V -100 -3.5 1.125 1.25 IOH = -0.4 mA IOL = 2 mA ICL = -18 mA VOUT = VCC, GND, 2.5V or 0.4V VOUT = 0V RL = 100 250 Conditions Min 2.0 GND 2.7 3.3 0.1 -0.79 0.3 -1.5 Typ Max VCC 0.8 Units V V V V V A mA mV mV V mV mA A mV mV A A CMOS/TTL DC SPECIFICATIONS 5.1 -60 345 10 -120 450 35 1.375 35 -5 LVDS DC SPECIFICATIONS 1 10 +100 10 10 ICCTG Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down Power Down = Low Driver Outputs in TRI-STATE (R) under Power Down Mode Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. www.national.com 2 Electrical Characteristics (Continued) Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and V OD). Note 4: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TCIT TCCS TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TCIP TCIH TCIL TSTC THTC TCCD TPLLS TPDD Parameter LVDS Low-to-High Transition Time (Figure 3 ) LVDS High-to-Low Transition Time (Figure 3 ) TxCLK IN Transition Time (Figure 4 ) TxOUT Channel-to-Channel Skew (Figure 5 ) Transmitter Output Pulse Position for Bit 0 (Figure 12 ) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 TxCLK IN Period (Figure 6) TxCLK IN High Time (Figure 6) TxCLK IN Low Time (Figure 6) TxIN Setup to TxCLK IN (Figure 6) TxIN Hold to TxCLK IN (Figure 6) TxCLK IN to TxCLK OUT Delay 25C, VCC = 3.3V (Figure 7 ) Transmitter Phase Lock Loop Set (Figure 8 ) Transmitter Power Down Delay (Figure 11) f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz -0.4 1.8 4.0 6.2 8.4 10.6 12.8 15 0.35T 0.35T 2.5 0 3 5.5 10 100 250 0 2.2 4.4 6.6 8.8 11 13.2 T 0.5T 0.5T 0.3 2.5 4.7 6.9 9.1 11.3 13.5 50 0.65T 0.65T Min Typ 0.75 0.75 Max 1.5 1.5 5 Units ns ns ns ps ps ns ns ns ns ns ns ns ns ns ns ns ns ms ns AC Timing Diagrams DS100033-4 FIGURE 1. "Worst Case" Test Pattern 3 www.national.com AC Timing Diagrams (Continued) DS100033-5 FIGURE 2. "16 Grayscale" Test Pattern (Notes 5, 6, 7, 8) Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. DS100033-6 FIGURE 3. DS90CF383 (Transmitter) LVDS Output Load and Transition Times DS100033-8 FIGURE 4. DS90CF383 (Transmitter) Input Clock Transition Time www.national.com 4 AC Timing Diagrams (Continued) DS100033-9 Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low High Edge FIGURE 5. DS90CF383 (Transmitter) Channel-to-Channel Skew and Pulse Width DS100033-10 FIGURE 6. DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) DS100033-12 FIGURE 7. DS90CF383 (Transmitter) Clock In to Clock Out Delay 5 www.national.com AC Timing Diagrams (Continued) DS100033-14 FIGURE 8. DS90CF383 (Transmitter) Phase Lock Loop Set Time DS100033-16 FIGURE 9. Seven Bits of LVDS in Once Clock Cycle DS100033-17 FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com 6 AC Timing Diagrams (Continued) DS100033-18 FIGURE 11. Transmitter Power Down Delay DS100033-26 FIGURE 12. Transmitter LVDS Output Pulse Position Measurement DS90CF383 Pin Description -- FPD Link Transmitter Pin Name TxIN TxOUT+ TxOUT- FPSHIFT IN TxCLK OUT+ TxCLK OUT- PWR DOWN VCC I/O I O O I O O I I No. 28 4 4 1 1 1 1 4 Description TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines -- FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. Power supply pins for TTL inputs. 7 www.national.com DS90CF383 Pin Description -- FPD Link Transmitter Pin Name GND PLL VCC PLL GND LVDS VCC LVDS GND I/O I I I I I No. 4 1 2 1 3 Ground pins for TTL inputs. Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs. Description (Continued) Applications Information The DS90CF383 and DS90CF384 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF583 and DS90CF584). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of both the transmitter and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90CF383 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant. Pin Diagram DS90CF383 DS100033-23 Application DS100033-3 www.national.com 8 9 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-- 65 MHz Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF383MTD NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. |
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