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DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link-- 65 MHz
July 1997
DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link-- 65 MHz
General Description
The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
Features
n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 171 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design (< 550 mW typ) Power-down mode saves power (< 0.25 mW) PLL requires no external components Low profile 48-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Single pixel per clock XGA (1024 x 768) Supports VGA, SVGA, XGA and higher 1.3 Gbps throughput
Block Diagrams
DS90CF563 DS90CF564
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Order Number DS90CF563MTD See NS Package Number MTD48
Order Number DS90CF564MTD See NS Package Number MTD48
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1998 National Semiconductor Corporation
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Block Diagrams
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +6V CMOS/TTL Input Voltage -0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 4 sec) +260C Maximum Package Power Dissipation @ +25C MTD48 (TSSOP) Package:
DS90CF563 1.98W DS90CF564 1.89W Package Derating: DS90CF563 16 mW/C above +25C DS90CF564 15 mW/C above +25C This device does not meet 2000V ESD rating (Note 4) .
Recommended Operating Conditions
Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 4.75 -10 0 Nom 5.0 +25 Max 5.25 +70 2.4 100 Units V C V mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOD VCM VCM VOH VOL IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between Complementary Output States Common Mode Voltage Change in VCM between Complementary Output States High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Output TRI-STATE (R) Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V VIN = 0V RL = 100, CL = 5 pF, Worst Case Pattern (Figure 1, Figure 3) RL = 100, CL = 5 pF, 16 Grayscale Pattern (Figure 2, Figure 3) VCC = 5.5V VOUT = 0V, RL = 100 Power Down = 0V, VOUT = 0V or VCC V = +1.2V -100 0.9 1.3 1.01 -2.9 -5 1.1 IOH = -0.4 mA IOL = 2 mA ICL = -18 mA VIN = VCC, GND, 2.5V or 0.4V VOUT = 0V R = 100 250 Conditions Min 2.0 GND 3.8 4.9 0.1 -0.79 0.3 -1.5 Typ Max VCC 0.8 Units V V V V V A mA mV mV V mV V V mA A mV mV CMOS/TTL DC SPECIFICATIONS
5.1
10
-120
LVDS DRIVER DC SPECIFICATIONS
L
290
450 35
1.25 1.375 35 1.6
1
10
+100
LVDS RECEIVER DC SPECIFICATIONS
CM
10 10
49 51 70 40 41 55 63 64 84 55 55 67
A A mA mA mA mA mA mA
TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current, Worst Case Transmitter Supply Current, 16 Grayscale f = 32.5 MHz f = 37.5 MHz f = 65 MHz f = 32.5 MHz f = 37.5 MHz f = 65 MHz
ICCTG
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Electrical Characteristics
Symbol ICCTZ Parameter Transmitter Supply Current, Power Down Receiver Supply Current, Worst Case ICCRG Receiver Supply Current, 16 Grayscale ICCRZ Receiver Supply Current, Power Down
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Over recommended operating supply and temperature ranges unless otherwise specified Conditions Power Down = Low Min Typ Max Units TRANSMITTER SUPPLY CURRENT 1 25 A
RECEIVER SUPPLY CURRENT ICCRW CL = 8 pF, Worst Case Pattern (Figure 1, Figure 4) CL = 8 pF, 16 Grayscale Pattern (Figure 2, Figure 4) Power Down = Low f = 32.5 MHz f = 37.5 MHz f = 65 MHz f = 32.5 MHz f = 37.5 MHz f = 65 MHz 64 70 110 35 37 55 1 77 85 140 55 55 67 10 mA mA mA mA mA mA A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and V OD). Note 4: ESD Rating: HBM (1.5 k, 100 pF) PLL V CC 1000V All other pins 2000V EIAJ (0, 200 pF) 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TCIT TCCS TCCD TCIP TCIH TCIL TSTC THTC TPDD TPLLS TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 Parameter LVDS Low-to-High Transition Time (Figure 3) LVDS High-to-Low Transition Time (Figure 3) TxCLK IN Transition Time (Figure 5) TxOUT Channel-to-Channel Skew (Note 5) (Figure 6) TxCLK IN to TxCLK OUT Delay @ 25C, VCC = 5.0V (Figure 9) TxCLK IN Period (Figure 7) TxCLK IN High Time (Figure 7) TxCLK IN Low Time (Figure 7) TxIN Setup to TxCLK IN (Figure 7 ) TxIN Hold to TxCLK IN (Figure 7) Transmitter Powerdown Delay (Figure 18) Transmitter Phase Lock Loop Set (Figure 11) Transmitter Output Pulse Position 0 (Figure 13) Transmitter Output Pulse Position 1 Transmitter Output Pulse Position 2 Transmitter Output Pulse Position 3 Transmitter Output Pulse Position 4 Transmitter Output Pulse Position 5 Transmitter Output Pulse Position 6 -0.30 1.70 3.60 5.90 8.30 10.40 12.70 0 1/7 Tclk 2/7 Tclk 3/7 Tclk 4/7 Tclk 5/7 Tclk 6/7 Tclk f = 65 MHz 15 0.35T 0.35T 5 2.5 T 0.5T 0.5T 3.5 1.5 100 10 0.30 2.50 4.50 6.75 9.00 11.10 13.40 50 0.65T 0.65T ns ns ns ns ns ns ms ns ns ns ns ns ns ns 3.5 Min Typ 0.75 0.75 Max 1.5 1.5 8 350 8.5 Units ns ns ns ps ns
Note 5: This limit based on bench characterization.
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol CLHT CHLT RCOP RCOH RCOL RSRC RHRC RCCD RPLLS RSKM RPDD Parameter CMOS/TTL Low-to-High Transition Time (Figure 4) CMOS/TTL High-to-Low Transition Time (Figure 4) RxCLK OUT Period RxCLK OUT High Time RxCLK OUT Low Time RxOUT Setup to RxCLK OUT RxOUT Hold to RxCLK OUT RxCLK IN to RxCLK OUT Delay @ 25C, VCC = 5.0V (Figure 10) Receiver Phase Lock Loop Set (Figure 12) RxIN Skew Margin (Note 6) (Figure 14) Receiver Powerdown (Figure 17) VCC = 5V, TA = 25C 600 1 10 ms ps s f = 65 MHz f = 65 MHz f = 65 MHz f = 65 MHz 15 7.8 3.8 2.5 4.0 6.4 Min Typ 2.5 2.0 T 9 5 4.2 5.2 10.7 Max 4.0 3.5 50 Units ns ns ns ns ns ns ns ns
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter. RSKM cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
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FIGURE 1. "Worst Case" Test Pattern
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AC Timing Diagrams
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FIGURE 2. "16 Grayscale" Test Pattern
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
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FIGURE 3. DS90CF563 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 4. DS90CF564 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 5. DS90CF563 (Transmitter) Input Clock Transition Time
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AC Timing Diagrams
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Note: Measurements at Vdiff = 0V Note: TCSS measured between earliest and latest LVDS edges. Note: TxCLK Differential HighLow Edge
FIGURE 6. DS90CF563 (Transmitter) Channel-to-Channel Skew and Pulse Width
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FIGURE 7. DS90CF563 (Transmitter) Setup/Hold and High/Low Times
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FIGURE 8. DS90CF564 (Receiver) Clock In to Clock Out Delay
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FIGURE 9. DS90CF563 (Transmitter) Clock In to Clock Out Delay
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AC Timing Diagrams
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FIGURE 10. DS90CF564 (Receiver) Clock In to Clock Out Delay
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FIGURE 11. DS90CF563 (Transmitter) Phase Lock Loop Set Time
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FIGURE 12. DS90CF564 (Receiver) Phase Lock Loop Set Time
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AC Timing Diagrams
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FIGURE 13. Transmitter LVDS Output Pulse Position Measurement
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SW -- Setup and Hold Time (Internal Data Sampling Window) TCCS -- Transmitter Output Skew RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) Cable Skew -- typically 10 ps-40 ps per foot
FIGURE 14. Receiver LVDS Input Skew Margin
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FIGURE 15. Seven Bits of LVDS in One Clock Cycle
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AC Timing Diagrams
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FIGURE 16. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF563)
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FIGURE 17. Receiver Powerdown Delay
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FIGURE 18. Transmitter Powerdown Delay
DS90CF563 Pin Descriptions -- FPD Link Transmitter
Pin Name TxIN TxOUT+ TxOUT- FPSHIFT IN TxCLK OUT+ TxCLK OUT- PWR DOWN VCC GND PLL VCC I/O I O O I O O I I I I No. 21 3 3 1 1 1 1 4 5 1 Description TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines -- FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable) Positive LVDS differential data output Negative LVDS differential data output TTL level clock input. The falling edge acts as data strobe Positive LVDS differential clock output Negative LVDS differential clock output TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down Power supply pins for TTL inputs Ground pins for TTL inputs Power supply pin for PLL
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DS90CF563 Pin Descriptions -- FPD Link Transmitter
Pin Name PLL GND LVDS VCC LVDS GND I/O I I I No. 2 1 3 Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs Description
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DS90CF564 Pin Descriptions -- FPD Link Receiver
Pin Name RxIN+ RxIN- RxOUT RxCLK IN+ RxCLK IN- FPSHIFT OUT PWR DOWN VCC GND PLL VCC PLL GND LVDS VCC LVDS GND I/O I I O I I O I I I I I I I No. 3 3 21 1 1 1 1 4 5 1 2 1 3 Positive LVDS differential data inputs Negative LVDS differential data inputs TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines -- FPLINE, FPFRAME, DRDY(also referred to as HSYNC, VSYNC, Data Enable) Positive LVDS differential clock input Negative LVDS differential clock input TTL level clock output. The falling edge acts as data strobe TTL level input. Assertion (low input) maintains the receiver outputs in the previous state Power supply pins for TTL outputs Ground pins for TTL outputs Power supply for PLL Ground pin for PLL Power supply pin for LVDS inputs Ground pins for LVDS inputs Description
Connection Diagrams
DS90CF563 DS90CF564
DS012615-22
DS012615-23
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DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link-- 65 MHz
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC NS Package Number MTD48
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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