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| DS90CF581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link June 1998 DS90CF581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link General Description The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. This transmitter is intended to interface to any of the FPD Link receivers. The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n n n n n n n n n Up to 140 Megabyte/sec Bandwidth Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI Low power CMOS design Power-down mode PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Block Diagrams DS90CF581 DS012486-28 Order Number DS90CF581MTD See NS Package Number MTD56 Application DS012486-2 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1998 National Semiconductor Corporation DS012486 www.national.com Connection Diagram DS90CF581 DS012486-3 www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3 to +6V CMOS/TTL Input Voltage -0.3 to (VCC + 0.3V) LVDS Driver Output Voltage -0.3 to (VCC + 0.3V) LVDS Output Short Circuit Duration continuous Junction Temperature +150C Storage Temperature Range -65C to +150C Lead Temperature (Soldering, 4 sec.) +260C Maximum Package Power Dissipation @ +25C MTD56 (TSSOP) Package: DS90CF581 Derate Package: DS90CF581 1.63W 12.5 mW/C above +25C This device does not meet 2000V ESD rating. (Note 4) Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 4.5 -10 0 Nom 5.0 +25 Max 5.5 +70 2.4 100 Units V C V mVP-P Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol VIH VIL VCL IIN VOD VOD VOS VOS VOH VOL IOS IOZ ICCTW Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current Differential Output Voltage Change in VOD between Complimentary Output States Offset Voltage (Note 5) Change in VOS between Complimentary Output States High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Output TRI-STATE (R) Current Transmitter Supply Current, Worst Case ICCTG Transmitter Supply Current, 16 Grayscale ICCTZ Transmitter Supply Current, Power Down Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). Note 4: ESD Rating: HBM (1.5 k, 100 pF) PLL VCC 1000V All other pins 2000V EIAJ (0, 200 pF) 150V Note 5: VOS previously referred as VCM. Conditions Min 2.0 GND Typ Max VCC 0.8 Units V V V A mV mV V mV V V mA A mA mA mA mA A CMOS/TTL DC SPECIFICATIONS ICL = -18 mA VIN = VCC, GND, 2.5V or 0.4V RL = 100 250 -0.79 -1.5 5.1 290 10 450 35 LVDS DRIVER DC SPECIFICATIONS 1.1 1.25 1.375 35 1.3 0.9 VOUT = 0V, RL = 100 Power Down = 0V, VOUT = 0V or VCC RL = 100, CL = 5 pF, Worst Case Pattern (Figure 1, Figure 3) RL = 100, CL = 5 pF, Grayscale Pattern (Figure 2, Figure 3) Power Down = Low f = 32.5 MHz f = 37.5 MHz f = 32.5 MHz f = 37.5 MHz 1.01 -2.9 1.6 -5 1 34 36 27 28 1 10 51 53 47 48 25 TRANSMITTER SUPPLY CURRENT 3 www.national.com Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TCIT TCCS TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TCIP TCIH TCIL TSTC THTC TCCD TPLLS TPDD Parameter LVDS Low-to-High Transition Time (Figure 3) LVDS High-to-Low Transition Time (Figure 3) TxCLK IN Transition Time (Figure 4) TxOUT Channel-to-Channel Skew (Note 6) (Figure 5) Transmitter Output Pulse Position for Bit 0 (Figure 11) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 Transmitter Output Pulse Position for Bit 0 (Figure 11) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 TxCLK IN Period (Figure 6) TxCLK IN High Time (Figure 6) TxCLK IN Low Time (Figure 6) TxIN Setup to TxCLK IN (Figure 6) TxIN Hold to TxCLK IN (Figure 6) TxCLK IN to TxCLK OUT Delay @ 25C, VCC = 5.0V (Figure 7) Transmitter Phase Lock Loop Set (Figure 8) Transmitter Powerdown Delay (Figure 10) f = 20 MHz f = 40 MHz f = 40 MHz f = 20 MHz -200 6.3 12.8 20 27.2 34.5 42.2 -100 2.9 6.1 9.7 13 17 20.3 25 0.35T 0.35T 14 8 2.5 5 2 9.7 10 100 150 7.2 13.6 20.8 28 35.2 42.6 100 3.3 6.6 10.2 13.5 17.4 20.8 T 0.5T 0.5T Min Typ 0.75 0.75 Max 1.5 1.5 8 350 350 7.5 14.6 21.5 28.5 35.6 42.9 300 3.9 7.1 10.7 14.1 17.8 21.4 50 0.65T 0.65T Units ns ns ns ps ps ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Note 6: This limit based on bench characterization. AC Timing Diagrams DS012486-15 FIGURE 1. "WORST CASE" Test Pattern www.national.com 4 AC Timing Diagrams (Continued) DS012486-16 Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 10: Recommended pin to signal mapping. Customer may choose to define differently. FIGURE 2. "16 GRAYSCALE" Test Pattern (Notes 7, 8, 9, 10) DS012486-8 DS012486-9 FIGURE 3. DS90CF581 (Transmitter) LVDS Output Load and Transition Timing 5 www.national.com AC Timing Diagrams (Continued) DS012486-17 FIGURE 4. DS90CF581 (Transmitter) Input Clock Transition Time DS012486-18 Note 11: Measurements at Vdiff = 0V Note 12: TCCS measured between earliest and latest initial LVDS edges. Note 13: TxCLK OUT Differential HighLow Edge for DS90CF581 TxCLK OUT Differential LowHigh Edge for DS90CR581 FIGURE 5. DS90CF581 (Transmitter) Channel-to-Channel Skew DS012486-12 FIGURE 6. DS90CF581 (Transmitter) Setup/Hold and High/Low Times DS012486-19 FIGURE 7. DS90CF581 (Transmitter) Clock In to Clock Out Delay www.national.com 6 AC Timing Diagrams (Continued) DS012486-14 FIGURE 8. DS90CF581 (Transmitter) Phase Lock Loop Set Time DS012486-23 FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF581) DS012486-24 FIGURE 10. Transmitter Powerdown Delay 7 www.national.com AC Timing Diagrams (Continued) DS012486-26 FIGURE 11. Transmitter LVDS Output Pulse Position Measurement DS90CF581 Pin Description -- FPD Link Transmitter Pin Name TxIN TxOUT+ TxOUT- FPSHIFT IN TxCLK OUT+ TxCLK OUT- PWR DOWN VCC GND PLL VCC PLL GND LVDS VCC LVDS GND I/O I O O I O O I I I I I I I No. 28 4 4 1 1 1 1 4 5 1 2 1 3 Description TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE, FPFRAME, DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE) Positive LVDS differential data output Negative LVDS differential data output TTL level clock input. The falling edge acts as data strobe. Positive LVDS differential clock output Negative LVDS differential clock output TTL level input. Assertion (low input) TRI-STATE the outputs, ensuring low current at power down. Power supply pins for TTL inputs Ground pins for TTL inputs Power supply pin for PLL Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs www.national.com 8 9 DS90CF581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF581MTD NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. |
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