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For:char Printed on:Mon, Feb 6, 1995 09:48:26 From book:DL121CH4 (5) VIEW Document:MC74F323 (5) VIEW Last saved on:Fri, Feb 3, 1995 16:04:13
MC74F323 8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS
The MC74F323 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. Its function is similar to the F299 with the exception of Synchronous Reset. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. Four modes of operation are possible: hold (store), shift left, shift right and parallel load. All modes are activated on the LOW-to-HIGH transition of the clock.
8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS
FASTTM SCHOTTKY TTL
* Common I/O For Reduced Pin Count * Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store * Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy
Cascading * Fully Synchronous Reset * 3-State Outputs for Bus Oriented Applications * Input Clamp Diodes Limit High-Speed Termination Effects
20 1
J SUFFIX CERAMIC CASE 732-03
20 1
N SUFFIX PLASTIC CASE 738-03
CONNECTION DIAGRAM
VCC 20 S1 19 DS7 Q7 18 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11
20 1
DW SUFFIX SOIC CASE 751D-03
ORDERING INFORMATION
1 S0 2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 9 10 SR GND MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 -1.0/- 3.0 20/24 Unit V C mA mA
FAST AND LS TTL DATA 4-150
MC74F323
FUNCTION TABLE
Inputs SR L H H H H S1 X H L H L S0 X H H L L CP X Response Synchronous Reset: Q0-Q7 = LOW Parallel Load: I/On Qn Shift Right: DS0 Q0, Q0 Q1, etc. Shift Left: DS7 Q7, Q7 Q6, etc. Hold
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH clock transition.
FUNCTIONAL DESCRIPTION
The MC74F323 contains eight edge-triggered D-type flips-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified)
Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Q0/Q7 VOH Output HIGH Voltage I/O VOL Output LOW Voltage 74 74 74 74 Q0/Q7 I/O Q0/Q7 IIH Input HIGH Current I/O Q0/Q7 I/O IIL IOZH IOZL IOS ICC Input LOW Current Off-State Output Current, High-Level Voltage Applied Off-State Output Current, Low-Level Voltage Applied Output Short Circuit Current (Note 2) Total Supply Current - 60 S0, S1 Other Inputs 2.5 2.7 2.7 2.4 0.5 0.5 20 70 0.1 1.0 -1.2 - 0.6 70 1.0 - 0.6 -150 95 3.4 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A mA mA A mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = -18 mA VCC = 4.5 V IOH = -1.0 mA VCC = 4.75 V IOH = - 3.0 mA IOL = 20 mA IOL = 24 mA VCC = 4.75 V VCC = 4.5 V VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX VIN = 7.0 V VIN = 5.5 V
VCC = MAX, VIN = 0.5 V VCC = MAX VOUT = 2.7 V VOUT = 5.5 V
VCC = MAX, VOUT = 0.5 V VCC = MAX VOUT = 0 V Outputs Disabled
NOTES: 1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-151
MC74F323
AC ELECTRICAL CHARACTERISTICS
74F TA = +25C VCC = +5.0 V CL = 50 pF Min Max 70 3.5 3.5 3.5 5.0 3.5 4.0 2.0 2.0 9.0 8.5 9.0 11 8.0 10 6.0 5.5 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF Min Max 70 3.5 3.5 3.5 5.0 3.5 4.0 2.0 2.0 10 9.5 10 12 9.0 11 7.0 6.5
Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ
Parameter Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Output Enable Time to HIGH or LOW Level Output Disable Time to HIGH or LOW Level
Unit MHz ns ns ns ns
AC SETUP REQUIREMENTS
74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Set-Up Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Set-Up Time, HIGH or LOW I/On, DS0, DS7 to CP Hold Time, HIGH or LOW I/On, DS0, DS7 to CP Set-Up Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP CP Pulse Width, HIGH or LOW Min 8.5 8.5 0.0 0.0 5.0 5.0 2.0 2.0 10 10 0.0 0.0 7.0 7.0 Typ Max 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF Min 8.5 8.5 0.0 0.0 5.0 5.0 2.0 2.0 10 10 0.0 0.0 7.0 7.0 Max Unit ns ns ns ns ns ns ns
S1
19
S0
1
LOGIC DIAGRAM
VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
18
DS7 DS0 SR CP
11 9 12 8 2 3 6 14 5 15 4 16
Q0 OE1 OE2
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
17
Q7
7
13
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
FAST AND LS TTL DATA 4-152

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