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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Input NOR Gate High-Performance Silicon-Gate CMOS The MC54/74HC02A is identical in pinout to the LS02. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 40 FETs or 10 Equivalent Gates MC54/74HC02A J SUFFIX CERAMIC PACKAGE CASE 632-08 1 14 14 1 N SUFFIX PLASTIC PACKAGE CASE 646-06 14 1 D SUFFIX SOIC PACKAGE CASE 751A-03 LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 2 1 3 5 4 6 8 10 9 11 13 12 PIN 14 = VCC PIN 7 = GND Y4 Y3 Y2 Y=A+B Y1 14 1 DT SUFFIX TSSOP PACKAGE CASE 948G-01 ORDERING INFORMATION MC54HCXXAJ MC74HCXXAN MC74HCXXAD MC74HCXXADT Ceramic Plastic SOIC TSSOP PIN ASSIGNMENT Y1 A1 B1 Y2 A2 B2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC Y4 B4 A4 Y3 B3 A3 FUNCTION TABLE Inputs A L L H H B L H L H Output Y H L L L 10/95 (c) Motorola, Inc. 1995 3-1 REV 7 MC54/74HC02A I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIII I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIII I II II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I III I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 300 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Ceramic DIP * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VIH Parameter Test Conditions VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 v85_C v125C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 Unit V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A V Vin = VIH or VIL |Iout| |Iout| |Iout| v 2.4 mA v 4.0 mA v 5.2 mA 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.7 5.2 MOTOROLA 3-2 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC02A III I I I I I II I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I I I III I I I I I I II I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1 v85_C v125C 0.1 0.1 0.1 0.1 0.1 0.1 0.4 0.4 0.4 0.33 0.33 0.33 Unit V Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A v Vin = VIH or VIL |Iout| |Iout| |Iout| Vin = VCC or GND Vin = VCC or GND |Iout| = 0 A v 2.4 mA v 4.0 mA v 5.2 mA 0.26 0.26 0.26 Iin Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) 0.1 1.0 1.0 10 1.0 40 A A ICC NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol tPLH, tPHL Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 75 30 15 13 75 30 15 13 10 v85_C v125_C 95 40 19 16 95 40 19 16 10 110 55 22 19 110 55 22 19 10 Unit ns Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) ns Cin Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 22 CPD Power Di i i C P Dissipation Capacitance (P G )* i (Per Gate)* pF F * Used to determine the no-load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 3-3 MOTOROLA MC54/74HC02A tf INPUT A OR B 90% 50% 10% tPLH OUTPUT Y tTLH 90% 50% 10% tr VCC GND tPHL DEVICE UNDER TEST TEST POINT OUTPUT CL* tTHL * Includes all probe and jig capacitance Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/4 OF THE DEVICE) A Figure 2. Test Circuit Y B MOTOROLA 3-4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC02A OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y -A14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 -B1 7 C L -TSEATING PLANE K F G D 14 PL 0.25 (0.010) N M M S TA J 14 PL 0.25 (0.010) M T B S DIM A B C D F G J K L M N N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 8 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 B 1 7 A F C N H G D SEATING PLANE L J K M High-Speed CMOS Logic Data DL129 -- Rev 6 3-5 MOTOROLA MC54/74HC02A OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 F SEATING PLANE D 14 PL K M M B S J 0.25 (0.010) T A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E MOTOROLA 3-6 EEE CCC EEE CCC High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC02A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 3-7 *MC54/74HC02A/D* MC54/74HC02A/D MOTOROLA |
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