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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. * Output Drive Capability: 10 LSTTL Loads * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2 to 6 V * Low Input Current: 1 A * High Noise Immunity Characteristic of CMOS Devices * In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 286 FETs or 71.5 Equivalent Gates LOGIC DIAGRAM
A B PARALLEL DATA INPUTS C 11 12 13 9 7 QH QH SERIAL DATA OUTPUTS
16
MC74HC165A
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
16 1 16 1
D SUFFIX SOIC PACKAGE CASE 751B-05 DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Plastic SOIC TSSOP
PIN ASSIGNMENT
SERIAL SHIFT/ PARALLEL LOAD CLOCK E F G H QH 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC CLOCK INHIBIT D C B A SA QH
D 14 E3 F4 G5
SERIAL DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 CLOCK INHIBIT
H6 SA 10
PIN 16 = VCC PIN 8 = GND
GND
15
FUNCTION TABLE
Serial Shift/ Parallel Load L H H H H H H H X = don't care L L X H L H X L Inputs Clock Inhibit Clock X X L L Internal Stages SA X L H L H X X X A-H a...h X X X X X X X QA a L H L H QB b QAn QAn QAn QAn No Change No Change Output QH h QGn QGn QGn QGn Operation O i Asynchronous Parallel Load Serial Shift via Clock Serial Shift via Clock Inhibit Inhibited Clock No Clock
QAn - QGn = Data shifted from the preceding stage
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 3/98
(c) Motorola, Inc. 1998
1
REV 1
MC74HC165A
II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII III I I III I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
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MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
S bl Symbol VIH
P Parameter
T Test C di i Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9
Ui Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
V
Vin = VIH or VIL |Iout| |Iout| |Iout|
v 2.4 mA v 4.0 mA v 5.2 mA
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
V
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC165A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II I III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1
v 85_C v 125_C
0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 0.33 0.40 0.40 0.40
Unit V
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
v
Vin = VIH or VIL |Iout| |Iout| |Iout| Vin = VCC or GND Vin = VCC or GND Iout = 0 A
v 2.4 mA v 4.0 mA v 5.2 mA
0.26 0.26 0.26
Iin
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
0.1 4
1.0 40
1.0 160
A A
ICC
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol S bl fmax
Parameter P
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 --
- 55 to 25_C 6 18 30 35
v 85_C v 125_C
4.8 17 24 28 4 15 20 24
Unit Ui
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8)
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8)
150 52 30 26 175 58 35 30 150 52 30 26 75 27 15 13 10
190 63 38 33 220 70 44 37 190 63 38 33 95 32 19 16 10
225 65 45 38 265 72 53 45 225 65 45 38 110 36 22 19 10
ns
tPLH, tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH (Figures 2 and 8)
ns
tPLH, tPHL
Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 8)
ns
Cin
Maximum Input Capacitance
pF
NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Di i i C P Dissipation Capacitance (P P k i (Per Package)* )* 40
pF F
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
III I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC74HC165A
Symbol S bl
trec
tr, tf
tsu
tsu
tsu
tsu
tw
tw
th
th
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse width, Serial Shift/Parallel Load (Figure 2)
Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1)
Minimum Recovery Time, Clock to Clock Inhibit (Figure 7)
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6)
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5)
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4)
Minimum Setup Time, Clock to Clock Inhibit (Figure 7)
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6)
Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5)
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4)
Parameter P
4 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 70 27 15 13 70 27 15 13 75 30 15 13 75 30 15 13 75 30 15 13 75 30 15 13 75 30 15 13 5 5 5 5 5 5 5 5 5 5 5 5
Guaranteed Limit
High-Speed CMOS Logic Data DL129 -- Rev 6
v 85_C v 125_C
1000 800 500 400 90 32 19 16 90 32 19 16 95 40 19 16 95 40 19 16 95 40 19 16 95 40 19 16 95 40 19 16 5 5 5 5 5 5 5 5 5 5 5 5
1000 800 500 400 100 36 22 19 100 36 22 19 110 55 22 19 110 55 22 19 110 55 22 19 110 55 22 19 110 55 22 19 5 5 5 5 5 5 5 5 5 5 5 5
Unit Ui
ns ns ns ns ns ns ns ns ns ns ns
MC74HC165A
PIN DESCRIPTIONS
INPUTS A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip-flops when the Serial Shift/Parallel Load input is low. SA (Pin 10) Serial Data input. When the Serial Shift/Parallel Load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the Clock. CONTROL INPUTS Serial Shift/Parallel Load (Pin 1) Data-entry control input. When a high level is applied to this pin, data at the Serial Data input (SA) are shifted into the register with the rising edge of the Clock. When a low level is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. Clock, Clock Inhibit (Pins 2, 15) Clock inputs. These two clock inputs function identically. Either may be used as an active-high clock inhibit. However, to avoid double clocking, the inhibit input should go high only while the clock input is high. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. OUTPUTS QH, QH (Pins 9, 7) Complementary Shift Register outputs. These pins are the noninverted and inverted outputs of the eighth stage of the shift register.
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC165A
SWITCHING WAVEFORMS
tr CLOCK OR CLOCK INHIBIT 90% 50% 10% tw 1/fmax tPLH QH OR QH 90% 50% 10% tTLH tTHL tPHL QH OR QH tf VCC GND SERIAL SHIFT/ PARALLEL LOAD tw 50% tPLH 50% 50% GND tPHL VCC
Figure 1. Serial-Shift Mode
Figure 2. Parallel-Load Mode
VALID tr INPUT H tPLH QH OR QH tTLH 90% 50% 10% tTHL 90% 50% 10% tPHL SERIAL SHIFT/ PARALLEL LOAD tf VCC VCC GND INPUTS A-H 50% GND tsu th VCC GND ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE)
Figure 3. Parallel-Load Mode
Figure 4. Parallel-Load Mode
VALID INPUT SA VCC 50% GND tsu CLOCK OR CLOCK INHIBIT th VCC 50% GND
SERIAL SHIFT/ PARALLEL LOAD
VCC 50% GND tsu th VCC 50% GND
CLOCK OR CLOCK INHIBIT
Figure 5. Serial-Shift Mode
Figure 6. Serial-Shift Mode
TEST POINT CLOCK 2 INHIBITED CLOCK INHIBIT 50% GND tsu CLOCK 50% GND * Includes all probe and jig capacitance trec VCC VCC OUTPUT DEVICE UNDER TEST CL*
Figure 7. Serial-Shift, Clock-Inhibit Mode
Figure 8. Test Circuit
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC165A
EXPANDED LOGIC DIAGRAM
A 11 B 12 C 13 F 4 G 5 H 6
SERIAL SHIFT/ 1 PARALLEL LOAD SERIAL DATA 10 INPUT SA D QA D QB D QC D QF D QG D QH
9Q H 7Q H
CC CLOCK 2 CLOCK 15 INHIBIT
CC
CC
CC
CC
CC
TIMING DIAGRAM
CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A B C PARALLEL DATA INPUTS D E F G H QH QH CLOCK INHIBIT MODE PARALLEL LOAD
H L H L H L H H HH LL L H H L L H H L L H H L
SERIAL-SHIFT MODE
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC74HC165A
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
-A -
16 9
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC165A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
M
DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/
High-Speed CMOS Logic Data DL129 -- Rev 6
9
EE CC EE CC
9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.
-W-
Mfax is a trademark of Motorola, Inc.
MC74HC165A/D MOTOROLA

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