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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC74HC175A/D
Quad D Flip-Flop with Common Clock and Reset
High-Performance Silicon-Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity 166 FETs or 41.5 Equivalent Gates
16
MC74HC175A
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Plastic SOIC TSSOP
LOGIC DIAGRAM
CLOCK 9 2 3 7 6 10 11 15 14 1 PIN 16 = VCC PIN 8 = GND Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
PIN ASSIGNMENT
RESET Q0 INVERTING AND NONINVERTING OUTPUTS Q0 D0 D1 Q1 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q3 Q3 D3 D2 Q2 Q2 CLOCK
D0 DATA INPUTS D1
4 5
D2 12 D3 13 RESET
FUNCTION TABLE
Inputs Reset L H H H Clock X D X H L X Outputs Q Q L H H L L H No Change
L
4/99
(c) Motorola, Inc. 1999
1
REV 1
MC74HC175A
IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII III I I III I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
IIIIIIII I I II I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIII I I III I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
S bl Symbol VIH
P Parameter
T Test C di i Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 1.5 2.1 3.15 42 0.5 0.9 1.35 1.80 1.9 4.4 5.9
Ui Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
V
Vin = VIH or VIL |Iout| |Iout| |Iout|
v 2.4 mA v 4.0 mA v 5.2 mA
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
MOTOROLA
2
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC74HC175A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIIIIIII I I II I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1
v 85_C v 125_C
0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 0.33 0.40 0.40 0.40
Unit V
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
v
Vin = VIH or VIL |Iout| |Iout| |Iout| Vin = VCC or GND Vin = VCC or GND Iout = 0 A
v 2.4 mA v 4.0 mA v 5.2 mA
0.26 0.26 0.26
Iin
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
0.1 4
1.0 40
1.0 160
A A
ICC
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I I III I I I I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I
Guaranteed Limit Symbol S bl fmax Parameter P VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 6 10 30 35
v 85_C v 125_C
4.8 8.0 24 28 4 6 20 24
Unit Ui
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4)
150 75 26 22 125 70 22 19 75 27 15 13 10
190 90 32 28 155 85 27 24 95 32 19 16 10
225 110 38 33 190 110 34 30 110 36 22 19 10
ns
tPHL
Maximum Propagation Delay, Reset to Q or Q (Figures 2 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 4)
ns
Cin
Maximum Input Capacitance
pF
NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD P i Power Di i i C Dissipation Capacitance (P Fli Fl )* (Per Flip-Flop)* 35
F pF
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
ECLinPS and ECLinPS Lite DL140 -- Rev 3
3
MOTOROLA
I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC74HC175A
MOTOROLA Symbol S bl trec tr, tf tsu tw tw th Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Hold Time, Clock to Data (Figure 3) Minimum Setup Time, Data to Clock (Figure 3) Parameter P
4 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 100 45 20 17 100 45 20 17 80 45 16 14 80 45 16 14 5 3 3 3
Guaranteed Limit
v 85_C v 125_C
1000 800 500 400
100 65 20 17
100 65 20 17
125 65 25 21
125 65 25 21
5 3 3 3
ECLinPS and ECLinPS Lite DL140 -- Rev 3 1000 800 500 400 120 85 24 20 120 85 24 20 150 85 30 26 150 85 30 26 5 3 3 3 Unit Ui ns ns ns ns ns ns
MC74HC175A
SWITCHING WAVEFORMS
tw RESET tf CLOCK 90% 50% 10% tw 1/fmax 90% 50% 10% tPLH tPHL CLOCK tTLH tTHL tr VCC GND Q 50% tPHL 50% tPLH Q 50% trec VCC 50% GND VCC GND
Q or Q
Figure 1.
Figure 2.
VALID VCC DATA tsu CLOCK GND th VCC 50% GND
Figure 3.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST
CL*
* Includes all probe and jig capacitance
Figure 4.
ECLinPS and ECLinPS Lite DL140 -- Rev 3
5
MOTOROLA
MC74HC175A
EXPANDED LOGIC DIAGRAM
4 2
D0
D C
Q
Q0
CLOCK
9
C
3 R
Q0
D1
5
D C C
Q
7
Q1
6 R
Q1
D2
12
D C C
Q
10
Q2
11 R
Q2
D3
13
D C C
Q
15
Q3
14 R
Q3
RESET
1
MOTOROLA
6
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC74HC175A
OUTLINE DIMENSIONS
N SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
B
1 8
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A -
16 9
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
ECLinPS and ECLinPS Lite DL140 -- Rev 3
7
MOTOROLA
MC74HC175A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
M
DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26668334 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MOTOROLA 8
EE CC EE CC
9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.
-W-
MC74HC175A/D ECLinPS and ECLinPS Lite DL140 -- Rev 3

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