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| MC74HC4316A Product Preview Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 P SUFFIX CASE 648 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week 74HC4316A AWLYWW HC43 16A ALYW HC4316AD AWLYWW HC4316AN AWLYYWW High-Performance Silicon-Gate CMOS The MC74HC4316A utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power-supply range (from VCC to VEE). The HC4316A is similar in function to the metal-gate CMOS MC14016 and MC14066, and to the High-Speed CMOS HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. Logic-level translators are provided so that the On/Off Control and Enable logic-level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active-low) is high, all four analog switches are turned off. * * * * * * * * Logic-Level Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 Volts Digital (Control) Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts, Independent of VEE Improved Linearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates PIN ASSIGNMENT XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC VEE ORDERING INFORMATION Device MC74HC4316AN MC74HC4316AD MC74HC4316ADR2 MC74HC4316ADT Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOEIAJ-14 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel See Note 1. FUNCTION TABLE Inputs On/Off Enable Control L L H X = don't care H L X State of Analog Switch On Off Off MC74HC4316ADTR2 MC74HC4316AF 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 1999 1 March, 2000 - Rev. 1 Publication Order Number: MC74HC4316A/D MC74HC4316A LOGIC DIAGRAM XA A ON/OFF CONTROL 1 15 LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD 12 YD 11 YC 3 YB ANALOG OUTPUTS/INPUTS PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND VEE ANALOG SWITCH 2 YA XB B ON/OFF CONTROL 4 5 XC C ON/OFF CONTROL 10 6 XD D ON/OFF CONTROL ENABLE 13 14 7 IIIIIIIIIIIIIIIIIIII II I IIII II I I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII II I III I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I II II I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC VEE VIS Vin I Parameter Value Unit V V V V Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) - 0.5 to + 7.0 - 0.5 to + 14.0 - 7.0 to + 0.5 VEE - 0.5 to VCC + 0.5 25 750 500 450 Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage DC Input Voltage (Ref. to GND) - 0.5 to VCC + 0.5 DC Current Into or Out of Any Pin Power Dissipation in Still Air mA PD Plastic DIP EIAJ/SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. v v *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C EIAJ/SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 2 MC74HC4316A RECOMMENDED OPERATING CONDITIONS II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIII I I I I IIIIIIIIIIIIIIIIIIIII I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I IIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I Symbol VCC VEE VIS Vin TA Parameter Min 2.0 Max 6.0 Unit V V V V V Positive DC Supply Voltage (Ref. to GND) Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage - 6.0 VEE -- GND VCC VCC 1.2 Digital Input Voltage (Ref. to GND) GND VIO* tr, tf Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) - 55 0 0 0 0 + 125 1000 600 500 400 _C ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted Guaranteed Limit VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 Symbol VIH Parameter Test Conditions v 85_C v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 Unit V Minimum High-Level Voltage, Control or Enable Inputs Ron = Per Spec VIL Maximum Low-Level Voltage, Control or Enable Inputs Ron = Per Spec V Iin Maximum Input Leakage Current, Control or Enable Inputs Vin = VCC or GND VEE = - 6.0 V Vin = VCC or GND VIO = 0 V 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) A VEE = GND VEE = - 6.0 6.0 6.0 2 4 20 40 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4316A DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I II I IIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I III I I I I I I I IIII I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I Guaranteed Limit Symbol Ron Parameter Test Conditions VCC V 2.0* 45 4.5 6.0 2.0 4.5 4.5 6.0 2.0 4.5 4.5 6.0 6.0 VEE V - 55 to 25_C -- 160 90 90 -- 90 70 70 -- 20 15 15 v 85_C v 125_C -- 200 110 110 -- 115 90 90 -- 25 20 20 -- 240 130 130 -- 140 105 105 -- 30 25 25 Unit Maximum "ON" Resistance Vin = VIH VIS = VCC to VEE IS 2.0 mA (Figures 1, 2) v 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 - 6.0 Vin = VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 1, 2) v v Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off-Channel Leakage Current, Any One Channel Maximum On-Channel Leakage Current, Any One Channel Vin = VIH VIS = 1/2 (VCC - VEE) IS 2.0 mA Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) Ioff 0.1 0.5 1.0 A Ion Vin = VIH VIS = VCC or VEE (Figure 4) 6.0 - 6.0 0.1 0.5 1.0 A *At supply voltage (VCC - VEE) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I Guaranteed Limit Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH C Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 40 6 5 v 85_C v 125_C 50 8 7 60 9 8 160 50 40 175 50 40 10 200 60 50 250 60 50 10 Unit ns Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Capacitance 130 40 30 140 40 30 10 ns ns ON/OFF Control and Enable Inputs pF Control Input = GND Analog I/O Feedthrough -- -- 35 1.0 35 1.0 35 1.0 NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC4316A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) IIII I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIII I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I III I I I III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Symbol BW Parameter Test Conditions VCC V 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 VEE V Limit* 25_C 150 160 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 MHz -- fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF -- Feedthrough Noise, Control to Switch (Figure 7) Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF RL = 10 k, CL = 10 pF v mVPP -- Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF - 70 - 70 - 70 - 80 - 80 - 80 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave % 2.25 4.50 6.00 - 2.25 - 4.50 - 6.00 0.10 0.06 0.04 *Limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 MC74HC4316A TBD TBD Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V Figure 1b. Typical On Resistance, VCC - VEE = 4.5 V TBD TBD Figure 1c. Typical On Resistance, VCC - VEE = 6.0 V Figure 1d. Typical On Resistance, VCC - VEE = 9.0 V PLOTTER PROGRAMMABLE POWER SUPPLY MINI COMPUTER DC ANALYZER TBD - + DEVICE UNDER TEST ANALOG IN VCC COMMON OUT GND VEE Figure 1e. Typical On Resistance, VCC - VEE = 12.0 V http://onsemi.com 6 Figure 2. On Resistance Test Set-Up MC74HC4316A VCC VEE VCC A OFF 16 VCC VCC A O/I VEE ON 16 VCC N/C VIL 7 8 9 VEE SELECTED CONTROL INPUT VEE 7 8 9 SELECTED CONTROL INPUT VIH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum On Channel Leakage Current, Test Set-Up VIS VCC 16 fin 0.1 F ON RL VCC SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. CL* VCC RL VCC 16 TO dB METER fin 0.1 F RL OFF RL CL* TO dB METER 7 8 9 VEE 7 8 9 SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 5. Maximum On-Channel Bandwidth Test Set-Up Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up VCC 16 TEST POINT RL SELECTED CONTROL INPUT CL* ANALOG IN tPLH 50% 50% GND tPHL ON/OFF RL 7 8 9 VEE CONTROL *Includes all probe and jig capacitance. VCC ANALOG OUT Figure 7. Feedthrough Noise, Control to Analog Out, Test Set-Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74HC4316A VCC 16 ANALOG I/O ON 50 pF* ANALOG O/I TEST POINT ENABLE 50% CONTROL tPZL 7 8 9 SELECTED CONTROL INPUT VCC ANALOG OUT 50% tPZH 50% *Includes all probe and jig capacitance. tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE tr tf VCC Figure 9. Propagation Delay Test Set-Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 CONTROL OR ENABLE 8 9 VEE ON/OFF 50 pF* POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 1 k TEST POINT fin 0.1 F RL VIS VCC 16 ON RL CL* ANALOG I/O OFF 7 8 9 RL VCC SELECTED CONTROL INPUT CL* TEST POINT *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set-Up Figure 12. Crosstalk Between Any Two Switches, Test Set-Up (Adjacent Channels Used) VCC A 16 N/C ON/OFF N/C 10 F fin ON RL 7 8 9 VEE CONTROL SELECTED CONTROL INPUT VEE CL* VIS VCC 16 VOS TO DISTORTION METER 7 8 9 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set-Up Figure 14. Total Harmonic Distortion, Test Set-Up http://onsemi.com 8 MC74HC4316A APPLICATIONS INFORMATION 0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 - 100 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 15. Plot, Harmonic Distortion The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (ON Semiconductor high current surge protectors). MOsorbs are fast turn-on devices ideally suited for precise dc protection with no inherent wear out mechanism. VCC = 6 V +6V -6 V +6V SELECTED CONTROL INPUT VEE 8 -6 V 16 ANALOG I/O ON ANALOG O/I +6V -6 V Dx VCC 16 ON Dx VEE VCC SELECTED CONTROL INPUT VEE VCC Dx Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) ENABLE CONTROL INPUTS (VCC OR GND) Figure 16. Figure 17. Transient Suppressor Application http://onsemi.com 9 MC74HC4316A VCC = 5 V +5 V ANALOG SIGNALS R* R* R* R* R* 16 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER LSTTL/ NMOS 5 6 14 15 16 ANALOG SIGNALS HC4316A TTL 7 5 6 14 15 R* = 2 TO 10 k ENABLE AND CONTROL 9 INPUTS 8 VEE = 0 TO - 6 V HC4016A VEE = 0 TO - 6 V CONTROL INPUTS 9 7 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VCC = 12 V 12 V POWER SUPPLY R1 GND = 6 V R2 VEE = 0 V R1 = R2 VCC ANALOG INPUT SIGNAL C R3 R4 VEE R1 = R2 R3 = R4 ANALOG OUTPUT SIGNAL 12 V 0 12 VPP 1 OF 4 SWITCHES Figure 19. Switching a 0-to-12 V Signal Using a Single Power Supply (GND 0 V) CHANNEL 4 1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT CHANNEL 3 CHANNEL 2 CHANNEL 1 Figure 20. 4-Input Multiplexer Figure 21. Sample/Hold Amplifier http://onsemi.com 10 MC74HC4316A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 6.85 0.250 0.270 3.69 4.44 0.145 0.175 0.39 0.53 0.015 0.021 1.02 1.77 0.040 0.070 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.38 0.008 0.015 2.80 3.30 0.110 0.130 7.50 7.74 0.295 0.305 0 10 0 10 0.51 1.01 0.020 0.040 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S http://onsemi.com 11 MC74HC4316A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O 16 9 LE Q1 E HE M_ L DETAIL P 1 8 Z D e A VIEW P b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 12 EEE CCC EEE CCC M c -W- DIM A B C D F G H J J1 K K1 L M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031 MC74HC4316A Notes http://onsemi.com 13 MC74HC4316A Notes http://onsemi.com 14 MC74HC4316A Notes http://onsemi.com 15 MC74HC4316A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 16 MC74HC4316A/D |
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