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 MC74VHC1GT125
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Noninverting Buffer / CMOS Logic Level Shifter
with LSTTL-Compatible Inputs
The MC74VHC1GT125 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT125 requires the 3-state control input (OE) to be set High to place the output into the high impedance state. The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply. The MC74VHC1GT125 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHC1GT125 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * High Speed: tPD = 3.5ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 2A (Max) at TA = 25C * TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V * CMOS-Compatible Outputs: VOH > 0.8VCC; VOL < 0.1VCC @Load * Power Down Protection Provided on Inputs and Outputs * Balanced Propagation Delays * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 1500V; MM > 200V
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SC-88A / SOT-353 DF SUFFIX CASE 419A
MARKING DIAGRAM
W1d
Pin 1 d = Date Code
PIN ASSIGNMENT
1 2 3 4 5 OE IN A GND OUT Y VCC
ORDERING INFORMATION
OE 1 IN A 2 GND 3 4 OUT Y 5 VCC
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
FUNCTION TABLE Figure 1. 5-Lead SOT-353 Pinout (Top View)
A Input OE Input L L H Y Output L H Z
LOGIC SYMBOL
OE IN A OUT Y
L H X
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 1999
1
February, 2000 - Rev. 0
Publication Order Number: MC74VHC1GT125/D
MC74VHC1GT125
II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I I I I I I I IIII I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
II I IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage DC Input Voltage Value Unit - 0.5 to + 7.0III V - 0.5 to + 7.0III V V Vout IIK DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW Tstg - 65 to + 150
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
v
v
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter
Min 4.5 0 0
Max 5.5 5.5
Unit V V V
DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage
VCC + 85 20
Operating Temperature, All Package Types Input Rise and Fall Time
- 40 0
_C
tr, tf
VCC =5.0V 0.5V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH
Parameter
Test Conditions
VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5
TA = 25C Typ
TA 85C
TA 125C
Min 1.2 2.0 2.0
Max
Min 1.2 2.0 2.0
Max
Min 1.2 2.0 2.0
Max
Unit V
Minimum High-Level Input Voltage
VIL
Maximum Low-Level Input Voltage Minimum High-Level Output Voltage VIN = VIH or VIL
0.53 0.8 0.8
0.53 0.8 0.8
0.53 0.8 0.8
V
VOH
VOL
Maximum Low-Level Output Voltage VIN = VIH or VIL
VIN = VIH or VIL IOH = - 50A VIN = VIH or VIL IOH = - 4mA IOH = - 8mA VIN = VIH or VIL IOL = 50A VIN = VIH or VIL IOL = 4mA IOL = 8mA VIN = 5.5 V or GND
2.9 4.4
3.0 4.5
2.9 4.4
2.9 4.4
V
2.58 3.94
2.48 3.80
2.34 3.66
0.0 0.0
0.1 0.1
0.1 0.1
0.1 0.1
V
0.36 0.36
0.44 0.44
0.52 0.52
IIN
Maximum Input Leakage Current
0 to 5.5 5.5 5.5 0.0
0.1 2.0
1.0 20
1.0 40
A A
ICC
Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current
VIN = VCC or GND Input: VIN = 3.4V VOUT = 5.5V
ICCT IOPD
1.35 0.5
1.50 5.0
1.65 10
mA A
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MC74VHC1GT125
II I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I I I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III IIIII I IIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Typ 5.6 8.1 3.8 5.3 5.4 7.9 3.6 5.1 6.5 8.0 4.8 7.0 4 6 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 TA 125C Symbol tPLH, tPHL Parameter Test Conditions Min Max 8.0 11.5 5.5 7.5 Max Min Max Unit ns Maximum Propagation Delay, A to Y (Figures 2 and 4) VCC = 3.3 0.3V CL = 15pF CL = 50pF VCC = 5.0 0.5V CL = 15pF CL = 50pF 9.5 13.0 6.5 8.5 12.0 16.0 8.5 10.5 11.5 15.0 7.5 9.5 tPZL, tPZH Maximum Output Enable TIme,OE to Y (Figures 3 and 5) VCC = 3.3 0.3V CL = 15pF RL = 1k CL = 50pF VCC = 5.0 0.5V CL = 15pF RL = 1k CL = 50pF VCC = 3.3 0.3V CL = 15pF RL = 1k CL = 50pF VCC = 5.0 0.5V CL = 15pF RL = 1k CL = 50pF 8.0 11.5 5.1 7.1 9.5 13.0 6.0 8.0 ns tPLZ, tPHZ Maximum Output Disable Time,OE to Y (Figures 3 and 5) 9.7 13.2 6.8 8.8 10 11.5 15.0 8.0 10.0 10 14.5 18.0 10.0 12.0 10 ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V CPD Power Dissipation Capacitance (Note 1.) pF 14 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
SWITCHING WAVEFORMS
3.0V OE 3.0V A tPLH 1.5V 1.5V GND tPHL VOH VOL Y Y Y tPZL tPLZ 1.5V tPZH tPHZ 1.5V 1.5V GND HIGH IMPEDANC VOL -0.3V VOH +0.3V HIGH IMPEDANC
Figure 2.
Figure 3.
TEST POINT OUTPUT DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
DEVICE UNDER TEST
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4. Test Circuit
Figure 5. Test Circuit
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3
MC74VHC1GT125
DEVICE ORDERING INFORMATION
Device Nomenclature Circuit Indicator MC Temp Range Identifier 74 Tech- nology VHC1G Input Type T Device Function 125 Package Suffix DF Tape & Reel Suffix T1 Package Type SC-88A/ SOT-353 Tape and Reel Size 7-Inch/3000 Unit
Device Order Number MC74VHC1GT125DFT1
PACKAGE DIMENSIONS
SC-88A / SOT-353 DF SUFFIX 5-LEAD PACKAGE CASE 419A-01 ISSUE B
A G V
DIM A B C D G H J K N S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 0.012 0.016 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 0.30 0.40
5
4
S
1 2 3
-B-
D 5 PL
0.2 (0.008)
M
B
M
0.5 mm (min) N J C
H
K 0.4 mm (min)
1.9 mm
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4
0.65 mm 0.65 mm
EE EE EE EE
EEE EEE EEE EEE EEE EEE EEE
MC74VHC1GT125
10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E A0 B1 K0 SEE NOTE 2 SEE NOTE 2
K t TOP COVER TAPE D P2
P0
F
W
+
B0 P
+
+
D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER
FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0
EMBOSSMENT USER DIRECTION OF FEED
CENTER LINES OF CAVITY
*TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE BENDING RADIUS
EMBOSSED CARRIER
EMBOSSMENT
10
MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE
100 mm (3.937")
1 mm MAX
TAPE 1 mm (0.039") MAX 250 mm (9.843")
TYPICAL COMPONENT CENTER LINE
CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape Size 8 mm B1 Max 4.35 mm (0.171") D 1.5 +0.1/ -0.0 mm (0.059 +0.004/ -0.0") D1 1.0 mm Min (0.039") E 1.75 0.1 mm (0.069 0.004") F 3.5 0.5 mm (1.38 0.002") K 2.4 mm (0.094") P 4.0 0.10 mm (0.157 0.004") P0 4.0 0.1 mm (0.156 0.004") P2 2.0 0.1 mm (0.079 0.002") R 25 mm (0.98") T 0.3 0.05 mm (0.01 +0.0038/ -0.0002") W 8.0 0.3 mm (0.315 0.012")
1. Metric Dimensions Govern-English are in parentheses for reference only. 2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity
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5
MC74VHC1GT125
t MAX
1.5 mm MIN (0.06") A 20.2 mm MIN (0.795")
13.0 mm 0.2 mm (0.512" 0.008")
50 mm MIN (1.969")
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size 8 mm A Max 330 mm (13") G 8.400 mm, +1.5 mm, -0.0 (0.33", +0.059", -0.00) t Max 14.4 mm (0.56")
DIRECTION OF FEED
BARCODE LABEL POCKET HOLE
Figure 8. Reel Winding Direction
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6
MC74VHC1GT125
CAVITY TAPE
TOP TAPE
TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN
COMPONENTS
TAPE LEADER NO COMPONENTS 400 mm MIN
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
"T1" PIN ONE TOWARDS SPROCKET HOLE
SC-88A/SOT-353 (5 Pin) DEVICE
User Direction of Feed
Figure 10. Reel Configuration
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7
MC74VHC1GT125
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
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8
MC74VHC1GT125/D


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