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| MC74VHC1GT126 Product Preview Noninverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs The MC74VHC1GT126 is a single gate noninverting 3-state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT126 requires the 3-state control input (OE) to be set Low to place the output into the high impedance state. The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply. The MC74VHC1GT126 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHC1GT126 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * High Speed: tPD = 3.5ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 2A (Max) at TA = 25C * TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V * CMOS-Compatible Outputs: VOH > 0.8VCC; VOL < 0.1VCC @Load * Power Down Protection Provided on Inputs and Outputs * Balanced Propagation Delays * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 1500V; MM > 200V http://onsemi.com SC-88A / SOT-353 DF SUFFIX CASE 419A MARKING DIAGRAM W3d Pin 1 d = Date Code PIN ASSIGNMENT 1 2 3 4 5 OE IN A GND OUT Y VCC ORDERING INFORMATION OE 1 IN A 2 GND 3 4 OUT Y 5 VCC See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. FUNCTION TABLE Figure 1. 5-Lead SOT-353 Pinout (Top View) LOGIC SYMBOL OE IN A OUT Y A Input L H X OE Input H H L Y Output L H Z This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 1999 1 February, 2000 - Rev. 0 Publication Order Number: MC74VHC1GT126/D II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I I I I I I I IIII I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C II I IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* SymbolIIIIIIIIIIIIII Parameter VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage SOIC Packages TSSOP Package DC ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS Symbol Symbol ICCT IOPD VOH VOL ICC VIH VCC Vout VIL IIN tr, tf Vin TA Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Input Rise and Fall Time Operating Temperature, All Package Types DC Output Voltage DC Input Voltage DC Supply Voltage Parameter Parameter VIN = VIH or VIL IOL = 4mA IOL = 8mA VIN = 5.5 V or GND VIN = VIH or VIL IOH = - 50A VIN = VIH or VIL IOH = - 4mA IOH = - 8mA VIN = VIH or VIL IOL = 50A VOUT = 5.5V Input: VIN = 3.4V VIN = VCC or GND Test Conditions VCC =5.0V 0.5V MC74VHC1GT126 http://onsemi.com 0 to 5.5 VCC (V) 0.0 5.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 5.5 3.0 4.5 5.5 - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0III V - 0.5 to + 7.0III V - 40 Min 4.5 Value 0 0 0 - 20 50 25 20 500 450 2.58 3.94 Min 2.9 4.4 1.2 2.0 2.0 TA = 25C VCC + 85 Max 5.5 5.5 20 Typ 0.0 0.0 3.0 4.5 ns/V Unit Unit mW mA mA mA mA 2 _C _C V V V V 0.1 1.35 0.36 0.36 0.53 0.8 0.8 Max 2.0 0.1 0.1 0.5 2.48 3.80 Min 2.9 4.4 1.2 2.0 2.0 TA 85C 1.0 1.50 0.44 0.44 0.53 0.8 0.8 Max 0.1 0.1 20 5.0 2.34 3.66 Min TA 125C 2.9 4.4 1.2 2.0 2.0 1.0 1.65 0.52 0.52 0.53 0.8 0.8 Max 0.1 0.1 40 10 Unit mA A A V V V V A MC74VHC1GT126 II I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I I I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III IIIII I IIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C Typ 5.6 8.1 3.8 5.3 5.4 7.9 3.6 5.1 6.5 8.0 4.8 7.0 4 6 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 TA 125C Symbol tPLH, tPHL Parameter Test Conditions Min Max 8.0 11.5 5.5 7.5 Max Min Max Unit ns Maximum Propagation Delay, A to Y (Figure 2 and 4) VCC = 3.3 0.3V CL = 15pF CL = 50pF VCC = 5.0 0.5V CL = 15pF CL = 50pF 9.5 13.0 6.5 8.5 12.0 16.0 8.5 10.5 11.5 15.0 7.5 9.5 tPZL, tPZH Maximum Output Enable TIme,OE to Y (Figure 3 and 5) VCC = 3.3 0.3V CL = 15pF RL = 1k CL = 50pF VCC = 5.0 0.5V CL = 15pF RL = 1k CL = 50pF VCC = 3.3 0.3V CL = 15pF RL = 1k CL = 50pF VCC = 5.0 0.5V CL = 15pF RL = 1k CL = 50pF 8.0 11.5 5.1 7.1 9.5 13.0 6.0 8.0 ns tPLZ, tPHZ Maximum Output Disable Time,OE to Y (Figure 3 and 5) 9.7 13.2 6.8 8.8 10 11.5 15.0 8.0 10.0 10 14.5 18.0 10.0 12.0 10 ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V CPD Power Dissipation Capacitance (Note 1.) pF 15 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. SWITCHING WAVEFORMS 3.0V 3.0V A tPLH 1.5V 1.5V GND tPHL VOH VOL Y Y Y OE 1.5V GND tPZL tPLZ 1.5V tPZH tPHZ 1.5V HIGH IMPEDANC VOL -0.3V VOH +0.3V HIGH IMPEDANC Figure 2. Figure 3. TEST POINT OUTPUT DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* DEVICE UNDER TEST CL * *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 4. Test Circuit Figure 5. Test Circuit http://onsemi.com 3 MC74VHC1GT126 DEVICE ORDERING INFORMATION Device Nomenclature Circuit Indicator MC Temp Range Identifier 74 Tech- nology VHC1G Input Type T Device Function 126 Package Suffix DF Tape & Reel Suffix T1 Package Type SC-88A/ SOT-353 Tape and Reel Size 7-Inch/3000 Unit Device Order Number MC74VHC1GT126DFT1 PACKAGE DIMENSIONS SC-88A / SOT-353 DF SUFFIX 5-LEAD PACKAGE CASE 419A-01 ISSUE B A G V DIM A B C D G H J K N S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 0.012 0.016 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 0.30 0.40 5 4 S 1 2 3 -B- D 5 PL 0.2 (0.008) M B M 0.5 mm (min) N J C H K 0.4 mm (min) 1.9 mm http://onsemi.com 4 0.65 mm 0.65 mm EE EE EE EE EEE EEE EEE EEE EEE EEE EEE MC74VHC1GT126 10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E A0 B1 K0 SEE NOTE 2 SEE NOTE 2 K t TOP COVER TAPE D P2 P0 F W + B0 P + + D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 EMBOSSMENT USER DIRECTION OF FEED CENTER LINES OF CAVITY *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE BENDING RADIUS EMBOSSED CARRIER EMBOSSMENT 10 MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE 100 mm (3.937") 1 mm MAX TAPE 1 mm (0.039") MAX 250 mm (9.843") TYPICAL COMPONENT CENTER LINE CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm Figure 6. Carrier Tape Specifications EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2) Tape Size 8 mm B1 Max 4.35 mm (0.171") D 1.5 +0.1/ -0.0 mm (0.059 +0.004/ -0.0") D1 1.0 mm Min (0.039") E 1.75 0.1 mm (0.069 0.004") F 3.5 0.5 mm (1.38 0.002") K 2.4 mm (0.094") P 4.0 0.10 mm (0.157 0.004") P0 4.0 0.1 mm (0.156 0.004") P2 2.0 0.1 mm (0.079 0.002") R 25 mm (0.98") T 0.3 0.05 mm (0.01 +0.0038/ -0.0002") W 8.0 0.3 mm (0.315 0.012") 1. Metric Dimensions Govern-English are in parentheses for reference only. 2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity http://onsemi.com 5 MC74VHC1GT126 t MAX 1.5 mm MIN (0.06") A 20.2 mm MIN (0.795") 13.0 mm 0.2 mm (0.512" 0.008") 50 mm MIN (1.969") FULL RADIUS G Figure 7. Reel Dimensions REEL DIMENSIONS Tape Size 8 mm A Max 330 mm (13") G 8.400 mm, +1.5 mm, -0.0 (0.33", +0.059", -0.00) t Max 14.4 mm (0.56") DIRECTION OF FEED BARCODE LABEL POCKET HOLE Figure 8. Reel Winding Direction http://onsemi.com 6 MC74VHC1GT126 CAVITY TAPE TOP TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN COMPONENTS TAPE LEADER NO COMPONENTS 400 mm MIN DIRECTION OF FEED Figure 9. Tape Ends for Finished Goods "T1" PIN ONE TOWARDS SPROCKET HOLE SC-88A/SOT-353 (5 Pin) DEVICE User Direction of Feed Figure 10. Reel Configuration http://onsemi.com 7 MC74VHC1GT126 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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