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| SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 5(9) 6(8) Q 1 CLEAR (CD) TO OTHER FLIP-FLOP 4(10) SET (SD) K 2(12) 14 1 N SUFFIX PLASTIC CASE 646-06 J 3(11) 13 CLOCK (CP) 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT -- TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load "0" (Reset) Load "1" (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q 3 13 2 1 VCC = PIN 14 GND = PIN 7 OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 J CP K CD Q SD Q 5 11 J CP 6 12 K C Q D 8 10 SD Q 9 * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don't Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition. FAST AND LS TTL DATA 5-1 SN54/74LS114A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage O Vl 54 74 54, 74 VOL Output LOW Voltage 74 J, K Set Clear Clock IIH Input HIGH Current J, K Set Clear Clock J, K Set Clear, Clock - 20 0.35 0.5 20 60 120 160 0.1 0.3 0.6 0.8 - 0.4 - 0.8 - 1.6 - 100 6.0 V 2.5 25 2.7 54 74 - 0.65 3.5 35 3.5 0.25 0.4 Min 2.0 0.7 0.8 - 1.5 Typ Max Unit Ui V V V V V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH MIN, MAX, or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table A VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V IIL IOS ICC Input LOW Current mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Output Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL Parameter P Maximum Clock Frequency Propagation Delay, Clock, pg y, , Clear, Set to Output Min 30 Typ 45 15 15 20 20 Max Unit Ui MHz ns ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tW tW ts th Parameter P Clock Pulse Width High Clear, Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit Ui ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions FAST AND LS TTL DATA 5-2 |
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