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| SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R 14 Q 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q 5 R 6 S1 7 Q 8 GND 16 1 J SUFFIX CERAMIC CASE 620-09 TRUTH TABLE INPUT S1 L L X H H S2 L X L H H R L H H L H OUTPUT (Q) h H H L No Change 16 1 N SUFFIX PLASTIC CASE 648-08 L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care h = The output is HIGH as long as h = S1 or S2 is LOW. If all inputs go h = HIGH simultaneously, the output h = state is indeterminate; otherwise, h = it follows the Truth Table 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-1 SN54/74LS279 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 7.0 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol tPLH tPHL tPHL Parameter Propagation Delay, S to Output Propagation Delay, R to Output Min Typ Max 22 *21* 27 Unit ns ns Test Conditions VCC = 5.0 V CL = 15 pF F * Add 0.6 ns to spec limit for each 1.0 ns input rise time less than 15 ns. FAST AND LS TTL DATA 5-2 |
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