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OPA 689
OPA689
OPA
689
For most current data sheet and other product information, visit www.burr-brown.com
Wideband, High Gain VOLTAGE LIMITING AMPLIFIER
FEATURES
q HIGH LINEARITY NEAR LIMITING q FAST RECOVERY FROM OVERDRIVE: 2.4ns q LIMITING VOLTAGE ACCURACY: 15mV q -3dB BANDWIDTH (G = +6): 280MHz q STABLE FOR G +4 q SLEW RATE: 1600V/s q 5V AND +5V SUPPLY OPERATION q LOW GAIN VERSION: OPA688
APPLICATIONS
q TRANSIMPEDANCE WITH FAST OVERDRIVE RECOVERY q FAST LIMITING ADC INPUT DRIVER q LOW PROP DELAY COMPARATOR q NON-LINEAR ANALOG SIGNAL PROCESSING q DIFFERENCE AMPLIFIER q IF LIMITING AMPLIFIER q AM SIGNAL GENERATION
DESCRIPTION
The OPA689 is a wideband, voltage feedback op amp that offers bipolar output voltage limiting, and is stable for gains +4. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to 15mV. The op amp operates linearly to within 30mV of the limits. The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mV of the desired linear output range. A fast 2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. Implementing the
LIMITED OUTPUT RESPONSE 2.5 2.0 2.10 G = +6 VH = 2.0V VL = -2.0V 2.05
limiting function at the output, as opposed to the input, gives the specified limiting accuracy for any gain, and allows the OPA689 to be used in all standard op amp applications. Non-linear analog signal processing circuits will benefit from the OPA689's sharp transition from linear operation to output limiting. The quick recovery time supports high speed applications. The OPA689 is available in an industry-standard pinout in PDIP-8 and SO-8 packages. For lower gain applications requiring output limiting with fast recovery, consider the OPA688.
DETAIL OF LIMITED OUTPUT VOLTAGE
Input and Output Voltage (V)
Input and Output Voltage (V)
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (200ns/div) VIN
2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 Time (50ns/div) VO
VO
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
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(c)
1997 Burr-Brown Corporation
PDS-1409D 1
Printed in U.S.A. January, 2000
OPA689
SBOS076
SPECIFICATIONS -- VS = 5V
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. OPA689U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
PARAMETER AC PERFORMANCE (see Fig. 1) Small Signal Bandwidth
CONDITIONS
+25C
+25C
UNITS
Gain Bandwidth Product (G +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Differential Gain Differential Phase Input Noise Density Voltage Noise Current Noise DC PERFORMANCE (VCM = 0V) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separation (VH - VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Offset Voltage Op Amp Input Bias Current Shift(3)
VO < 0.5Vp-p G = +6 G = +12 G = -6 VO < 0.5Vp-p VO < 0.5Vp-p, G = +4 VO < 0.5Vp-p VO = 2Vp-p 2V Step 0.5V Step 2V Step f = 5MHz, VO = 2Vp-p NTSC, PAL, RL = 500 NTSC, PAL, RL = 500 f 1MHz f 1MHz VO = 0.5V
280 90 220 720 8 110 290 1600 1.2 7 61 0.02 0.01 4.6 2.0 56 1 -- +8 -- 0.3 -- 60 3.3 0.4 || 1 1 || 1
220 -- -- 490 -- -- 185 1300 1.8 -- 57 -- -- 5.3 2.5 50 --
210 -- -- 460 -- -- 175 1250 1.9 -- 53 -- -- 6.0 2.9 48 6 14 13 -60 3 10 52 3.2 -- -- 3.9 85 -65 -- -- 6 19 12.8 57 3.0 200 4.3 68 34 40 -- -- 40 --
200 -- -- 430 -- -- 170 950 2.4 -- 48 -- -- 6.1 3.6 47 7 14 20 -90 4 10 50 3.1 -- -- 3.8 80 -60 -- -- 6 20 11 55 2.9 200 4.3 70 31 45 -- -- 40 --
MHz MHz MHz MHz dB MHz MHz V/s ns ns dB % nV/Hz pA/Hz dB mV V/C A nA/C A nA/C dB V M || pF M || pF V mA mA V V mA mA dB V mV V A A nA/C M || pF dB mV A
Min Typ Typ Min Typ Typ Min Min Max Typ Min Typ Typ Max Max Min Max Max Max Max Max Max Min Min Typ Typ Min Min Min Typ Typ Max Max Min Min Min Min Max Max Min Max Typ Typ Max Typ
B C C B C C B B B C B C C B B A A B A B A B A A C C A A A C C A A A A A B B A A B C C A C
5
--
12 2
-- 53 3.2 -- --
Input Referred, VCM = 0.5V
VH = -VL = 4.3V RL 500
G = +4, f < 100kHz
4.1 105 -85 0.8 5 -- 15.8 15.8
3.9
90 -70 -- --
6
17 14 58
+VS = 4.5V to 5.5V 65 Limiter Pins Open 3.3 200 -- 54 54 -- 2 || 1 -60 15 3
3.0
200 4.3 65 35 -- -- --
VO = 0
f = 5MHz VIN = 0.7V (VO - VH) or (VO - VL)
35
--
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OPA689
2
SPECIFICATIONS -- VS = 5V
(cont.)
OPA689U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
PARAMETER OUTPUT VOLTAGE LIMITERS (CONT) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8
CONDITIONS
+25C
+25C
UNITS
VIN = 0.7V, VO < 0.02Vp-p VIN = 0 to 0.7V Step VIN = 0.7V to 0 Step f = 5MHz, VO = 2Vp-p Specification: P, U
450 100 250 2.4 30 -40 to +85 100 125
-- -- -- 2.8 -- -- -- --
-- -- -- 3.0 -- -- -- --
-- -- -- 3.2 -- -- -- --
MHz V/s mV ns mV C C/W C/W
Typ Typ Typ Max Typ Typ Typ Typ
C C C B C C C C
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25C guaranteed specifications. Junction Temperature = Ambient Temperature + 23C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 7. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: V IN = +0.7V, G = +6, VL = -2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 1MHz, VO = 2Vpp) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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3
OPA689
SPECIFICATIONS -- VS = +5V
G = +6, RF = 750, RL = 500 tied to VCM = 2.5V, VL = VCM -1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted. OPA689U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
PARAMETER AC PERFORMANCE (see Fig. 2) Small Signal Bandwidth
CONDITIONS VO < 0.5Vp-p G = +6 G = +12 G = -6 VO < 0.5Vp-p VO < 0.5Vp-p, G = +4 VO < 0.5Vp-p VO = 2Vp-p 2V Step 0.5V Step 2V Step f = 5MHz, VO = 2Vp-p f 1MHz f 1MHz VO = 0.5V
+25C
+25C
UNITS
Gain Bandwidth Product (G +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Input Noise Voltage Noise Density Current Noise Density DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separation (VH - VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Isolation(6) DC Performance in Limit Mode Limiter Voltage Accuracy Op Amp Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8)
210 70 180 440 4 35 175 1600 1.9 7 59 4.6 2.0 56 1 -- +8 -- 0.3 -- 58 VCM 0.8 0.4 || 1 1 || 1
180 -- -- 330 -- -- 150 1300 2.1 -- 55 5.3 2.5 50 --
160 -- -- 310 -- -- 140 1250 2.2 -- 51 6.0 2.9 48 6 14 13 -60 3 10 50 VCM 0.7 -- -- VCM 1.4 55 -45 -- -- 12 15 10 -- VCM 0.6 200 VCM 1.8 75 0 30 -- -- 40 -- -- -- -- -- --
150 -- -- 300 -- -- 125 950 2.6 -- 46 6.1 3.6 47 8 14 20 -90 4 10 48 VCM 0.6 -- -- VCM 1.3 50 -40 -- -- 12 16 9 -- VCM 0.6 200 VCM 1.8 85 0 50 -- -- 40 -- -- -- -- -- --
MHz MHz MHz MHz dB MHz MHz V/s ns ns dB nV/Hz pA/Hz dB mV V/C A nA/C A nA/C dB V M || pF M || pF V mA mA V V mA mA dB V mV V A A nA/C M || pF dB mV A MHz V/s mV ns mV
Min Typ Typ Min Typ Typ Min Min Max Typ Min Max Max Min Max Max Max Max Max Max Min Min Typ Typ Min Min Min Typ Typ Max Max Min Typ Min Min Max Max Min Max Typ Typ Max Typ Typ Typ Typ Typ Typ
B C C B B C B B B C B B B A A B A B A B A A C C A A A C C A A A C A B B A A B C C A C C C C C C
5
--
12 2
-- 51 VCM 0.7 -- -- VCM 1.4 60 -50 -- -- 12 15 11 -- VCM 0.6 200 VCM 1.8 65 0 -- -- --
Input Referred, VCM 0.5V
VH = VCM + 1.8V, VL = VCM - 1.8V RL 500
G = +4, f < 100kHz
VCM 1.6 70 -60 0.8 5 -- 13 13
VS = 4.5V to 5.5V 65 Limiter Pins Open VCM 0.9 200 -- 35 35 -- 2 || 1 -60 15 5 300 20 55 15 30
VO = 2.5V
f = 5MHz VIN = VCM 0.4V (VO - VH) or (VO - VL) VIN = 0.4V, VO < 0.02Vp-p VIN = VCM to VCM 0.4V Step VIN = VCM 0.4V to VCM Step f = 5MHz, VO = 2Vp-p
35
-- -- -- -- -- --
(R)
OPA689
4
SPECIFICATIONS -- VS = +5V
(cont.)
OPA689U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
G = +6, RF = 750, RL = 500 tied to VCM = 2.5V, VL = VCM -1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted.
PARAMETER THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8
CONDITIONS
+25C
+25C
UNITS C C/W C/W
Specification: P, U
-40 to +85 100 125
-- -- --
-- -- --
-- -- --
Typ Typ Typ
C C C
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25C guaranteed specifications. Junction Temperature = Ambient Temperature + 23C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 7. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = VCM -1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM 1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. 6.5V Internal Power Dissipation ........................... See Thermal Characteristics Input Voltage Range ............................................................................ VS Differential Input Voltage ..................................................................... VS Limiter Voltage Range ........................................................... (VS - 0.7V) Storage Temperature Range: P, U ................................ -40C to +125C Lead Temperature (DIP, soldering, 10s) ...................................... +300C (SO-8, soldering, 3s) ...................................... +260C Junction Temperature .................................................................... +175C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
Top View DIP-8, SO-8
NC Inverting Input Non-Inverting Input -VS
1 2 3 4
8 7 6 5
VH +VS Output VL
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 006 182 SPECIFIED TEMPERATURE RANGE -40C to +85C -40C to +85C PACKAGE MARKING OPA689P OPA689U ORDERING NUMBER(1) OPA689P OPA689U OPA689U/2K5 TRANSPORT MEDIA Rails Rails Tape and Reel
PRODUCT OPA689P OPA689U
PACKAGE DIP-8 SO-8 Surface Mount
"
"
"
"
"
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "OPA689U/2K5" will get a single 2500-piece Tape and Reel.
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5
OPA689
TYPICAL PERFORMANCE CURVES-- VS = 5V
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 6
Normalized Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3
Normalized Gain (dB)
VO = 0.5Vp-p
G = +4 G = +6
VO = 0.5Vp-p
G = -4
3 0 -3 -6 -9 -12 -15 -18 -21 1M 10M 100M Frequency (Hz) 1G G = +20 G = +12
0 -3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) 1G G = -6
G = -12
SMALL-SIGNAL PULSE RESPONSE 0.5 0.4 0.3
Output Voltage (V)
LARGE-SIGNAL PULSE RESPONSE 2.5 2.0 1.5
Output Voltage (V)
VO = 0.5Vp-p
VO = 2Vp-p
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Time (5ns/div)
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (5ns/div)
VH--LIMITED PULSE RESPONSE 2.5 2.0
Input and Output Voltages (V)
VL--LIMITED PULSE RESPONSE 2.5 2.0
Input and Output Voltages (V)
VO
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (20ns/div) VH = +2V G = +6 VIN
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (20ns/div) VO VIN VL = -2V G = +6
(R)
OPA689
6
TYPICAL PERFORMANCE CURVES-- VS = 5V
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
(cont.)
HARMONIC DISTORTION vs FREQUENCY
2nd and 3rd Harmonic Distortion (dBc)
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 1M Frequency (Hz) 10M 20M HD3 VO = 2Vp-p RL = 500 HD2
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 HD3 HD2 VO = 0VDC 1Vp f1 = 5MHz RL = 500
Limit Voltage (V)
2ND HARMONIC DISTORTION vs OUTPUT SWING -40
2nd Harmonic Distortion (dBc)
3RD HARMONIC DISTORTION vs OUTPUT SWING -40
3rd Harmonic Distortion (dBc)
-45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.1
RL = 500
f1 = 20MHz f1 = 10MHz
-45 -50 -55 -60 -65 -70 -75 -80 -85 -90
RL = 500 f1 = 20MHz f1 = 10MHz f1 = 5MHz f1 = 2MHz f1 = 1MHz
f1 = 5MHz f1 = 2MHz f1 = 1MHz
1.0 Output Swing (Vp-p)
5.0
0.1
1.0 Output Swing (Vp-p)
5.0
HARMONIC DISTORTION vs LOAD RESISTANCE 2nd and 3rd Harmonic Distortion (dBc) -40 -45 -50 -55 HD2 VO = 2Vp-p f1 = 5MHz
21.6 18.6 15.6 12.6
LARGE SIGNAL FREQUENCY RESPONSE G = +6 2Vp-p 0.5Vp-p
Gain (dB)
-60 -65 -70 -75 -80 -85 -90 50 100 Load Resistance () 1000 HD3
9.6 6.6 3.6 0.6 -2.4 -5.4 -8.4 0.1 10M
100M Frequency (Hz)
1G
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7
OPA689
TYPICAL PERFORMANCE CURVES-- VS = 5V
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
(cont.)
RS vs CAPACITIVE LOAD 50 45
Gain to Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD 21.6 18.6 15.6 12.6 9.6 6.6 3.6 0.6 -2.4
150 VIN 125 RS
VO = 0.5Vp-p
CL = 0 CL = 100pF CL = 1000pF CL = 10pF
40 35
RS ()
30 25 20 15 10 5 0 1 10 100 1000 Capacitive Load (pF)
OPA689
750 1k
VO CL
-5.4 -8.4 0.1
1k is optional
10M
100M Frequency (Hz)
1G
OPEN-LOOP FREQUENCY RESPONSE
Input Voltage Noise Density (nV/Hz) Input Current Noise Density (pA/Hz)
INPUT NOISE DENSITY
60 50 Gain
Open-Loop Gain (dB)
0 -30 -60 Phase -90 VO = 0.5Vp-p -120 -150 -180 -210 -240 1G
Open-Loop Phase (deg)
100
40 30 20 10 0 -10 -20 10k 100k 1M 10M 100M Frequency (Hz)
Voltage Noise 10 4.6nV/Hz Current Noise
2.0pA/Hz 1 100 1k 10k 100k 1M 10M Frequency (Hz)
LIMITER SMALL-SIGNAL FREQUENCY RESPONSE 6 3 0 VO = 0.02Vp-p
LIMITER FEEDTHROUGH -30 -35 -40
Feedthrough (dB)
Limiter Gain (dB)
-3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) 1G
150 750 125 0.7VDC 8 VO VH = 0.02Vp-p + 2.0VDC
-45 -50 -55 -60 -65 -70 -75 -80 1M 10M Frequency (Hz) 50M
150 750 125 8 VO VH = 0.02Vp-p + 2VDC
(R)
OPA689
8
TYPICAL PERFORMANCE CURVES-- VS = 5V
G = +6, RL = 500, RF = 750, VH = -VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
(cont.)
CLOSED-LOOP OUTPUT IMPEDANCE 100
Limter Input Bias Current (A)
100
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE Maximum Over Temperature 75 50 25 Minimum Over Temperature 0 -25 -50 -75 Limiter Headroom = +VS - VH = VL - (-VS) Current = IVH or -IVL
G = +4 VO = 0.5Vp-p
Output Impedance ()
10
1
0.1 100k
1M
10M Frequency (Hz)
100M
1G
-100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Limiter Headroom (V)
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 20 200 100
PSR AND CMR vs TEMPERATURE
PSR and CMR, Input Referred (dB)
95 90 85 80 75 70 65 60 55 50 -50 -25 0 25 50 75 100 Ambient Temperature (C) CMRR PSR+ PSRR PSR-
18
Supply Current (mA)
16
Supply Current
160
14 | Output Current, Sinking | 12
140
120
10 -50 -25 0 25 50 75 Ambient Temperature (C)
100 100
VOLTAGE RANGES vs TEMPERATURE 5.0 VH = -VL = 4.3V
Voltage Range (V)
4.5 Output Voltage Range 4.0
3.5 Common-Mode Input Range 3.0 -50 -25 0 25 50 75 100 Ambient Temperature (C)
Output Current (mA)
Output Current, Sourcing
180
(R)
9
OPA689
TYPICAL PERFORMANCE CURVES-- VS = +5V
G = +6, RF = 402, RL = 500 tied to VCM = 2.5V, VL = VCM -1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted.
NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 6
Normalized Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3
Normalized Gain (dB)
VO = 0.5Vp-p
VO = 0.5Vp-p G = -4
3 0 -3 -6 -9 -12 -15 -18 -21 1M 10M 100M Frequency (Hz) 1G G = +20 G = +12 G = +6 G = +4
0 -3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) 1G G = -12 G = -6
LARGE-SIGNAL FREQUENCY RESPONSE 21.6 18.6 15.6 12.6 0.5Vp-p
VH AND VH--LIMITED PULSE RESPONSE 5.0 4.5
Input and Output Voltages (V)
VH = VCM +1.2V VL = VCM -1.2V VO
2Vp-p
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 VCM = 2.5V
Gain (dB)
9.6 6.6 3.6 0.6 -2.4 -5.4 -8.4 0.1 10M 100M Frequency (Hz) 1G
VIN
VIN
VO
Time (20ns/div)
HARMONIC DISTORTION vs FREQUENCY
2nd and 3rd Harmonic Distortion (dBc)
2nd and 3rd Harmonic Distortion (dBc)
HARMONIC DISTORTION NEAR LIMIT VOLTAGES -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 HD3 HD2 VO = 2.5VDC 1Vp f1 = 5MHz RL = 500
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 1M Frequency (Hz) 10M 20M HD3 VO = 2Vp-p RL = 500 HD2
| Limit Voltages - 2.5VDC |
(R)
OPA689
10
TYPICAL APPLICATIONS
DUAL SUPPLY, NON-INVERTING AMPLIFIER Figure 1 shows a non-inverting gain amplifier for dual supply operation. This circuit was used for AC characterization of the OPA689, with a 50 source, which it matches, and a 500 load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. SINGLE SUPPLY, NON-INVERTING AMPLIFIER Figure 2 shows an AC coupled, non-inverting gain amplifier for single supply operation. This circuit was used for AC
3.01k +VS = +5V + 2.2F 0.1F 1.91k
characterization of the OPA689, with a 50 source, which it matches, and a 500 load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL ) and their bias currents (IVH and IVL ) have the polarities shown. Notice that the single supply circuit can use 3 resistors to set VH and VL, where the dual supply circuit usually uses 4 to reference the limit voltages to ground. LOW DISTORTION, ADC INPUT DRIVER The circuit in Figure 3 shows an inverting, low distortion ADC driver that operates on single supply. The converter's internal references bias the op amp input. The 4.0pF and 18pF capacitors form a compensation network that allows
VS = +5V
0.1F VH = +2V
+ 2.2F 0.1F 523 0.1F VH = 3.7V 1.50k
100 VIN 49.9
3
7 8
IVH 6 500 VO
0.1F VIN 53.6
OPA689
2 5 4
3 1.50k 2
7 8
IVH 6
976 0.1F VO 500
RG 150
RF 750
IVL
OPA689
5 4
IVL
0.1F
0.1F VL = -2V
RF 750 0.1F RG 150 VL = 1.3V 523
+ -VS = -5V
2.2F
3.01k
1.91k
0.1F
FIGURE 1. DC-Coupled, Dual Supply Amplifier.
FIGURE 2. AC-Coupled, Single Supply Amplifier.
VS = +5V 787 VH = +3.6V
4.0pF
0.1F
0.1F VIN
374
750 100 VS = +5V 2 7 8 OPA689 3 4 REFB 0.1F 1.40k 1.40k +2.5V VL = +1.4V 787 +1.5V 100 5 6 24.9 IN 100pF ADS822 10-Bit 40MSPS +3.5V REFT RSEL
VS = +5V
18pF
+VS
10-Bit Data
INT/EXT GND
0.1F
FIGURE 3. Low Distortion, Limiting ADC Input Driver.
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the OPA689 to have a flat frequency response at a gain of - 2. This increases the loop gain of the op amp feedback network, which reduces the distortion products below their specified values. PRECISION HALF WAVE RECTIFIER Figure 4 shows a half wave rectifier with outstanding precision and speed. VH will default to a voltage between 3.1 and 3.8V if left open, while the negative limit is set to ground.
ID CD 5.0pF 3 -VB
CF 1.0pF 4.32k VO +VS = +5V 7 OPA689 2 4 5 NC NC 8 6
+VS = +5V
0.1F
4.32k -VS = -5V
124 VIN
2
7
NC 8
FIGURE 6. Transimpedance Amplifier.
6 VO
OPA689
3 4 150 750 5
DESIGN-IN TOOLS
APPLICATIONS SUPPORT The Burr-Brown Applications Department is available for design assistance at phone number 1-800-548-6132 (US/Canada only). The Burr-Brown Internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance of the OPA689 in both package styles. These will be available as an unpopulated PCB with descriptive documentation. See the board literature for more information. The summary information for these boards is shown below:
BOARD PART NUMBER DEM-OPA68xP DEM-OPA68xU LITERATURE REQUEST NUMBER MKT-350 MKT-351
-VS = -5V
FIGURE 4. Precision Half Wave Rectifier. VERY HIGH SPEED COMPARATOR Figure 5 shows a very high speed comparator with hysterisis. The output level are precisely defined, and the recovery time is exceptional. The output voltage swings between 0.5V and 3.5V to provide a logic level output that switches as VIN crosses VREF.
+VS = +5V 100 2.00k 604 VO 3 7 8 95.3 VIN 6 0.1F PRODUCT OPA689P OPA689U PACKAGE 8-Pin DIP 8-Pin SO-8
OPA689
2 4 5
1.21k
0.1F
Contact the Burr-Brown Applications Department for availability of these boards. SPICE MODELS Computer simulation of circuit performance using SPICE is often useful when analyzing analog circuit or system performance. This is particularly true for high speed amplifier circuits where parasitic capacitance and inductance can have a major effect on frequency response. SPICE models are available through the Burr-Brown web site (www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion, temperature effects, or different gain and phase characteristics. These models do not distinquish between the AC performance of different package types. 12
200k -VS = -5V
FIGURE 5. Very High Speed Comparator. TRANSIMPEDANCE AMPLIFIER Figure 6 shows a transimpedance amplifier that has exceptional overdrive characteristics. The feedback capacitor (CF) stabilizes the circuit for the assumed diode capacitance (CD).
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OPERATING INFORMATION
THEORY OF OPERATION The OPA689 is a voltage feedback op amp that is stable for gains +4. The output voltage is limited to a range set by the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of the output buffer. This avoids saturating any parts in the signal path, gives quick overdrive recovery, and gives consistent limiter accuracy for any gain. This part is de-compensated (stable for gains +4). This gives greater bandwidth, higher slew rate, and lower noise than the unity gain stable companion part OPA688. The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the limiter voltages to be set very near (<100 mV) the desired signal range. The distortion performance is also very good near the limiter voltages. CIRCUIT LAYOUT Achieving optimum performance with the high frequency OPA689 requires careful attention to layout design and component selection. Recommended PCB layout techniques and component selection criteria are: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere. b) Provide a high quality power supply. Use linear regulators, ground plane, and power planes, to provide power. Place high frequency 0.1F decoupling capacitors < 0.2" away from each power supply pin. Use wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2F to 6.8F) high frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several adjacent devices. c) Place external components close to the OPA689. This minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors. d) Use high frequency components to minimize parasitic elements. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. Never use wire-wound resistors for high frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances. Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2F to 6.8F) should be tantalum for better high frequency and pulse performance.
e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors > 1.5k, this adds a pole and/or zero below 500MHz. Make sure that the output loading is not too heavy. The recommended 750 feedback resistor is a good starting point in your design. f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation resistor recommended in the RS vs Capacitive Load plot. Parasitic loads < 2pF may not need the isolation resistor. g) When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50 transmission line is not required on board--a higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. If the 6dB of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. This will isolate the op amp output from the reactive load presented by the line, but the frequency response will be degraded. Multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. h) Do not use sockets for high speed parts like the OPA689. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part onto the board. If socketing for DIP prototypes is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. POWER SUPPLIES The OPA689 is nominally specified for operation using either 5V supplies or a single +5V supply. The maximum specified total supply voltage of 13V allows reasonable tolerances on the supplies. Higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow design of non-standard or single supply operation circuits. Figure 2 shows one approach to single-supply operation.
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ESD PROTECTION ESD damage is known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD damage. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are required when handling the OPA689. OUTPUT LIMITERS The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear region of operation to output limiting is sharp--the desired output signal can safely come to within 30mV of VH or VL. Distortion performance is also good over the same range. The limiter voltages can be set to within 0.7V of the supplies (VL -VS + 0.7V, VH +VS - 0.7V). They must also be at least 200mV apart (VH - VL 0.2V). When pins 5 and 8 are left open, VH and VL go to the Default Voltage Limit; the minimum values are in the spec table. Looking at Figure 7 for the zero bias current case will show the expected range of (VS - default limit voltages) = headroom). When the limiter voltages are more than 2.1V from the supplies (VL -VS + 2.1V or VH +VS - 2.1V), you can use simple resistor dividers to set V H and VL (see Figure 1). Make sure you include the Limiter Input Bias Currents (Figure 7) in the calculations (i.e., IVL -50A out of pin 5, and IVH +50A out of pin 8). For good limiter voltage accuracy, run at least 1mA quiescent bias current through these resistors.
When the limiter voltages need to be within 2.1V of the supplies (VL -VS + 2.1V or VH +VS - 2.1V), use low impedance voltage sources to set VH and VL to minimize errors due to bias current uncertainty. This will typically be the case for single supply operation (VS = +5V). Figure 2 runs 2.5mA through the resistive divider that sets VH and VL. This keeps errors due to IVH and IVL < 1% of the target limit voltages. The limiters' DC accuracy depends on attention to detail. The two dominant error sources can be improved as follows: * Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (e.g., (5%). Using a more accurate source, or bypassing pins 5 and 8 with good capacitors, will improve limiter PSRR. * The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Other error sources also contribute, but should have little impact on the limiters' DC accuracy: * Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as described above. * Consider the signal path DC errors as contributing to the uncertainty in the useable output range. * The Limiter Offset Voltage only slightly degrades the limiter accuracy. Figure 8 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for output voltages swinging right up to the limiter voltages.
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 HD3 HD2 VO = 0VDC 1Vp f1 = 5MHz RL = 500
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE 100 Maximum Over Temperature
Limter Input Bias Current (A)
75 50 25 Minimum Over Temperature 0 -25 -50 -75 -100 0.0 0.5 1.0 1.5 2.0 Limiter Headroom = +VS - VH = VL - (-VS) Current = IVH or -IVL 2.5 3.0 3.5 4.0 4.5 5.0
Limit Voltage (V)
FIGURE 8. Linearity Guardband.
Limiter Headroom (V)
FIGURE 7. Limiter Bias Current vs Limiter Voltage.
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OFFSET VOLTAGE ADJUSTMENT The circuit in Figure 9 allows offset adjustment without degrading offset drift with temperature. Use this circuit with caution since power supply noise can inadvertently couple into the op amp. Remember that additional offset errors can be created by the amplifier's input bias currents. Whenever possible, match the resistance seen by both DC Input Bias Currents by using R3. This minimizes the output offset voltage caused by the Input Bias Currents.
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either supply voltage. In this condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that it is the power in the output stage, and not in the load, that determines internal power dissipation. The operating junction temperature is: TJ = TA + PD JA, where TA is the ambient temperature. For example, the maximum TJ for a OPA689U with G = +6, RFB = 750, RL = 100, and VS = 5V at the maximum TA = +85C is calculated this way:
+VS RTRIM 47k
R2
OPA689 -VS 0.1F R1 R3 = R1 || R2
VO
P DQ = (10V * 20mA ) = 200mW P DL = 4 * (100 || 850 )
( 5V )2
P D = 200mW + 70mW = 270mW
VIN or Ground NOTES: (1) R3 is optional and minimizes output offset due to input bias currents. (2) Set R1 << RTRIM.
T J = 85 C + 270mW *125 C/ W = 119 C
CAPACITIVE LOADS Capacitive loads, such as flash A/D converters, will decrease the amplifier's phase margin, which may cause peaking or oscillations. Capacitive loads 1pF should be isolated by connecting a small resistor in series with the output as shown in Figure 10. Increasing the gain from +6 will improve the capacitive drive capabilities due to increased phase margin.
FIGURE 9. Offset Voltage Trim. OUTPUT DRIVE The OPA689 has been optimized to drive 500 loads, such as A/D converters. It still performs very well driving 100 loads. This makes the OPA689 an ideal choice for a wide range of high frequency applications. Many high speed applications, such as driving A/D converters, require op amps with low output impedance. As shown in the Output Impedance vs Frequency performance curve, the OPA689 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency. THERMAL CONSIDERATIONS The OPA689 will not require heat-sinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175C.
RISO OPA689 VO
RL RL is optional
CL
FIGURE 10. Driving Capacitive Loads. In general, capacitive loads should be minimized for optimum high frequency performance. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance.
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OPA689
FREQUENCY RESPONSE COMPENSATION The OPA689 is internally compensated to be stable at a gain of +4, and has a nominal phase margin of 60 at a gain of +6. Phase margin and peaking improve at higher gains. Recall that an inverting gain of -5 is equivalent to a gain of +6 for bandwidth purposes (i.e., noise gain = 6). Standard external compensation techniques work with this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. To maintain a large bandwidth at high gains, cascade several op amps. In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor "Tee" network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise generated by this feedback network too much. PULSE SETTLING TIME The OPA689 is capable of an extremely fast settling time in response to a pulse input. Frequency response flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an A/D converter, use the
recommended RS in the RS vs Capacitive Load plot. Extremely fine scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. The pulse settling characteristics when recovering from overdrive are very good. DISTORTION The OPA689's distortion performance is specified for a 500 load, such as an A/D converter. Driving loads with smaller resistance will increase the distortion as illustrated in Figure 11. Remember to include the feedback network in the load resistance calculations.
HARMONIC DISTORTION vs LOAD RESISTANCE
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 50 100 Load Resistance () 1000 HD3 HD2 VO = 2Vp-p f1 = 5MHz
FIGURE 11. 5MHz Harmonic Distortion vs Load Resistance.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE OPA689P OPA689U OPA689U/2K5 STATUS(1) ACTIVE ACTIVE ACTIVE PACKAGE TYPE PDIP SOIC SOIC PACKAGE DRAWING P D D PINS 8 8 8 PACKAGE QTY 50 100 2500
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

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