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| MITSUMI CMOS System Reset PST4XXAXXXN CMOS System Reset Monolithic IC PST4XXAXXXN Series Outline This is a reset IC for systems developed using the CMOS process. The CMOS process allows ultra-low current consumption of 1.5A typ. Further, a fixed delay timer is built in, so that power voltage is verified when power is turned on or interrupted for accurate system reset. Features 1 Detection voltage precision 1.5% (25C, VDD = VDET + 0.1 2 Low current consumption SOT-23 : 1.5A 3 External capacitor for delay timer not required. Built-in delay timer SOT-23 : 50/100/200/240/400ms 4 Full line of rank variation available for detection voltage, package, output form, delay timer. 5 Supports car devices with operating temperature range of -40 ~ +105C. Package SOT-23 Applications 1. Reset circuits in microcomputers, CPUs and MPUs 2. Logic circuit reset circuits. 3. Battery voltage check circuits. 4. Back-up power supply switching circuits. 5. Level detection circuits. 6. Mechanical reset circuits. Pin Assignment 3 1 2 3 1 2 GND VOUT VDD SOT-23 MITSUMI CMOS System Reset PST4XXAXXXN Block Diagram CMOS Output PST41 VDD A N Active-Low Output PST43 VDD A N Active-High Output TIMER VOUT TIMER VOUT GND GND N-ch Open Drain Output PST42 VDD A N Active-Low Output PST44 VDD A N Active-High Output TIMER VOUT TIMER VOUT GND GND Pin Explanations Pin No. Pin Name 1 2 3 GND VOUT VDD GND Pin Reset Signal Output Pin Power Supply Pin/Voltage Detect Pin Refer to 4.Block Diagram. Function Internal Equivalent Circuit Pin Explanations PST4 ab A d N f b TDEL Rank 1 2 3 4 5 50ms 100ms 200ms 240ms 400ms 160 ~ d VDET Rank VDET=1.60V ~ f Packing Specifications R L R Housing L Housing 1 2 3 4 a Output Type CMOS Output Active-Low Output N-ch Open Drain Output Active-Low Output CMOS Output Active-High Output N-ch Open Drain Output Active-High Output 480 VDET=4.80V MITSUMI CMOS System Reset PST4XXAXXXN Absolute Maximum Ratings Item Operating Temperature Storage Temperature Supply Voltage Output Voltage Output Current Power Dissipation (Ta=25C) Symbol TOPR TSTG VDD max. VOUT IOUT PD Rating -40~+105 -65~+160 6.5 GND-0.3~VDD max.+0.3(CMOS Type) GND-0.3~6.5(N-ch Open Drain Type) 20 150 Unit C C V V mA mW Recommended Operating Conditions Item Operating Temperature Symbol TOPR Rating -40~+105 Unit C MITSUMI CMOS System Reset PST4XXAXXXN Electrical Characteristics Item VDD Range Detecting Voltage Detecting Voltage Temp. Coefficient Supply Current (Unless otherwise specified, Ta=25C) Symbol VDD VDET VDET/ T ISS PST4 PST4 PST4 VOH PST4 PST4 PST4 PST4 Test Conditions Test Circuit 1 Test Circuit 1 < -40C=TOPR<105C Test Circuit1 = VDD=VDET+0.1 Test Circuit 2 160N ~ 230N 240N ~ 350N 360N ~ 480N 160N ~ 350N 360N ~ 480N 160N ~ 230N 240N ~ 350N 360N ~ 480N 160N ~ 350N 360N ~ 480N VDD=VDET-0.1V IOUT=150A VDD=VDET-0.1V IOUT=500A VDD=VDET-0.1V IOUT=800A VDD=VDET+0.1V IOUT=1.2mA VDD=VDET+0.1V IOUT=3.2mA VDD=VDET+0.1V IOUT=150A VDD=VDET+0.1V IOUT=500A VDD=VDET+0.1V IOUT=800A VDD=VDET-0.1V IOUT=1.2mA VDD=VDET-0.1V IOUT=3.2mA Min. Typ. Max. Unit 1.0 -1.5% 1.6V~4.8V (0.1V STEP) 30 1.5 3.5 6.0 +1.5% V V ppm/C A "H" Out put Voltage (PST41 A /42 A) 0.8VDD V Test Circuit 6 PST4 VOL PST4 PST4 PST4 PST4 "H" Out put Voltage (PST43 A /44 A) PST4 VOH PST4 PST4 PST4 PST4 "L" Out put Voltage (PST43 A /44 A) PST4 VOL PST4 PST4 0.3 V "L" Out put Voltage (PST41 A /42 A) 0.4 V Test Circuit 7 0.8VDD V Test Circuit 6 0.3 V 0.4 35 70 50 100 200 240 400 20 0.1 65 130 260 310 520 V Test Circuit 7 Reset Active Timeout Period TDEL Test Circuit 8 140 170 280 ms VDD to Reset Delay Output Leakage Current (PST42 A /44 A) TDET ILEAK Test Circuit 8 Test Circuit 5 s A Note 1: This device is tested at only normal temperature. Over temperature limit guaranteed by desigh only. Note 2: This device has no Hysteresis Voltage. MITSUMI CMOS System Reset PST4XXAXXXN Measuring Circuit (1)-a PST41 A / 43 A (1)-b PST42 A / 44 A VDD 3 VIN PST 4 A2 1 GND VIN OUT VDD 3 RL PST 4 A 2 OUT 1 GND (2) ISS VDD 3 VIN PST 4 A2 1 GND (3) VDD 3 VIN PST 4 A2 1 GND ISINK OUT VDS (4) (5) VDD 3 VIN PST 4 A2 1 GND ISOURCE OUT VDS VIN VDD 3 PST 4 A2 1 GND ILEAK OUT VDS MITSUMI CMOS System Reset PST4XXAXXXN Measuring Circuit (6) (7) VDD 3 VIN PST 4 A2 1 GND IOH OUT VIN V VOH VDD 3 PST 4 A2 1 GND IOL OUT V VOL (8) PST41 A / 43 A (9) PST42 A / 44 A VDD 3 VIN PST 4 A2 1 GND VIN OUT VDD 3 RL=470k PST 4 A 2 OUT 1 GND VDET+1.0V Input Voltage VDET 1.0V GND Output Voltage PST41 A PST42 A 100% 50% GND TDEL 100% 50% GND TDEL Delay Time TDET TDET Output Voltage PST43 A PST44 A MITSUMI CMOS System Reset PST4XXAXXXN Application Circuits VDD VDD 3 VIN RESET PST 4 A2 VOUT 1 GND Logic System VIN VDD 3 PST 4 A2 OUT 1 GND Please note that there is any possibility of circuit oscillation when resistance put in the line VIN. Load current and load resistance should be adjusted, which not over power dissipation level. PD>(VDD-VOH) * IOH PD> VOL * IOL We shall not be liable for any trouble or damage caused by using this circuit. In the event a problem which may affect industrial property or any other rights of us or a third party is encountered during the use of information described in these circuit, Mitsumi Electric Co., Ltd. shall not be liable for any such problem, nor grant a license therefore. MITSUMI CMOS System Reset PST4XXAXXXN Timing Chart PST41 A / 42 V A Active-Low Output VDET VDD V TDEL VOUT TDEL PST43 A / 44 V A Active-High Output VDD VDET V TDEL VOUT TDEL MITSUMI CMOS System Reset PST4XXAXXXN Characteristics Detecting voltage (PST414A290N 4 ) Detecting voltage (PST434A290N ) * Output Voltage (V) 4 3 2 1 0 * Output Voltage (V) 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 Input Voltage (V) Test Circuit 1-b (RL=12k) Input Voltage (V) Test Circuit 1-b (RL=12k) * When Input Voltage is Under 1.0V, Output Voltage is Unstable. Supply current 2.5 Supply Current (A) 2 1.5 1 0.5 0 0 1 2 VDET=2.90V VDET=4.60V 3 4 5 Input Voltage (V) Test Circuit 2 N-ch Output current (PST414A460N N-ch Output Current (mA) 60 50 VDD=4V 40 30 VDD=3V 20 VDD=2V 10 0 0 VDD=1V 0.5 1 1.5 2 2.5 3 3.5 ) P-ch Output current (PST414A290N P-ch Output Current (mA) 60 50 40 30 VDD=4V 20 10 0 0 1 2 3 4 VDD=3V VDD=5V ) 4 5 VDS (V) Test Circuit 3 VDD-VDS (V) Test Circuit 4 Note: These are typical characteristics. MITSUMI CMOS System Reset PST4XXAXXXN Characteristics Detecting voltage vs temperature (PST414A290N ) 2.93 Supply current vs temperature (PST414A290N ) 4 Detecting Voltage (V) 2.92 2.91 2.90 2.89 2.88 2.87 -40 -20 Supply Current (A) 0 20 40 60 80 100 3 2 1 0 -40 -20 0 20 40 60 80 100 Temperature (C) Test Circuit 1-a Temperature (C) Test Circuit 2 Threshold Operating Voltage Vs temperature Threshold Operating Voltage (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -40 -20 Output leakage current vs temperature Output Leakage Current (nA) 20 15 10 5 0 -40 -20 0 20 40 60 80 100 0 20 40 60 80 100 Temperature (C) Test Circuit 7 Temperature (C) Test Circuit 5 Reset active timeout period vs temperature Reset Active Timeout Period (ms) 350 300 250 200 150 -40 -20 VDD to reset delay vs temperature VDD To Reset Delay (s) 50 40 30 20 10 0 -40 -20 0 20 40 60 80 100 0 20 40 60 80 100 Temperature (C) Test Circuit 8 Temperature (C) Test Circuit 8 Note: These are typical characteristics. MITSUMI CMOS System Reset PST4XXAXXXN Characteristics "H"Output voltage vs temperature (PST414A290N ) 3.00 "L"Output voltage vs temperature (PST414A290N ) 0.50 Output Voltage (V) Output Voltage (V) 0 20 40 60 80 100 2.95 2.90 2.85 2.80 -40 -20 0.40 0.30 0.20 0.10 0.00 -40 -20 0 20 40 60 80 100 Temperature (C) Test Circuit 6 Temperature (C) Test Circuit 7 Maximum transient duration vs VDET-VDD Maximum Transient Duration (s) 250 200 150 100 50 0 1 10 100 1000 VDET=2.90V Reset active timeout period vs VDD-VDET (PST414A290N ) Reset Active Timeout Period (ms) 350 300 250 200 150 0 1 2 3 4 VDET=4.60V VDET-VDD (mV) Test Circuit 8 VDD-VDET (V) Test Circuit 8 Note: These are typical characteristics. |
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