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INTEGRATED CIRCUITS
DATA SHEET
SAA7118E Multistandard video decoder with adaptive comb filter and component video input
Preliminary specification Supersedes data of 2000 Nov 21 File under Integrated Circuits, IC22 2000 Nov 27
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 10 10.1 10.2 FEATURES Video acquisition/clock Video decoder Component video processing Video scaler Vertical Blanking Interval (VBI) data decoder and slicer Audio clock generation Digital I/O interfaces Miscellaneous APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder Component video processing Decoder output formatter Scaler VBI-data decoder and capture (subaddresses 40H to 7FH) Image port output formatter (subaddresses 84H to 87H) Audio clock generation (subaddresses 30H to 3FH) INPUT/OUTPUT INTERFACES AND PORTS Analog terminals Audio clock signals Clock and real-time synchronization signals Interrupt handling Video expansion port (X-port) Image port (I-port) Host port for 16-bit extension of video data I/O (H-port) Basic input and output timing diagrams I-port and X-port BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes 16 16.1 16.2 16.3 16.4 16.5 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 LIMITING VALUES
SAA7118E
THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION I2C-BUS DESCRIPTION I2C-bus format I2C-bus details Programming register RGB/Y-PB-PR component input processing Interrupt mask registers Programming register audio clock generation Programming register VBI-data slicer Programming register interfaces and scaler part PROGRAMMING START SET-UP Decoder part Component video part and interrupt mask Audio clock generation part Data slicer and data type control part Scaler and interfaces PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
1 1.1 FEATURES Video acquisition/clock
SAA7118E
* Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals) * Up to eight analog Y + C inputs, split as desired * Up to four analog component inputs, with embedded or separate sync, split as desired * Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs) * Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals * Switchable white peak control * Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz) * Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties * On-chip line-locked clock generation in accordance with "ITU 601" * Requires only one crystal (32.11 or 24.576 MHz) for all standards * Horizontal and vertical sync detection. 1.2 Video decoder * Independent gain and offset adjustment for raw data path. 1.3 Component video processing
* RGB component inputs * Y-PB-PR component inputs * Fast blanking between CVBS and synchronous component inputs * Digital RGB to Y-CB-CR matrix. 1.4 Video scaler
* Horizontal and vertical downscaling and upscaling to randomly sized windows * Horizontal and vertical scaling range: variable zoom to 1 (icon) (note: H and V zoom are restricted by the 64 transfer data rates) * Anti-alias and accumulating filter for horizontal scaling * Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) * Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) * Two independent programming sets for scaler part, to define two `ranges' per field or sequences over frames * Fieldwise switching between decoder part and expansion port (X-port) input * Brightness, contrast and saturation controls for scaled outputs. 1.5 Vertical Blanking Interval (VBI) data decoder and slicer
* Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR * Automatic detection of any supported colour standard * Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM * Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals - Increased luminance and chrominance bandwidth for all PAL and NTSC standards - Reduced cross colour and cross luminance artefacts * PAL delay line for correcting PAL phase errors * Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals * User programmable sharpness control * Detection of copy-protected signals according to the macrovision standard, indicating level of protection
* Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
1.6 Audio clock generation 2 APPLICATIONS
SAA7118E
* Generation of a field-locked audio master clock to support a constant number of audio clocks per video field * Generation of an audio serial and left/right (channel) clock signal. 1.7 Digital I/O interfaces
* Desktop video * Multimedia * Digital television * Image processing * Video phone * PC editing cards * PC tuner cards. 3 GENERAL DESCRIPTION
* Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document "RTC Functional Specification" for details) * Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-CB-CR - Output from decoder part, real-time and unscaled - Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible) * Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals * Discontinuous data streams supported * 32-word x 4-byte FIFO register for video output data * 28-word x 4-byte FIFO register for decoded VBI-data output * Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-CB-CR output * Scaled 8-bit luminance only and raw CVBS data output * Sliced, decoded VBI-data output. 1.8 Miscellaneous
The SAA7118E is a video capture device for applications at the image port of VGA controllers. Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video. The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB-PR or RGB. An expansion port (X-port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7118E supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAA7118E is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.
* Power-on control * 5 V tolerant digital inputs and I/O ports * Software controlled power saving standby modes supported * Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s * Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994" * BGA156 package.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
The SAA7118E also provides a means for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available: 1. To capture raw video samples, after interpolation to the required output data rate, via the scaler 2. A versatile data slicer (data recovery) unit. The SAA7118E also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback. 4 QUICK REFERENCE DATA SYMBOL VDDD VDDDC VDDA Tamb PA+D Note PARAMETER digital supply voltage digital core supply voltage analog supply voltage ambient temperature analog and digital power dissipation note 1 CONDITIONS MIN. 3.0 3.0 3.1 0 - TYP. 3.3 3.3 3.3 - 1.1
SAA7118E
All of the ADCs may be used to digitize a VSB signal for subsequent decoding; a dedicated output port and a selectable VSB clock input is provided. The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).
MAX. 3.6 3.6 3.5 70 1.35 V V V C W
UNIT
1. Power dissipation is measured in component mode (four ADCs active) and 8-bit image port output mode, expansion port is 3-stated. 5 ORDERING INFORMATION TYPE NUMBER SAA7118E PACKAGE NAME BGA156 DESCRIPTION plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm VERSION SOT472-1
2000 Nov 27
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LINE FIFO BUFFER
ANALOG INPUT CONTROL
and ADC2
C
CROMINANCE PROCESSING
CR
Y-CB-CR
AI31 AI32 AI33 AI34 AI3D AI41 AI42 AI43 AI44 AI4D AOUT AGND AGNDA
ANALOG3 and ADC3
COMB FILTER
VIDEO FIFO
CB
BCS-SCALER
ANALOG2
OUTPUT FORMATTER I PORT
FIR-PREFILTER PRESCALER
AI21 AI22 AI23 AI24 AI2D
VERTICAL SCALING
RAW
DECODER OUTPUT CONTROL
HORIZONTAL FINE (PHASE) SCALING
2000 Nov 27
FSW AI11 AI12 AI13 AI14 AI1D
6
Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
BLOCK DIAGRAM
ADP [8:0] CLKEXT CE
RES TEST
SDA
SCL
INT_A
AD PORT
CONTROL
I2C-BUS REGISTER MAP
FIRST TASK I2C-BUS REGISTER MAP SCALER SECOND TASK I2C-BUS REGISTER MAP SCALER
ANALOG1 and ADC1 R G B
FAST SWITCH DELAY Y CB CR S
SCALER EVENT CONTROLLER
COMPONENTS PROCESSING
IGP1 IGP0 IGPV IGPH IPD [7:0]
6
SAA7118E
RAW Y-CB-CR TEXT FIFO VBI-DATA SLICER
Y S LUMININANCE PROCESSING S S SYNCHRONIZATION Y
ICLK IDQ ITRDY ITRI
ANALOG4 and ADC4
S CB-CR Y-CB-CRS CB-CR VIDEO/TEXT ARBITER
POWER-ON CONTROL POWER SUPPLY
VIDEO CLOCK
GPO
CRYSTAL
X PORT
H PORT
AUDIO CLOCK
BOUNDARY SCAN
Preliminary specification
VSSA
VSSD
VDDA
VDD(xtal) LLC2 VSS(xtal) VDDD LLC
RTS0
RTCO
XTALI
XRDY
XCLK XDQ
XRH XRV
XTRI
AMXCLK ALRCLK HPD [7:0] AMCLK
TDO TDI
TRST TCK
TMS
MHB724
SAA7118E
RTS1
XTALO
XTOUT XPD [7:0]
ASCLK
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
7 PINNING TYPE(1) O O P O O I/O I/O I/O I/O I/O I/pu I/pu I O P I I/pu I/pu I/O I/O I/O I/O I DESCRIPTION crystal oscillator output signal; auxiliary signal
SAA7118E
SYMBOL PIN XTOUT XTALO VSS(xtal) TDO XRDY XCLK XPD0 XPD2 XPD4 XPD6 TEST1 TEST2 AI41 TEST3 VDD(xtal) XTALI TDI TCK XDQ XPD1 XPD3 XPD5 XTRI A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock input of XTALI is used ground for crystal oscillator test data output for boundary scan test; note 2 task flag or ready signal from scaler, controlled by XRQT clock I/O expansion port LSB of expansion port data MSB - 5 of expansion port data MSB - 3 of expansion port data MSB - 1 of expansion port data do not connect, reserved for future extensions and for testing: scan input do not connect, reserved for future extensions and for testing: scan input analog input 41 do not connect, reserved for future extensions and for testing supply voltage for crystal oscillator input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal test data input for boundary scan test; note 2 test clock for boundary scan test; note 2 data qualifier for expansion port MSB - 6 of expansion port data MSB - 4 of expansion port data MSB - 2 of expansion port data X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE in subaddress 83H) do not connect, reserved for future extensions and for testing: scan output do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing ground for analog inputs AI4x analog ground do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing digital supply voltage 1 (peripheral cells) test reset input (active LOW), for boundary scan test (with internal pull-up); notes 2, 3 and 4 horizontal reference I/O expansion port digital supply voltage 2 (core) digital supply voltage 3 (peripheral cells) digital supply voltage 4 (core) 7
TEST4 TEST5 TEST6 VSSA4 AGND TEST7 TEST8 VDDD1 TRST XRH VDDD2 VDDD3 VDDD4
B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
O NC NC P P NC NC P I/pu I/O P P P
2000 Nov 27
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PIN XPD7 TEST9 TEST10 TEST11 AI43 AI42 AI4D VDDA4 VSSD1 TMS VSSD2 XRV VSSD3 VSSD4 VSSD5 VDDD5 TEST12 HPD0 AI44 VDDA4A AI31 VSSA3 HPD1 HPD3 HPD2 HPD4 AI3D AI32 AI33 VDDA3 VSSD6 VDDD6 HPD5 HPD6 AI34 2000 Nov 27 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 TYPE(1) I/O NC NC I/pu I I I P P I/pu P I/O P P P P I/pu I/O I P I P I/O I/O I/O I/O I/O I I P P P I/O I/O I MSB of expansion port data do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing DESCRIPTION
SAA7118E
do not connect, reserved for future extensions and for testing: scan input analog input 43 analog input 42 differential input for ADC channel 4 (pins AI41 to AI44) analog supply voltage for analog inputs AI4x (3.3 V) digital ground 1 (peripheral cells) test mode select input for boundary scan test or scan test; note 2 digital ground 2 (core; substrate connection) vertical reference I/O expansion port digital ground 3 (peripheral cells) digital ground 4 (core) digital ground 5 (peripheral cells) digital supply voltage 5 (peripheral cells) do not connect, reserved for future extensions and for testing: scan input LSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port analog input 44 analog supply voltage for analog inputs AI4x (3.3 V) analog input 31 ground for analog inputs AI3x MSB - 6 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port MSB - 4 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port MSB - 5 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port MSB - 3 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port differential input for ADC channel 3 (pins AI31 to AI34) analog input 32 analog input 33 analog supply voltage for analog inputs AI3x (3.3 V) digital ground 6 (core) digital supply voltage 6 (core) MSB - 2 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port MSB - 1 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port analog input 34 8
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PIN VDDA3A AI22 AI21 VSSD7 IPD1 HPD7 IPD0 AI2D AI23 VSSA2 VDDA2 IPD2 VDDD7 IPD4 IPD3 VDDA2A AI11 AI24 VSSA1 VSSD8 VDDD8 IPD6 IPD5 AI12 AI13 AI1D VDDA1 IPD7 IGPH IGP1 IGPV VDDA1A AGNDA AI14 VSSD9 VSSD10 ADP6 ADP3 G2 G3 G4 G11 G12 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 TYPE(1) P I I P O I/O O I I P P O P O O P I I P P P O O I I I P O O O O P P I P P O O analog input 22 analog input 21 digital ground 7 (peripheral cells) MSB - 6 of image port data output DESCRIPTION analog supply voltage for analog inputs AI3x (3.3 V)
SAA7118E
MSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port LSB of image port data output differential input for ADC channel 2 (pins AI24 to AI21) analog input 23 ground for analog inputs AI2x analog supply voltage for analog inputs AI2x MSB - 5 of image port data output digital supply voltage 7 (peripheral cells) MSB - 3 of image port data output MSB - 4 of image port data output analog supply voltage for analog inputs AI2x analog input 11 analog input 24 ground for analog inputs AI1x digital ground 8 (core) digital supply voltage 8 (core) MSB - 1 of image port data output MSB - 2 of image port data output analog input 12 analog input 13 differential input for ADC channel 1 (pins AI14 to AI11) analog supply voltage for analog inputs AI1x (3.3 V) MSB of image port data output multi purpose horizontal reference output signal; image port (controlled by subaddresses 84H and 85H) general purpose output signal 1; image port (controlled by subaddresses 84H and 85H) multi purpose vertical reference output signal; image port (controlled by subaddresses 84H and 85H) analog supply voltage for analog inputs AI1x (3.3 V) analog signal ground analog input 14 digital ground 9 (peripheral cells) digital ground 10 (core) MSB - 2 of direct analog-to-digital converted output data (VSB) MSB - 5 of direct analog-to-digital converted output data (VSB)
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PIN VSSD11 VSSD12 RTCO L8 L9 L10 TYPE(1) P P O/st/pd digital ground 11 (peripheral cells) digital ground 12 (core) DESCRIPTION
SAA7118E
real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see document "RTC Functional Description", available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see notes 5, 6 and Table 35 digital ground 13 (peripheral cells) image port output control signal, affects all input port pins inclusive ICLK, enable and active polarity is under software control (bits IPE in subaddress 87H); output path used for testing: scan output output data qualifier for image port (optional: gated clock output) general purpose output signal 0; image port (controlled by subaddresses 84H and 85H) analog test output (do not connect) ground for internal Clock Generation Circuit (CGC) analog supply voltage (3.3 V) for internal clock generation circuit digital supply voltage 9 (peripheral cells) digital supply voltage 10 (core) MSB - 1 of direct analog-to-digital converted output data (VSB) MSB - 6 of direct analog-to-digital converted output data (VSB) digital supply voltage 11 (peripheral cells) digital supply voltage 12 (core) real-time status or sync information, controlled by subaddresses 11H and 12H digital supply voltage 13 (peripheral cells) audio master external clock input fast switch (blanking) with internal pull-down inserts component inputs into CVBS signal clock output signal for image port, or optional asynchronous back-end clock input do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing chip enable or reset input (with internal pull-up) line-locked 12 clock output (13.5 MHz nominal) external clock input intended for analog-to-digital conversion of VSB signals (36 MHz) MSB - 3 of direct analog-to-digital converted output data (VSB) LSB of direct analog-to-digital converted output data (VSB) serial clock input (I2C-bus) real-time status or sync information, controlled by subaddresses 11H and 12H audio serial clock output target ready input for image port data do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing external mode clear (with internal pull-down) 10
VSSD13 ITRI
L11 L12
P I/(O)
IDQ IGP0 AOUT VSSA0 VDDA0 VDDD9 VDDD10 ADP7 ADP2 VDDD11 VDDD12 RTS0 VDDD13 AMXCLK FSW ICLK TEST13 TEST14 TEST15 CE LLC2 CLKEXT ADP5 ADP0 SCL RTS1 ASCLK ITRDY TEST16 TEST17 TEST18 EXMCLR
L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P2 P3
O O O P P P P O O P P O P I I/pd I/O NC I/pu I/pd I/pu O I O O I O O I NC NC I/O I/pd
2000 Nov 27
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PIN LLC RES ADP8 ADP4 ADP1 INT_A SDA AMCLK ALRCLK P4 P5 P6 P7 P8 P9 P10 P11 P12 TYPE(1) O O O O O O/od I/O/od O O/st/pd reset output (active LOW) MSB of direct analog-to-digital converted output data (VSB) MSB - 4 of direct analog-to-digital converted output data (VSB) MSB - 7 of direct analog-to-digital converted output data (VSB) I2C-bus interrupt flag (LOW if any enabled status bit has changed) serial data input/output (I2C-bus) audio master clock output, up to 50% of crystal clock DESCRIPTION line-locked system clock output (27 MHz nominal)
SAA7118E
audio left/right clock output; can be strapped to supply via a 3.3 k resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 5 and 7 do not connect, reserved for future extensions and for testing: scan input
TEST19 Notes
P13
I/pu
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. 2. In accordance with the "IEEE1149.1" standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. 3. For board design without boundary scan implementation connect the TRST pin to ground. 4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 5. Pin strapping is done by connecting the pin to the supply via a 3.3 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). 6. Pin RTCO operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H. 7. Pin ALRCLK: 0 = 24.576 MHz crystal (default; Philips order number 4322 143 05291); 1 = 32.110 MHz crystal (Philips order number 9922 522 00013).
handbook, halfpage
MHB725
P N M L K J H G F E D C B A
SAA7118E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.2 Pin configuration.
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Table 1
Pin assignment (top view)
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
1 A B C D E F G H J K L M N P AI41 VSSA4 AI43 AI44 AI3D AI34 AI2D VDDA2A AI12 VDDA1A AOUT
2 XTOUT TEST3 AGND AI42 VDDA4A AI32 VDDA3A AI23 AI11 AI13 AGNDA VSSA0
3 XTALO VDD(xtal) TEST7 AI4D AI31 AI33 AI22 VSSA2 AI24 AI1D AI14 VDDA0
4 VSS(xtal) XTALI TEST8 VDDA4 VSSA3 VDDA3 AI21 VDDA2 VSSA1 VDDA1 VSSD9 VDDD9 CE LLC
5 TDO TDI VDDD1 VSSD1
6 XRDY TCK TRST TMS
7 XCLK XDQ XRH VSSD2
8 XPD0 XPD1 VDDD2 XRV
9 XPD2 XPD3 VDDD3 VSSD3
10 XPD4 XPD5 VDDD4 VSSD4
11 XPD6 XTRI XPD7 VSSD5 HPD1 VSSD6 VSSD7 IPD2 VSSD8 IPD7
12 TEST1 TEST4 TEST9 VDDD5 HPD3 VDDD6 IPD1 VDDD7 VDDD8 IGPH ITRI
13 TEST2 TEST5
14
TEST6
TEST10 TEST11 TEST12 HPD2 HPD5 HPD7 IPD4 IPD6 IGP1 IDQ FSW HPD0 HPD4 HPD6 IPD0 IPD3 IPD5 IGPV IGP0 ICLK
VSSD10 VDDD10 LLC2 RES
ADP6 ADP7 CLKEXT ADP8
ADP3 ADP2 ADP5 ADP4
VSSD11 VDDD11 ADP0 ADP1
VSSD12 VDDD12 SCL INT_A
RTCO RTS0 RTS1 SDA
VSSD13
VDDD13 AMXCLK ASCLK ITRDY
Preliminary specification
SAA7118E
TEST13 TEST14 TEST15 TEST18 EXMCLR
TEST16 TEST17
AMCLK ALRCLK TEST19
Table 2
8-bit/16-bit and alternative pin functional configurations
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
PIN
SYMBOL
8-BIT INPUT MODES D1 data input
16-BIT INPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) Y data input
ALTERNATIVE INPUT FUNCTIONS
8-BIT OUTPUT MODES D1 decoder output
16-BIT OUTPUT MODES (ONLY FOR I2C-BUS PROGRAMMING)
ALTERNATIVE OUTPUT FUNCTIONS
I/O CONFIGURATION PROGRAMMING BITS XCODE[92H[3]] XPE[1:0] 83H[1:0] + pin XTRI
C11, A11, B10, A10, B9, A9, B8, A8 A7
XPD7 to XPD0
XCLK
clock input
gated clock input
decoder clock output data qualifier output (HREF and VREF gate)
XPE[1:0] 83H[1:0] + pin XTRI XPCK[1:0] 83H[5:4] XCKS[92H[0]] XDQ[92H[1]] XPE[1:0] 83H[1:0] + pin XTRI
B7
XDQ
data qualifier input
A6
XRDY
input ready output horizontal reference input vertical reference input output enable input
active task A/B flag decoder horizontal reference output decoder vertical reference output
XRQT[83H[2]] XPE[1:0] 83H[1:0] + pin XTRI XDH[92H[2]] XPE[1:0] 83H[1:0] + pin XTRI XDV[1:0] 92H[5:4] XPE[1:0] 83H[1:0] + pin XTRI
C7
XRH
D8
XRV
Preliminary specification
B11
XTRI
XPE[1:0] 83H[1:0]
SAA7118E
2000 Nov 27 14
Philips Semiconductors
PIN
SYMBOL
8-BIT INPUT MODES
16-BIT INPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) CB-CR data input
ALTERNATIVE INPUT FUNCTIONS
8-BIT OUTPUT MODES
16-BIT OUTPUT MODES (ONLY FOR I2C-BUS PROGRAMMING) CB-CR scaler output
ALTERNATIVE OUTPUT FUNCTIONS
I/O CONFIGURATION PROGRAMMING BITS ICODE[93H[7]] ISWP[1:0] 85H[7:6] I8_16[93H[6]] IPE[1:0] 87H[1:0] + pin ITRI
Multistandard video decoder with adaptive comb filter and component video input
G13, HPD7 to F14, HPD0 F13, E14, E12, E13, E11, D14 K11, IPD7 to J13, J14, IPD0 H13, H14, H11, G12,G14 M14 ICLK
D1 scaler output
Y scaler output
ICODE[93H[7]] ISWP[1:0] 85H[7:6] I8_16[93H[6]] IPE[1:0] 87H[1:0] + pin ITRI clock input ICKS[1:0] 80H[1:0] IPE[1:0] 87H[1:0] + pin ITRI ICKS[3:2] 80H[3:2] IDQP[85H[0]] IPE[1:0] 87H[1:0] + pin ITRI
clock output data qualifier output target ready input H-gate output
L13
IDQ
gated clock output
N12 K12
ITRDY IGPH
extended H-gate, horizontal pulses V-sync, vertical pulses
IDH[1:0] 84H[1:0] IRHP[85H[1]] IPE[1:0] 87H[1:0] + pin ITRI IDV[1:0] 84H[3:2] IRVP[85H[2]] IPE[1:0] 87H[1:0] + pin ITRI Preliminary specification
K14
IGPV
V-gate output
SAA7118E
2000 Nov 27 15
Philips Semiconductors
PIN
SYMBOL
8-BIT INPUT MODES
16-BIT INPUT MODES (ONLY FOR I2C-BUS PROGRAMMING)
ALTERNATIVE INPUT FUNCTIONS
8-BIT OUTPUT MODES general purpose
16-BIT OUTPUT MODES (ONLY FOR I2C-BUS PROGRAMMING)
ALTERNATIVE OUTPUT FUNCTIONS
I/O CONFIGURATION PROGRAMMING BITS IDG1[1:0] 84H[5:4] IG1P[85H[3]] IPE[1:0] 87H[1:0] + pin ITRI IDG0[1:0] 84H[7:6] IG0P[85H[4]] IPE[1:0] 87H[1:0] + pin ITRI
Multistandard video decoder with adaptive comb filter and component video input
K13
IGP1
L14
IGP0
general purpose
L12
ITRI
output enable input
Preliminary specification
SAA7118E
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8 8.1 8.1.1 FUNCTIONAL DESCRIPTION Decoder ANALOG INPUT PROCESSING
SAA7118E
The SAA7118E offers sixteen analog signal inputs, four analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.6. 8.1.2 ANALOG CONTROL CIRCUITS
The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown in Fig.3. During the vertical blanking period gain and clamping control are frozen.
MGD138
6 V (dB) 0 -6 -12 -18 -24 -30 -36 -42
0
2
4
6
8
10
12
f (MHz)
14
Fig.3 Anti-alias filter.
2000 Nov 27
16
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.1.2.1 Clamping
SAA7118E
The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the four ADC channels are fixed for luminance (120), chrominance (256) and for component inputs as component Y (32), components PB and PR (256) or components RGB (32). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal.
The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. Component inputs are gain adjusted manually at a fixed gain. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 7 and 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.
8.1.2.2
Gain control
The gain control circuit receives (via the I2C-bus) the static gain levels for the four analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO).
handbook, halfpage
TV line analog line blanking
analog input level +3 dB maximum
controlled ADC input level
511
GAIN 120 1
CLAMP
0 dB (1 V (p-p) 18/56 ) -6 dB
range 9 dB
0 dB
minimum
MHB325
HCL HSY
MHB726
Fig.4
Analog line with clamp (HCL) and gain range (HSY).
Fig.5 Automatic gain range.
2000 Nov 27
17
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, full pagewidth
TEST SELECTOR AND BUFFER DIGITAL TEST SELECTOR
AOUT
AOSL[2:0]
ADP[8:0]
AI44 AI43 AI42 AI41 AI4D
DOSL[1:0] SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 ANTI-ALIAS FILTER BYPASS SWITCH ADC4
FUSE[1:0] AI34 AI33 AI32 AI31 AI3D ANALOG AMPLIFIER DAC9
SOURCE SWITCH
CLAMP CIRCUIT
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC3
FUSE[1:0] AI24 AI23 AI22 AI21 AI2D ANALOG AMPLIFIER DAC9
SOURCE SWITCH
CLAMP CIRCUIT
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC2
FUSE[1:0] AI14 AI13 AI12 AI11 AI1D ANALOG AMPLIFIER DAC9
SOURCE SWITCH
CLAMP CIRCUIT
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC1
FUSE[1:0]
MODE CONTROL
CLAMP CONTROL
GAIN CONTROL
ANTI-ALIAS CONTROL
VERTICAL BLANKING CONTROL
MODE[5:0]
HCL
GLIMB HSY GLIMT WIPA SLTCA
HOLDG GAFIX WPOFF GUDL[1:0] GAI[28:20] GAI[18:10] HLNRS UPTCV
VBSL
VBLNK SVREF
9
9
9
9
ANALOG CONTROL
CROSS MULTIPLEXER 9 CVBS/Y 9 CHROMA 9 R/R - Y 9 G/Y 9 B/B - Y 9 9
MHB727
AD2/4BYP AD1/3BYP
Fig.6 Analog input processing using the SAA7118E as differential front-end with 9-bit ADC.
2000 Nov 27
18
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, full pagewidth
ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 9 LUMA/CHROMA DECODER gain DAC 9
NO ACTION
1
VBLK 1
0 0
HOLDG 1
X 1
0 0
HSY
0 0 1
> 510
1 1 0 1 0
<4
<1
> 510
X=0 1 > 496 0
X=1
+1/F STOP
+1/L
-1/LLC2
+1/LLC2
-1/LLC2
+/- 0
GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-3/+6 dB] 1 0 1
X
HSY 1
0 0
Y
AGV X = system variable. Y = AGV - FGV > GUDL . GUDL = gain update level (adjustable). VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.
UPDATE
FGV
GAIN VALUE 9-BIT
MHB728
Fig.7 Gain flow chart.
2000 Nov 27
19
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
ANALOG INPUT ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
0
1
CLL
0
0
SBOT
1
1
WIPE
0
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
fast - GAIN
slow + GAIN
MGC647
WIPE = white peak level (510). SBOT = sync bottom level (1). CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.
Fig.8 Clamp and gain flow chart.
2000 Nov 27
20
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andbook, full pagewidth
2000 Nov 27
CVBS-IN or Y-IN LDEL YCOMB DELAY COMPENSATION CHR QUADRATURE MODULATOR CB-CR LUBW CVBS-IN or CHR-IN QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING SUBCARRIER GENERATION 2 LCBW [ 2:0]
8.1.3 CHROMINANCE AND LUMINANCE PROCESSING
Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
Y SUBTRACTOR
LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT
Y/CVBS DBRI [ 7:0] DCON [ 7:0] DSAT [ 7:0] RAWG [ 7:0] RAWO [ 7:0] COLO
INTERPOLATION LOW-PASS 3 LUFI [ 3:0] CSTD [ 2:0] YDEL [ 2:0] SET_RAW SET_VBI
CB-CR
ADAPTIVE COMB FILTER
CB-CR
LOW-PASS 2
BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL
Y-OUT/ CVBS OUT CB-CR -OUT HREF-OUT
SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS
CHBW
21
CHROMINANCE INCREMENT DELAY LDEL YCOMB CHROMINANCE INCREMENT DTO RESET SUBCARRIER GENERATION 1 SUBCARRIER INCREMENT GENERATION AND DIVIDER HUEC CDTO INCS CSTD [ 2:0] RTCO
SECAM PROCESSING
CB-CR PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER CHROMA GAIN CONTROL
SET_RAW SET_VBI
PAL DELAY LINE CB-CR ADJUSTMENT SECAM RECOMBINATION
FCTC ACGC CGAIN [ 6:0] IDEL [ 3:0]
CODE
SECS
SET_RAW SET_VBI
DCVF
Preliminary specification
MHB729
SAA7118E
fH /2 switch signal
Fig.9 Chrominance and luminance processing.
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.1.3.1 Chrominance path
SAA7118E
The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard. The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCWB3 to LCWB0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0 and 90 FM signals (SECAM). The chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y-comb filter is disabled by YCOMB = 0 the filter influences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 8.3. The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. It's characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-passes 1 and 2 see Figs 10 and 11. The SECAM processing (bypassed for QAM standards) contains the following blocks: * Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90 FM signals * Phase demodulator and differentiator (FM-demodulation) * De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). 2000 Nov 27 22
The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains the following: * Burst gate accumulator * Colour identification and colour killer * Comparison nominal/actual burst amplitude (PAL/NTSC standards only) * Loop filter chrominance gain control (PAL/NTSC standards only) * Loop filter chrominance PLL (only active for PAL/NTSC standards) * PAL/SECAM sequence detection, H/2-switch generation. The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 8.3. The embedded line delay is also used for SECAM recombination (cross-over switches).
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -48 -51 -54 -57 -60 0
(1) (2) (3) (4)
MHB533
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
(5) (6) (7) (8)
Fig.10 Transfer characteristics of the chrominance low-pass at CHBW = 0.
2000 Nov 27
23
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -48 -51 -54 -57 -60 0
(1) (2) (3) (4)
MHB534
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
(5) (6) (7) (8)
Fig.11 Transfer characteristics of the chrominance low-pass at CHBW = 1.
2000 Nov 27
24
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.1.3.2 Luminance path
SAA7118E
The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. It's characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance `notch' without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figs 12 to 15. It should be noted that these frequency curves are only valid for Y-comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard. The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the remodulated chrominance signal.
The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.16. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).
2000 Nov 27
25
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB535
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.12 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0.
2000 Nov 27
26
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000 LCBW[2:0] = 010 LCBW[2:0] = 100 LCBW[2:0] = 110 -51 -54 -57 -60
(1) (2) (3) (4)
MHB536
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001 LCBW[2:0] = 011 LCBW[2:0] = 101 LCBW[2:0] = 111 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.13 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 1.
2000 Nov 27
27
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB537
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.14 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0.
2000 Nov 27
28
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB538
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.15 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1.
2000 Nov 27
29
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
MHB539
9 V (dB) 8
(1) (2)
7 6 5 4 3 (1) (2) (3) (4) (5) (6) (7) (8) LUFI[3:0] = 0001. LUFI[3:0] = 0010. LUFI[3:0] = 0011. LUFI[3:0] = 0100. LUFI[3:0] = 0101. LUFI[3:0] = 0110. LUFI[3:0] = 0111. LUFI[3:0] = 0000. 2 1 0 -1 0 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. -24 -27 -30 -33 -36 -39 0 0.5 1.0 0.5 1.0
(3) (4) (5) (6) (7) (8)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5 f (MHz)
6.0
(9) (10) (11) (12) (13) (14) (15) (16)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5 f (MHz)
6.0
Fig.16 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).
2000 Nov 27
30
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels
SAA7118E
The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions: * Chrominance saturation control by DSAT7 to DSAT0 * Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 * Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 * Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656".
+255 handbook, full pagewidth +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128
colourless CB-COMPONENT
+128
colourless CR-COMPONENT
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MHB730
a. Y output range.
b. CB output range.
c. CR output range.
"ITU Recommendation 601/656" digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H. Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT.
Luminance: DCON Y OUT = Int ---------------- x ( Y - 128 ) + DBRI 68
DSAT Chrominance: ( C R C B ) OUT = Int --------------- x ( C R, C B - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656".
Fig.17 Y-CB-CR range for scaler input and X-port output.
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
+71 +60 SYNC 1
black black shoulder
+60 SYNC
black shoulder = black
sync bottom
1
sync bottom
MGD700
a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).
b. Sources not containing black level offset.
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int ----------------- x ( CVBS nom - 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656".
Fig.18 CVBS (raw data) range for scaler input, data slicer and X-port output.
8.1.4
SYNCHRONIZATION
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO; see Fig.19. The detection of `pseudo syncs' as part of the macrovision copy protection standard is also achieved within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.1.5 CLOCK GENERATION CIRCUIT Table 3 Decoder clock frequencies CLOCK XTALO LLC LLC2 LLC4 (internal) LLC8 (virtual)
SAA7118E
The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: 6.75 MHz = 429 x fH (50 Hz), or 6.75 MHz = 432 x fH (60 Hz). The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor.
FREQUENCY (MHz) 24.576 or 32.110 27 13.5 6.75 3.375
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
MHB330
LLC2
Fig.19 Block diagram of the clock generation circuit.
8.1.6
POWER-ON RESET AND CHIP ENABLE (CE) INPUT
A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.20). The indicator output RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the Chip Enable pin (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
POC V
DDA ANALOG
POC V
DDD DIGITAL
CLOCK PLL LLC CE POC LOGIC RESINT CLK0 POC DELAY RES
CE
XTALO
LLCINT
RESINT
LLC
RES (internal reset)
some ms
20 to 200 s PLL-delay <1 ms
896 LCC digital delay
128 LCC
MHB331
POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output.
Fig.20 Power-on control circuit.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.2 Component video processing
SAA7118E
handbook, full pagewidth
FSW
FSW DELAY
G/Y B/CB R/CR
Y RGB/Y-CB-CR CB MATRIX CR
DOWN FOMATTER and Y BCS and CB-CR COMPONENT DELAY
MIXER
Y to X-port CB-CR
bypass
BCS
Y-CB-CR decoder
MHB731
Fig.21 Component video processing.
8.2.1
RGB-TO-(Y-CB-CR) MATRIX
The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-CB-CR representation. The input and output word widths are 9 bits. The matrix has a gain factor of 1. The block provides a delay compensated bypass for component input signals. The matrix is represented by the following equations: Y = 0.299 x R + 0.587 x G = 0.114 x B CB = 0.5772 x (B - Y) CR = 0.7296 x (R - Y)
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.2.2 DOWNFORMATTER
SAA7118E
The block mainly consists of 2 parts: the colour difference signal downsampler and the Y-path. The colour difference signals are first passed through low-pass filters which reduce alias effects due to the lower data rate. The ITU sampling scheme requires that both colour difference samples fit to the first Y sample of the current time slot. Thus the CR signal is delayed by 1 clock before it is fed to the multiplexer. The switch signal defines the data multiplex phase at the output: a `0' marks the first clock of a time slot, this is a CB sample. The output is fed through a register, so that the multiplexer runs with the opposite phase.
The delay compensation for the Y signal already provides most of the registers required for a small high-pass filter. It can be used to compensate high frequency losses in the analog part. It provides 2 dB gain at 6.75 MHz. The Y high-pass filter frequency response is shown in Fig.24. The DC gain of the filter is 1, so a limiter is required at the filter output. The current implementation clips at the maximum values of 0 and 511. The entire filter can be controlled by the I2C-bus bit CMFI in subaddress 29H.
handbook, full pagewidth
LOW-PASS CR D Q 0 D 1 LOW-PASS CB Q (CR-CB)OUT
switch delay compensation HIGH-PASS Y D n Q YOUT
bypass CMFI
MHB732
Fig.22 Downformatter block diagram.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
MHB788
handbook, halfpage
4
Z (dB) 3
2
1
0
-1
0
2
4
6 f (MHz)
8
Fig.23 CB-CR low-pass filter frequency response.
MHB787
handbook, halfpage
2
Z (dB) 0
-20
-40
-60
0
2
4
6
f (MHz)
8
Fig.24 Y high-pass filter frequency response.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.2.3 COMPONENT VIDEO BCS CONTROL
SAA7118E
The resulting Y and CB-CR signals are fed to the Component BCS (CBCS) block, which contains the following functions: * Chrominance saturation control by CSAT7 to CSAT0 * Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0 * Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656".
+255 handbook, full pagewidth +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128
colourless CB-COMPONENT
+128
colourless CR-COMPONENT
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MHB730
a. Y output range.
b. CB output range.
c. CR output range.
"ITU Recommendation 601/656" digital levels with default CBCS (decoder) settings CCON[7:0] = 44H, CBRI[7:0] = 80H and CSAT[7:0] = 40H. Equations for modification to the Y-CB-CR levels via CBCS control I2C-bus bytes CBRI, CCON and CSAT.
Luminance: CCON Y OUT = Int ---------------- x ( Y - 128 ) + CBRI 68
CSAT Chrominance: ( C B C R ) OUT = Int --------------- x ( C B, C R - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656".
Fig.25 Components Y-CB-CR range.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.3 Decoder output formatter
SAA7118E
The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.5.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 (see also Chapter 15; subaddresses 41H to 57H). Table 4 Data formats at decoder output DATA TYPE teletext EuroWST, CCST European closed caption
For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit D7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 5 to 8.
DATA TYPE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DECODER OUTPUT DATA FORMAT raw raw raw raw raw raw Y-CB-CR 4 : 2 : 2 raw raw raw raw raw raw raw raw Y-CB-CR 4 : 2 : 2
Video Programming Service (VPS) wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region
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Table 5 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 521 259 522 260 523 active video 261 24 262 263 active video 524 525 1 264 2 265 2 3 266 3 4 267 4 5 serration pulses 268 5 269 6 serration pulses 6 7 270 7 8 271 8 9 272 9 equalization pulses equalization pulses equalization pulses equalization pulses
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
Table 6 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 10 273 10 11 274 11 12 275 12 13 276 13 14 277 14 15 278 15 16 279 16 17 280 17 18 281 18 19 282 19 20 283 20 21 284 21 22 285 22 23 286 23 24 287 24 25 288 nominal VBI-lines F1 nominal VBI-lines F2 active video active video
Table 7 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 621 309 622 active video 310 311 24 active video 623 624 312 625 313 1 314 serration pulses 2 2 serration pulses 315 316 3 3 4 317 4 5 318 5 equalization pulses equalization pulses equalization pulses equalization pulses
Table 8 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7])
Preliminary specification
SAA7118E
Line number (1st field) Line number (2nd field) LCR
6 319 6
7 320 7
8 321 8
9 322 9
10 323 10
11 324 11
12 325 12
13 326 13
14 327 14
15 328 15
16 329 16
17 330 17
18 331 18
19 332 19
20 333 20
21 334 21
22 335 22
23 336 23
24 337 24
25 338
nominal VBI-lines F1 nominal VBI-lines F2
active video active video
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
ITU counting single field counting CVBS
622 309
623 310
624 311
625 312
1 1
2 2
3 3
4 4
5 5
6 6
7 7
... ...
22 22
23 23
HREF
F_ITU656
V123 (1) VSTO [8:0] = 134H VGATE
FID
(a) 1st field
VSTA [8:0] = 15H
ITU counting single field counting CVBS
309 309
310 310
311 311
312 312
313 313
314 1
315 2
316 3
317 4
318 5
319 6
... ...
335 22
336 23
HREF
F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE
FID
(b) 2nd field
VSTA [8:0] = 15H
MHB540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME HREF F_ITU656 V123 VGATE FID
RTS0 (PIN M10) X - X X X
RTS1 (PIN N10) X - X X X
XRH (PIN C7) X - - - -
XRV (PIN D8) - X X - -
For further information see Section 15.2: Tables 56, 57 and 58.
Fig.26 Vertical timing diagram for 50 Hz/625 line systems.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
ITU counting single field counting CVBS
525 262
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
... ...
21 21
22 22
HREF
F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE
FID
(a) 1st field
VSTA [8:0] = 011H
ITU counting single field counting CVBS
262 262
263 263
264 1
265 2
266 3
267 4
268 5
269 6
270 7
271 8
272 9
... ...
284 21
285 22
HREF
F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE
FID
(b) 2nd field
VSTA [8:0] = 011H
MHB541
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME HREF F_ITU656 V123 VGATE FID
RTS0 (PIN M10) X - X X X
RTS1 (PIN N10) X - X X X
XRH (PIN C7) X - - - -
XRV (PIN D8) - X X - -
For further information see Section 15.2: Tables 56, 57 and 58.
Fig.27 Vertical timing diagram for 60 Hz/525 line systems.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
CVBS input
burst processing delay ADC to expansion port: 140 x 1/LLC
expansion port data output
sync clipped
HREF (50 Hz) 720 x 2/LLC CREF CREF2 5 x 2/LLC HS (50 Hz) programming range 108 (step size: 8/LLC) 0 2 x 2/LLC -107 12 x 2/LLC 144 x 2/LLC
HREF (60 Hz) 16 x 2/LLC 720 x 2/LLC CREF CREF2 HS (60 Hz) programming range (step size: 8/LLC) 107 0 138 x 2/LLC
1 x 2/LLC 2 x 2/LLC -106
MHB542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 56 and 57); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 58).
Fig.28 Horizontal timing diagram (50/60 Hz).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.4 Scaler
SAA7118E
The High Performance video Scaler (HPS) is based on the system as implemented in the SAA7140, but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process itself. The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. The high performance video scaler in the SAA7118E has the following major blocks: * Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) * Prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format * Brightness, saturation, contrast control for scaled output data * Line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-CR 4 : 2 : 2) * Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscale, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better alias suppression * Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling * Output formatter for scaled Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1 and Y only (format also for raw data) * FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR formats * Output interface, 8 or 16-bit (only if extended by H-port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream.
The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2% for running in and running out, the maximum HV_zoom is equal to: T_input_field - T_v_blanking 0.98 x ------------------------------------------------------------------------------------------------------------------------------------in_pixel x in_lines x out_cycle_per_pix x T_out_clk For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to: 20 ms - 24 x 64 s 0.98 x -------------------------------------------------------- = 1.18 720 x 288 x 2 x 37 ns 2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H-port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms - 22 x 64 s 0.98 x ------------------------------------------------------------- = 2.34 720 x 240 x 1 x 37 ns The video scaler receives its input signal from the video decoder or from the expansion port (X-port). It gets 16-bit Y-CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. Discontinuous data stream can be accepted from the expansion port (X-port), normally 8-bit wide ITU 656 like Y-CB-CR data, accompanied by a pixel qualifier on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time multiplexed chrominance CB and CR samples. An Y-CB-CR 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. The scaler operation is defined by two programming pages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors and signal source during odd and even fields). Each programming page contains control: * For signal source selection and formats * For task handling and trigger conditions * For input and output acquisition window definition * For H-prescaler, V-scaler and H-phase scaling. Raw VBI-data is handled as specific input format and needs its own programming page (equals own task).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, however, the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 8.4.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH AND C4H TO CFH)
SAA7118E
The task handling is controlled by subaddress 90H (see Section 8.4.1.2).
8.4.1.1
Input field processing
The trigger event for the field sequence detection from external signals (X-port) are defined in subaddress 92H. From the X-port the state of the scalers H-reference signal at the time of the V-reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. The bits XFDV[92H[7]] and XFDH[92H[6]] define the detection event and state of the flag from the X-port. For the default setting of XFDV and XFDH at `00' the state of the H-input at the falling edge of the V-input is taken. The scaler directly gets a corresponding field ID information from the SAA7118E decoder path. The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0] 90H[1:0]). According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X-port signals and the internal decoder ID can be changed via XFDH. As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated for by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figs 26 and 27. As the H and V reference events inside the ITU 656 data stream (from X-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.
The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X-port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X-port only qualified pixels and lines (lines with qualified pixel) are counted. The acquisition window parameters are as follows: * Signal source selection regarding input video stream and formats from the decoder, or from X-port (programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0]) Remark: The input of raw VBI-data from the internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 8.3) * Vertical offset defined in lines of the video source, parameter YO[11:0] 99H[3:0] 98H[7:0] * Vertical length defined in lines of the video source, parameter YS[11:0] 9BH[3:0] 9AH[7:0] * Vertical length defined in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0] * Horizontal offset defined in number of pixels of the video source, parameter XO[11:0] 95H[3:0] 94H[7:0] * Horizontal length defined in number of pixels of the video source, parameter XS[11:0] 97H[3:0] 96H[7:0] * Horizontal destination size, defined in target pixels after fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0]. The source start offset (XO11 to XO0 and YO11 to YO0) opens the acquisition window, and the target size (XD11 to XD0, YD11 to YD0) closes the window, but the window is cut vertically, if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 9 Processing trigger and start DESCRIPTION Internal decoder: The processing triggers at the falling edge of the V123 pulse (see Figs 26 (50 Hz) and 27 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number: 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count) 0 0 0 XDV1 92H[5]
SAA7118E
XDV0 92H[4]
XDH 92H[2]
1 0 0
0 0 0
8.4.1.2
Task handling
The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]]. The handler is then triggered by events, which can be defined for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit SWRST[88H[5]] to logic 0. Especially if the programming registers, related acquisition window and scale are reprogrammed while a task is active, a software reset must be performed after programming. Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0 it sets the internal state machines directly to their idle states. The start condition for the handler is defined by bits STRC[1:0] 90H[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached. When RPTSK[90H[2]] is at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90H[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated. Examples are given in Section 8.4.1.3. Remarks: * To activate a task the start condition must be fulfilled and the acquisition window offsets must be reached. 2000 Nov 27 46
For example, in case of `start immediately', and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will `wait for next V'. * Basically the trigger conditions are checked, when a task is activated. It is important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in output field rate of 503 Hz). * After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A.
8.4.1.3
Output field processing
As a reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOOGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn't synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see Section 8.4.3). With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected.
Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it is possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as `task flag' on the pins IGP0 (IGP1), if TASK output is selected. Table 10 Examples for field processing FIELD SEQUENCE FRAME/FIELD SUBJECT EXAMPLE 1(1) 1/1 Processed by task State of detected ITU 656 FID TOGGLE flag Bit D6 of SAV/EAV byte Required sequence conversion at the vertical scaler(8) Output(9) A 0 1 0 UP UP O 1/2 A 1 0 1 LO LO O 2/1 A 0 1 0 UP UP O EXAMPLE 2(2)(3) 1/1 B 0 1 0 UP UP O 1/2 A 1 1 1 LO LO O 2/1 B 0 0 0 UP UP O 2/2 A 1 0 1 LO LO O 1/1 B 0 1 1 UP LO O EXAMPLE 3(2)(4)(5) 1/2 B 1 0 0 LO UP O 2/1 A 0 1 1 UP LO O 2/2 B 1 1 1 LO LO O 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O 1/1 B 0 0(7) 0(7) UP UP NO EXAMPLE 4(2)(4)(6) 1/2 B 1 1 1 LO LO O 2/1 A 0 1 1 UP LO O 2/2 B 1 1(7) 1(7) LO LO NO 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
Notes 1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0. 2. Tasks are used to scale to different output windows, priority on task B after SWRST. 3. Both tasks at 12 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H. 4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. 5. Task B at 23 frame rate constructed from neighbouring motion phases; task A at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H. 6. Task A and B at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H. 7. State of prior field. 8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.
Preliminary specification
9. O = data output; NO = no output.
SAA7118E
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.4.2 HORIZONTAL SCALING
SAA7118E
The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: output pixel H-scale ratio = ----------------------------input pixel 1 1024 H-scale ratio = --------------------------- x -----------------------------XPSC[5:0] XSCY[12:0] where the parameter of prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 13.5 is to split in 14 x 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. Prescaler and fine scaler create the horizontal scaler of the SAA7118E. Using the accumulation length function of the prescaler (XACL[5:0] A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined.
* The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process: - XC2_1 = 0 1 + 1...+ 1 +1 - XC2_1 = 1 1 + 2...+ 2 +1 The prescaler creates a prescale dependent FIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1XPSC[5:0]. The user can therefore decide between signal bandwidth (sharpness impression) and alias. Equation for XPSC[5:0] calculation is: Npix_in XPSC[5:0] = lower integer of ---------------------Npix_out where, the range is 1 to 63 (value 0 is not allowed); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the complete horizontal scaler. The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = [(XACL[5:0] - XC2_1) + 1] x (XC2_1 + 1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain amplification, as these amplitudes can be renormalized by the XDCG[2:0] 1 controlled ------ shifter of the prescaler. N 2 The renormalization range of XDCG[2:0] is 1, 12... down to 1128. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain of 1, e.g. for an accumulation sequence of `1 + 1 + 1' (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to `010', this equals 14 and the BCS has to amplify the signal to 43 (SATN[7:0] and CONT[7:0] value = lower integer of 43 x 64). The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be <2 x XPSC[5:0]. XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects.
8.4.2.1
Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)
The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance sharpness and aliasing effects. The FIR prefilter stage implements different low-pass characteristics to reduce alias for downscales in the range of 1 to 12. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 12 scale); see Table 11. The function of the prescaler is defined by: * An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 163 * An averaging sequence length XACL[5:0] A1H[5:0] (equals 0 to 63); range 1 to 64 * A DC gain renormalization XDCG[2:0] A2H[2:0]; 1 down to 1128
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen different to the previously mentioned equations or Table 12, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to downscale by a factor of 10248191. Figs 31 and 32 show some resulting frequency characteristics of the prescaler. Table 12 shows the recommended prescaler programming. Other programmings, other than given in Table 12, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: 2 CONT[7:0] = SATN[7:0] = lower integer of --------------------------------DC gain x 64 Where: 2XDCG[2:0] DC gain DC gain = (XC2_1 + 1) x XACL[5:0] + (1 - XC2_1). Table 11 FIR prefilter functions PFUV[1:0] A2H[7:6] PFY[1:0] A2H[5:4] 00 01 10 11 LUMINANCE FILTER COEFFICIENTS bypassed 121 -1 1 1.75 4.5 1.75 1 -1 12221
XDCG[2:0]
SAA7118E
For example, if XACL[5:0] = 5, XC2_1 = 1, then the DC gain = 10 and the required XDCG[2:0] = 4. The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance path and chrominance path, but the FIR filter settings can be defined differently in the two channels. Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figs 29 and 30 show the frequency characteristics of the selectable FIR filters.
CHROMINANCE COEFFICIENTS bypassed 121 3 8 10 8 3 12221
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(3) (2) (1)
MHB543
0.45 f_sig/f_clock
0.5
Fig.29 Luminance prefilter characteristic.
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. -39 -42 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2
(2) (3) (1)
MHB544
0.225 0.25 f_sig/f_clock
Fig.30 Chrominance prefilter characteristic.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 XC2_1 = 0; Zero's at 1 f = n x -----------------------XACL + 1 with XACL = (1), (2), (3), (4) or (5) -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(5) (4) (3) (2) (1)
MHB545
0.45 f_sig/f_clock
0.5
Fig.31 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 (1) (2) (3) (4) (5) (6) XC2_1 = 0 and XACL[5:0] = 1. XC2_1 = 1 and XACL[5:0] = 2. XC2_1 = 0 and XACL[5:0] = 3. XC2_1 = 1 and XACL[5:0] = 4. XC2_1 = 0 and XACL[5:0] = 7. XC2_1 = 1 and XACL[5:0] = 8. -33 -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(2) (6) (5) (4) (3)
MHB546
(1)
3 dB at 0.25 6 dB at 0.33
0.45 f_sig/f_clock
0.5
Fig.32 Examples for prescaler filter characteristics: setting XC2_1 =1.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 12 XACL[5:0] example of usage RECOMMENDED VALUES PRESCALE XPSC RATIO [5:0] FOR LOWER BANDWIDTH REQUIREMENTS XACL[5:0] 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 1 1 1 1 1 1 1
SAA7118E
FOR HIGHER BANDWIDTH REQUIREMENTS XACL[5:0] 0 1 3 4 7 7 7 8
(1) 16
FIR PREFILTER PFY (PB-PR) 0 to 2 0 to 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3
XC2_1 0 1 (1 2 1) x
1 (1) 4
XDCG[2:0] 0 2 3
1 (1) 8
XC2_1 0 0 (1 1) x 0
1 (1) 2
XDCG[2:0] 0 1 2
1 2 3 4 5 6 7 8 9 10 13 15 16 19 31 32 35
0 2 4 7 8 8 8 15 15 16 16 31 32 32 32 63 63
1 (1 2 2 2 1) x 0 (1 1 1 1 1 1 1 1) x 18(1) 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 116(1) 0 0 1 1 0 1 1 1 1 1
1 (1) 16 1 (1) 16
(1 1 1 1) x 3 4 4 4 4
1
1 (1) 4
1 (1 2 2 2 1) x 18(1) 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 18(1) 1 1 1 1 1 1 1 1 1 1
1 (1) 8 1 (1) 8
3 3 3 3 4
1 (1) 16
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x
(1 2 2 2 2 2 2 2 1) x 8 8
4 5
1 (1) 32
4 4
1 (1) 16
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x 116(1)
10
(1 2 2 2 2 2 2 2 1) x 116(1) (1 2 2 2 2 2 2 2 1) x 16 16 16 32 32 32 63
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) x
13 15 16 19 31 32 35
5 5 6 6 6 7 7
5 5 5 6 6 6 7
Note 1. Resulting FIR function.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.4.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH) 8.4.3.1
SAA7118E
Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H)
The horizontal fine scaling (VPD) should operate at scaling ratios between 12 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 17.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. In combination with the prescaler a compromise between sharpness impression and alias can be found, which is a signal source and application dependent. For the luminance channel a filter structure with 10 taps is implemented, and for the chrominance a filter with 4 taps. Luminance and chrominance scale increments (XSCY[12:0] A9H[4:0]A8H[7:0] and XSCC[12:0] ADH[4:0]ACH[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 132T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. According to the equations Npix_in 1 XSCY[12:0] = 1024 x --------------------------- x ---------------------- and XPSC[5:0] Npix_out XSCY[12:0] XSCC[12:0] = -----------------------------2 the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture. 8.4.3 VERTICAL SCALING
The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. It has to be preserved by means of the input acquisition window definition, so that the processing starts with a line containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1] 91H[2:1] define the distance between the Y/C lines. In the event of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to `00'. The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone applications (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. The line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port.
The vertical scaler of the SAA7118E consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 164. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate the DC gain amplification of the ACM mode (see Section 8.4.3.2) as the internal RAMs are only 8-bit wide.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.4.3.2 Vertical scaler (subaddresses B0H to BFH and E0H to EFH)
SAA7118E
Vertical scaling of any ratio from 64 (theoretical zoom) to 163 (icon) can be applied. The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and accumulation (ACM) mode. These are controlled by YMODE[B4H[0]]: * LPI mode: In LPI mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to 12), it must be applied for vertical zooming. * ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to 164. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part. The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0] B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start phase covers the range of 25532 to 132 lines offset. By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH) depending on odd/even field ID of the source video stream and A/B-page cycle, frame ID conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). Figs 33 and 34 and Tables 13 and 14 describe the use of the offsets.
Remark: The vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2 output processing. The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are: * Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0] Nline_in = lower integer of 1024 x ------------------------ Nline_out * BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0] Nline_out = lower integer of ------------------------ x 64 , or Nline_in 1024 = lower integer of ------------------------------ x 64 YSCY[15:0]
8.4.3.3
Use of the vertical phase offsets
As described in Section 8.4.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see Fig.33). For correct interlaced processing the vertical scaler must be used with respect to the interlace properties of the input signal and, if required, for conversion of the field sequences. Four events should be considered, they are illustrated in Fig.34.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
unscaled input field 1 field 2
scaled output, no phase offset field 1 field 2
scaled output, with phase offset field 1 field 2
correct scale dependent position
scale dependent start offset
mismatched vertical line distances
MHB547
Fig.33 Basic problem of interlaced vertical scaling (example: downscale 35).
field 1 upper
field 2 lower A
field 1 case UP-UP
field 2 case LO-LO B
field 1 case UP-LO
field 2 case LO-UP
C D
MHB548
1024 Offset = ------------ = 32 = 1 line shift 32 1 1024 Offset = ------------ = 32 = 1 line shift A = -- input line shift = 16 32 2 1 A = 1 input line shift =1 scale increment = YSCY[15:0] + 16 -B = -- input line shift + --16 -----------------------------2 2 2 64
1 YSCY[15:0] C = -- scale increment = -----------------------------2 64 1 D = no input line shift + 1 scale increment = YSCY[15:0] + 16 B = -- offset = 0 ------------------------------2 2 64 1 YSCY[15:0] C = -- scale increment = -----------------------------2 64 D = no offset = 0
Fig.34 Derivation of the phase related equations (example: interlace vertical scaling down to 35, with field conversion).
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
In Tables 13 and 14 PHO is a usable common phase offset. It should be noted that the equations of Fig.34 produce an interpolated output, also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field (see Table 13). If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the 12 line phase shift (PHO + 16) that can be skipped. This case is listed in Table 14. The SAA7118E supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line.
SAA7118E
The registers are assigned to the following events; e.g. subaddresses B8H to BBH: * B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 8.4.1.3) * B9H: 01 = input field ID 0, task status bit 1 * BAH: 10 = input field ID 1, task status bit 0 * BBH: 11 = input field ID 1, task status bit 1. Depending on the input signal (interlaced or non-interlaced) and the task processing 50 Hz or field reduced processing with one or two tasks (see examples in Section 8.4.1.3), other combinations may also be possible, but the basic equations are the same.
Table 13 Examples for vertical phase offset usage: global equations INPUT FIELD UNDER PROCESSING Upper input lines Upper input lines Lower input lines Lower input lines OUTPUT FIELD USED ABBREVIATION INTERPRETATION upper output lines lower output lines upper output lines lower output lines UP-UP UP-LO LO-UP LO-LO EQUATION FOR PHASE OFFSET CALCULATION (DECIMAL VALUES) PHO + 16 YSCY[15:0] PHO + ------------------------------ + 16 64 PHO YSCY[15:0] PHO + -----------------------------64
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 14 Vertical phase offset usage; assignment of the phase offsets DETECTED INPUT FIELD ID 0 = upper lines TASK STATUS BIT 0 VERTICAL PHASE OFFSET YPY0[7:0] and YPC0[7:0] CASE
SAA7118E
EQUATION TO BE USED
case 1(1) UP-UP (PHO) case 2(2) UP-UP case 3(3) UP-LO case 1 case 2 case 3 case 1 UP-UP (PHO) UP-LO UP-UP YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-UP LO-LO YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-LO LO-UP
0 = upper lines
1
YPY1[7:0] and YPC1[7:0]
1 = lower lines
0
YPY2[7:0] and YPC2[7:0]
case 2 case 3 1 = lower lines 1 YPY3[7:0] and YPC3[7:0] case 1
case 2 case 3 Notes
1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines. 2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines. 3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines.
8.5
VBI-data decoder and capture (subaddresses 40H to 7FH)
The SAA7118E contains a versatile VBI-data decoder. The implementation and programming model is in accordance with the VBI-data slicer built into the multimedia video data acquisition circuit SAA5284. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI-data FIFO with a capacity of 2 x 56 bytes (2 x 14 Dwords). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40H. The supported VBI-data standards are shown in Table 15. For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCR24_[7:0] to LCR2_[7:0] in 57H[7:0] to 41H[7:0]: 23 x 2 x 4 bit programming bits).
The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24_[7:0] = FFH) to stop the activity of the VBI-data slicer during active video. To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available: parameters HOFF[10:0] 5BH[2:0] 59H[7:0], VOFF[8:0] 5BH[4] 5AH[7:0] and FOFF[5BH[7]]). Contrary to the scalers counting, the slicers offsets define the position of the H and V trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part. The relationship of these programming values to the input signal and the recommended values can be seen in Tables 5 to 8.
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 15 Data types supported by the data slicer block DT[3:0] 62H[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 US NABTS MOJI (Japanese) no sliced data transmitted (video data selected) 5.7272 5.7272 5 STANDARD TYPE teletext EuroWST, CCST European closed caption VPS wide screen signalling bits US teletext (WST) US closed caption (line 21) (video data selected) (raw data selected) teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) DATA RATE (Mbits/s) 6.9375 0.500 5 5 5.7272 0.503 5 5 6.9375 1.8125 1.7898 FRAMING CODE 27H 001 9951H 1E3C1FH 27H 001 none none programmable programmable programmable reserved programmable programmable none NABTS open disable
SAA7118E
FC WINDOW WST625 CC625 VPS WSS WST525 CC525 disable disable general text VITC625 VITC525
HAM CHECK always
always
optional
optional
programmable (A7H) Japtext
Japanese format switch (L20/22) 5
8.6
Image port output formatter (subaddresses 84H to 87H)
The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information. The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H: * Output field ID * Start and end of vertical active video range * Start and end of active video line * Data qualifier or gated clock * Actually activated programming page (if CONLH is used) * Threshold controlled FIFO filling flags (empty, full, filled) * Sliced data marker. 2000 Nov 27 58
The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I-port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I-port output. The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration. As a further operation the serialization of the internal 32-bit Dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here. For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided (see Section 8.6.2).
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.6.1 SCALER OUTPUT FORMATTER (SUBADDRESSES 93H AND C3H)
SAA7118E
The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1, Y-CB-CR 4 : 2 : 0, Y-CB-CR 4 : 1 : 0, Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0] 93H[4:3] and FYSK[93H[5]]. The data formats are defined on Dwords, or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compares to SAA7146A), but planar formats are not supported. Table 16 Byte stream for different output formats OUTPUT FORMAT Y-CB-CR 4 : 2 : 2 Y-CB-CR 4 : 1 : 1 Y only CB0 CB0 Y0 Y0 Y0 Y1 CR0 CR0 Y2
FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line. Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 18.
BYTE SEQUENCE FOR 8-BIT OUTPUT MODES Y1 Y1 Y3 CB2 CB4 Y4 Y2 Y2 Y5 CR2 CR4 Y6 Y3 Y3 Y7 CB4 Y4 Y8 Y4 Y5 Y9 CR4 Y6 Y10 Y5 Y7 Y11 CB6 CB8 Y12 Y6 Y8 Y13
Table 17 Explanation to Table 16 NAME CBn Yn CRn EXPLANATION CB (B - Y) colour difference component, pixel number n = 0, 2, 4 to 718 Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CR (R - Y) colour difference component, pixel number n = 0, 2, 4 to 718
Table 18 Limiting range on I-port LIMIT STEP ILLV[85H[5]] 0 1 8.6.2 VALID RANGE DECIMAL VALUE 1 to 254 8 to 247 VIDEO FIFO (SUBADDRESS 86H) HEXADECIMAL VALUE 01 to FE 08 to F7 These are: * The FIFO Almost Empty (FAE) flag * The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark * The FIFO Almost Full (FAF) flag * The FIFO Overflow (FOVL) flag. The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16, 8, 4, empty). The state of this flag can be seen on the pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H (see Section 9.6). 59 SUPPRESSED CODES (HEXADECIMAL VALUE) LOWER RANGE 00 00 to 07 UPPER RANGE FF F8 to FF
The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-CB-CR 4 : 2 : 2 format. But as the entire scaler can act as a pipeline buffer, the actual available buffer capacity for the image port is much higher, and can exceed beyond a video line. The image port, and the video FIFO, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous and burst mode), as appropriate for the VGA controller or attached frame buffer. The video FIFO provides 4 internal flags, reporting to what extent the FIFO is actually filled. 2000 Nov 27
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.6.3 TEXT FIFO
SAA7118E
The data of the terminal VBI-data slicer is collected in the text FIFO before the transmission over the I-port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I-port. The decoded VBI-data is collected in the dedicated VBI-data FIFO. After capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, telling line number and standard. The VBI-data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI-data is lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH) or by SAV/EAV codes selectable by DID[5:0] at value 3EH or 3FH. Pin IGP0 or IGP1 is set, if the first byte of the ANC header is valid on the I-port bus. It is reset if an SAV occurs. So it may frame multiple lines of text data output, in case video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I-port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The decoded VBI-data are presented in two different data formats, controlled by bit RECODE. * RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH * RECODE = 0: values 00H and FFH may occur in the data stream as detected. 8.6.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)
If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video. 8.6.5 DATA STREAM CODING AND REFERENCE SIGNAL (SUBADDRESSES 84H, 85H AND 93H)
GENERATION
As H and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H. If ITU 656 like codes are not wanted, they can be suppressed in the output stream. As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I-port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (active). Table 19 shows the relevant and supported SAV and EAV coding.
Sliced text data and scaled video data are transferred over the same bus, the I-port. The mixed transfer is controlled by an arbitration circuit.
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Table 19 SAV/EAV codes on I-port
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
SAV/EAV CODES ON I-PORT(1) (HEX) EVENT DESCRIPTION MSB(2) OF SAV/EAV BYTE = 0 FIELD ID = 0 Next pixel is FIRST pixel of any active line Previous pixel was LAST pixel of any active line, but not the last Next pixel is FIRST pixel of any V-blanking line Previous pixel was LAST pixel of the last active line or of any V-blanking line No valid data, don't capture and don't increment pointer Notes 1. The leading byte sequence is: FFH-00H-00H. 2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A MSB = CONLH[90H[7]]; task B MSB = CONLH[C0H[7]]. b) VBI-data slicer output data: DID[5:0] 5DH[5:0] = 3EH MSB = 1; DID[5:0] 5DH[5:0] = 3FH MSB = 0. 0E 13 25 38 FIELD ID = 1 49 54 62 7F 00 MSB(2) OF SAV/EAV BYTE = 1 FIELD ID = 0 80 9D AB B6 FIELD ID = 1 C7 DA EC F1 HREF = active; VREF = active HREF = inactive; VREF = active HREF = active; VREF = inactive HREF = inactive; VREF = inactive IDQ pin inactive COMMENT
invalid data or end of raw VBI line
timing reference code FF 00 00
internal header IDI1
sliced data IDI2 D1_3 D1_4 D2_1
and filling data
timing reference code BC FF 00 00 EAV
invalid data 00 00
... ...
FF 00
00 00
00 EAV
SAV SDID DC
...
DDC_3 DDC_4 CS
...
MHB549
D1_1 D1_2 ANC header 00 FF FF internal header DID SDID DC IDI1 sliced data IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS BC
ANC data output is only filled up to the Dword boundary 00 00
...
Preliminary specification
ANC header active for DID (subaddress 5DH) <3EH
SAA7118E
Fig.35 Sliced data formats on the I-port in 8-bit mode.
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 20 Explanation to Fig.35 NAME SAV SDID DC start of active data; see Table 21 EXPLANATION
SAA7118E
sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, D5 to D0, e. g. to be used as source identifier Dword count: NEP(1), EP(2), DC5 to DC0. DC describes the number of succeeding 32-bit words: * For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH) * For ANC mode it is: DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. It should be noted that the number of valid bytes inside the stream can be seen in the BC byte.
IDI1 IDI2 Dn_m DDC_4 CS BC EAV Notes
internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 21 internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 21 Dword number n, byte number m last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill value is A0H the check sum byte, the checksum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte number of valid sliced bytes counted from the IDI1 byte end of active data; see Table 21
1. Inverted EP (bit 7); for EP see note 2. 2. Even parity (bit 6) of bits 5 to 0. 3. Odd parity (bit 7) of bits 6 to 0.
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 21 Bytes stream of the data slicer NICK NAME DID, SAV, EAV COMMENT subaddress 5DH = 00H subaddress 5DH; D5 = 1 subaddress 5DH D5 = 3EH; note 5 subaddress 5DH D5 = 3FH; note 5 SDID DC(8) IDI1 IDI2 CS BC Notes 1. NEP = inverted EP (see note 2). 2. EP = Even Parity of bits 5 to 0. 3. FID = 0: field 1; FID = 1: field 2. check sum byte valid byte count programmable via subaddress 5EH D7 NEP(1) NEP 1 0 NEP NEP OP(9) OP CS6 OP D6 EP(2) EP FID(3) FID(3) EP EP(2) FID(3) LN2(10) CS6 0 D5 0 0 V(6) V(6) D4 1 D3 0 D2 FID(3)
SAA7118E
D1 I1(4)
D0 I0(4)
D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH] H(7) H(7) P3 P3 P2 P2 P1 P1 P0 P0
D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH] DC5 LN8(10) LN1(10) CS5 CNT5 DC4 LN7(10) LN0(10) CS4 CNT4 DC3 LN6(10) DT3(11) CS3 CNT3 DC2 LN5(10) DT2(11) CS2 CNT2 DC1 LN4(10) DT1(11) CS1 CNT1 DC0 LN3(10) DT0(11) CS0 CNT0
4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field. 5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value. 6. V = 0: active video; V = 1: blanking. 7. H = 0: start of line; H = 1: end of line. 8. DC = Data Count in Dwords according to the data type. 9. OP = Odd Parity of bits 6 to 0. 10. LN = Line Number. 11. DT = Data Type according to table.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.7 Audio clock generation (subaddresses 30H to 3FH)
SAA7118E
* Audio master Clocks Nominal Increment, ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] according to the equation: audio frequency 23 ACNI[21:0] = round -------------------------------------------- x 2 crystal frequency See Table 22 for examples. Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.
The SAA7118E incorporates the generation of a field-locked audio clock as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. That ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear editing. 8.7.1 MASTER AUDIO CLOCK
The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters: * Audio master Clocks Per Field, ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] according to the equation: audio frequency ACPF[17:0] = round ----------------------------------------- field frequency-
Table 22 Programming examples for audio master clock generation XTALO (MHz) FIELD (Hz) ACPF DECIMAL HEX DECIMAL ACNI HEX
AMCLK = 256 x 48 kHz (12.288 MHz) 32.11 24.576 50 59.94 50 59.94 245760 205005 - - 225792 188348 225792 188348 3C000 320CD - - 37200 2DFBC 37200 2DFBC 3210190 3210190 - - 2949362 2949362 3853517 3853 517 30FBCE 30FBCE - - 2D00F2 2D00F2 3ACCCD 3ACCCD
AMCLK = 256 x 44.1 kHz (11.2896 MHz) 32.11 24.576 50 59.94 50 59.94
AMCLK = 256 x 32 kHz (8.192 MHz) 32.11 24.576 50 59.94 50 59.94 163840 136670 163840 136670 28000 215DE 28000 215DE 2140127 2140127 2796203 2796203 20A7DF 20A7DF 2AAAAB 2AAAAB
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
8.7.2 SIGNALS ASCLK AND ALRCLK
SAA7118E
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the following parameters: * SDIV[5:0] 38H[5:0] according to the equation: f AMXCLK f AMXCLK f ASCLK = ------------------------------------- SDIV[5:0] = ------------------- - 1 ( SDIV + 1 ) x 2 2f ASCLK f ASCLK f ASCLK * LRDIV[5:0] 39H[5:0] according to the equation: f ALRCLK = -------------------------- LRDIV[5:0] = ---------------------LRDIV x 2 2f ALRCLK See Table 23 for examples. Table 23 Programming examples for ASCLK/ALRCLK clock generation AMXCLK (MHz) 12.288 11.2896 8.192 8.7.3 ASCLK (kHz) 1536 768 1411.2 2822.4 1024 2048 SDIV DECIMAL 3 7 3 1 3 1 HEX 03 07 03 01 03 01 ALRCLK (kHz) 48 44.1 32 LRDIV DECIMAL 16 8 16 32 16 32 HEX 10 08 10 10 10 10
OTHER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references: APLL[3AH[3]]; Audio PLL mode: 0: PLL closed 1: PLL open AMVR[3AH[2]]; Audio Master clock Vertical Reference: 0: internal V 1: external V LRPH[3AH[1]]; ALRCLK Phase 0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: don't invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK SCPH[3AH[0]]; ASCLK Phase: 0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: don't invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9 INPUT/OUTPUT INTERFACES AND PORTS
SAA7118E
The SAA7118E has 5 different I/O interfaces: * Analog video input interface, for analog CVBS and/or Y and C input signals and/or component video signals * Audio clock port * Digital real-time signal port (RT port) * Digital video expansion port (X-port), for unscaled digital video input and output * Digital image port (I-port) for scaled video data output and programming * Digital host port (H-port) for extension of the image port or expansion port from 8 to 16-bit. 9.1 Analog terminals
Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed to two ADC channels, one for the video contents, the other for sync conversion. Additionally, there are four differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are no peripheral components required other than these decoupling capacitors and 18 /56 termination resistors, one set per connected input signal (see also application example in Fig.45). Four anti-alias filters are integrated. Clamp and gain control for the four ADCs are also integrated. An analog video output (pin AOUT) is provided for testing purposes.
The SAA7118E has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite video CVBS or S-video Y/C signal pairs or component video input signals RGB plus separate sync (or Y-PB-PR plus separate sync). Table 24 Analog pin description SYMBOL AI11 to AI14 AI21 to AI24 AI31 to AI34 AI41 to AI44 AOUT PIN J2, K1, K2 and L3 G4, G3, H2 and J3 E3, F2, F3 and G1 B1, D2, D1 and E1 M1 O I I/O I DESCRIPTION analog video signal inputs, e.g. 16 CVBS signals or eight Y/C pairs, or four RGB plus separate sync (or Y-PB-PR plus separate sync) signal groups can be connected simultaneously to this device; many combinations are possible; see Figs 48 to 88 analog video output, for test purposes analog reference pins for differential ADC operation; connect to ground via 47 nF BIT MODE5 to MODE0
AOSL2 to AOSL0 -
AI1D, AI2D, K3, H1, F1 and D3 AI3D and AI4D
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9.2 Audio clock signals
SAA7118E
The SAA7118E also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. Table 25 Audio clock pin description SYMBOL PIN I/O AMCLK P11 O DESCRIPTION audio master clock output
An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated; * ASCLK: can be used as audio serial clock * ALRCLK: audio left/right channel clock. The ratios are programmable; see also Section 8.7.
BIT ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] -
AMXCLK
M12
I
external audio master clock input for the clock division circuit, can be directly connected to output AMCLK for standard applications serial audio clock output, can be synchronized to rising or falling edge of AMXCLK audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK
ASCLK ALRCLK
N11 P12
O O
SDIV[5:0] 38H[5:0] and SCPH[3AH[0]] LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
9.3
Clock and real-time synchronization signals
For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built-in for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK). Alternatively pin XTALI can be driven from an external single-ended oscillator. The crystal oscillation can be propagated as a clock to other ICs in the system via pin XTOUT.
The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to "ITU recommendation 601". In order to support interfacing circuits, a direct pixel clock (LLC2) is also provided. The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7118E. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0] 12H[3:0].
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 26 Clock and real-time synchronization signals SYMBOL PIN I/O Crystal oscillator XTALI XTALO XTOUT B4 A3 A2 I O O input for crystal oscillator or reference clock output of crystal oscillator reference (crystal) clock output drive (optional) - - DESCRIPTION
SAA7118E
BIT
XTOUTE[14H[3]] - - -
Real-time signals (RT port) LLC LLC2 RTCO P4 N5 L10 O O O line-locked clock, nominal 27 MHz, double pixel clock locked to the selected video input signal line-locked pixel clock, nominal 13.5 MHz real-time control output, transfers real-time status information supporting RTC level 3.1 (see document "RTC Functional Description", available on request) real-time status information line 0, can be programmed to carry various real-time information (see Table 56) real-time status information line 1, can be programmed to carry various real-time information (see Table 57)
RTS0 RTS1
M10 N10
O O
RTSE0[3:0] 12H[3:0] RTSE1[3:0] 12H[7:4]
9.4 9.4.1
Interrupt handling INTERRUPT FLAGS
PPV: PALplus identification found or lost. CCV: Closed caption identification found or lost.
The pin INT_A is an open-drain output (active LOW). All flags can be independently enabled. For the default setting all flags are disabled after reset. For the description of interrupt mask registers see Section 15.4.
9.4.1.4
Scaler
ERROF: scaler output formatting error detected. 9.4.2 STATUS READING CONDITIONS
9.4.1.1
Power state
PRDON: a power fail has been detected during normal operation, the device needs re-programming.
9.4.1.2
Video decoder
INTL: interlaced/non-interlaced source detected. HLCK: horizontal PLL state changed (locked unlocked). HLVLN: vertical lock state changed (locked unlocked). FIDT: detected field frequency has changed (50 Hz 60 Hz). RDCAP: ready for capture (true false). DCSTD[1:0]: detected colour standard has changed or colour lost. COPRO, COLSTR and TYPE3: various levels of copy protection have changed.
The status information read after an interrupt will always be the LATEST state, that means the status will not be `frozen' when an interrupt is being generated. Therefore, if there is a long time between interrupt generation and status reading, the original trigger condition might have been overridden by the present state. 9.4.3 ERASING CONDITIONS
The status flags are grouped into four 8-bit registers. The interrupt flag will only be cleared on a read access to the status register in which the signal is located which caused the interrupt. This implies that it is sufficient to clear the interrupt by reading only those registers which have been enabled by their corresponding masks. Priority: If a new trigger condition occurs at the SAME time (clock) on which a status is being read, the flag will NOT be cleared.
9.4.1.3
VBI data slicer
VPSV: VPS identification found or lost. 2000 Nov 27 68
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9.5 Video expansion port (X-port)
SAA7118E
As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields only.
The expansion port is intended for transporting video streams image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I-port). The expansion port consists of two groups of signals/pins: * 8-bit data, I/O, regularly components video Y-CB-CR 4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0. * Clock, synchronization and auxiliary signals, accompanying the data stream, I/O. Table 27 Signals dedicated to the expansion port SYMBOL XPD7 to XPD0 PIN I/O
DESCRIPTION
BIT
OFTS[2:0] 13H[2:0], 91H[7:0] C11, A11, I/O X-port data: in output mode controlled by decoder and C1H[7:0] B10, A10, section, data format see Table 28; in input mode B9, A9, Y-CB-CR 4 : 2 : 2 serial input data or luminance part of a 16-bit Y-CB-CR 4 : 2 : 2 input B8 and A8 A7 I/O clock at expansion port: if output, then copy of LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualifier) XCKS[92H[0]]
XCLK
XDQ
B7
I/O data valid flag of the expansion port input (qualifier): - if output, then decoder (HREF and VGATE) gate (see Fig.28) O data request flag = ready to receive, to work with XRQT[83H[2]] optional buffer in external device, to prevent internal buffer overflow; second function: input related task flag A/B
XRDY
A6
XRH
C7
I/O horizontal reference signal for the X-port: as output: XRHS[13H[6]], XFDH[92H[6]] and HREF or HS from the decoder (see Fig.28); as XDH[92H[2]] input: a reference edge for horizontal input timing and a polarity for input field ID detection can be defined I/O vertical reference signal for the X-port: as output: V123 or field ID from the decoder, see Figs 26 and 27; as input: a reference edge for vertical input timing and for input field ID detection can be defined I port control: switches X-port input 3-state XRVS[1:0] 13H[5:4], XFDV[92H[7]] and XDV[1:0] 92H[5:4]
XRV
D8
XTRI
B11
XPE[1:0] 83H[1:0]
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9.5.1 X-PORT CONFIGURED AS OUTPUT
SAA7118E
If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see Table 4. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected. Some details of data types on the expansion port are as follows: * Active video (data type 15): contains component Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.17. * Test line (data type 6): is similar to the active video format, with some constraints within the data processing: - adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled - adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing. This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. For nominal levels see Fig.17. * Raw samples (data types 0 to 5 and 7 to 14): CB-CR samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. Table 28 Data format on the expansion port BLANKING PERIOD ... 80 TIMING REFERENCE CODE (HEX)(1)
The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0; see Chapter 15, Tables 63 and 64. For nominal levels see Fig.18. The relationship of LCR programming to line numbers is described in Section 8.3, see Tables 5 to 8. The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly intended for device production test. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13H[1:0] settings; see Table 58. The output configuration is done via MODE[5:0] 02H[5:0] settings; see Table 40. If a Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, and in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode. Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 56. The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence `- 80 - 10 - 80 - 10 -...' is transmitted during the horizontal blanking period between EAV and SAV. The position of the F-bit is constant in accordance with ITU 656; see Tables 30 and 31. The V-bit can be generated in two different ways (see Tables 30 and 31) controlled via OFTS1 and OFTS0; see Table 58. The F and V bits change synchronously with the EAV code.
720 PIXELS Y-CB-CR 4 : 2 : 2 DATA(2)
TIMING REFERENCE CODE (HEX)(1)
BLANKING PERIOD 10 ...
10 FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80
Notes 1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to `010', see Table 58. In this event the code sequence is replaced by the standard `- 80 - 10 -' blanking values. 2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples. 2000 Nov 27 70
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 29 SAV/EAV format on expansion port XPD7 to XPD0 BIT 7 1 field bit 1st field: F = 0 2nd field: F = 1 BIT 6 (F) BIT 5 (V) vertical blanking bit VBI: V = 1 active video: V = 0 format H = 0 in SAV format H = 1 in EAV format BIT 4 (H)
SAA7118E
BIT 3 BIT 2 BIT 1 BIT 0 (P3) (P2) (P1) (P0) reserved; evaluation not recommended (protection bits according to ITU 656)
for vertical timing see Tables 30 and 31 Table 30 525 lines/60 Hz vertical timing V LINE NUMBER 1 to 3 4 to 19 20 21 22 to 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 OFTS[2:0] = 001 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 60 to 62
Table 31 625 lines/50 Hz vertical timing V LINE NUMBER 1 to 22 23 24 to 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 OFTS[1:0] = 10 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 60 to 62
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9.5.2 X-PORT CONFIGURED AS INPUT
SAA7118E
If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91H[2:0]). The input stream must be accompanied by an external clock (XCLK), qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656 are also accepted. The protection bits are not evaluated. XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV1[92H[5]]). The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0] 92H[5:4] and XDH[92H[2]]. The signal polarity of the qualifier can also be defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified. As the VBI data slicer may have different requirements for its input reference signals from X-port XRV, XRH, XDQ, XCLK and XPD7 to XPD0, a second set of parameters is available for defining the meaning of the X-port input signals and polarities for the VBI data slicer input path. These bits are defined in subaddresses 81H and 82H. 9.6 Image port (I-port)
The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures. However the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes. Available formats are as follows: * Y-CB-CR 4 : 2 : 2 * Y-CB-CR 4 : 1 : 1 * Raw samples * Decoded VBI-data. For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on these pins is controlled via subaddresses 84H and 85H. VBI-data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded VBI-data can be signed by the VBI flag on pin IGP0 or IGP1. As scaled video data and decoded VBI-data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI-data slicer has priority. The image port consists of the pins and/or signals, as listed in Table 32. For pin constrained applications, or interfaces, the relevant timing and data reference signals can also get encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible.
The image port transfers data from the scaler as well as from the VBI-data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as an output, or as an input (maximum 33 MHz). As output, ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80H[2]]).
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
The following deviations from "ITU 656 recommendation" are implemented at the SAA7118Es image port interface: * SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines * There may be more or less than 720 pixels between SAV and EAV * Data content and the number of clock cycles during horizontal and vertical blanking is undefined, and may not be constant * Data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes * There may be an irregular pattern of not-valid data, or IDQ, and as a result, CB-Y-CR-Y is not in a fixed phase to a regular clock divider * VBI raw sample streams are enveloped with SAV and EAV, like normal video Table 32 Signals dedicated to the image port SYMBOL IPD7 to IPD0 PIN I/O DESCRIPTION
SAA7118E
* Decoded VBI-data is transported as Ancillary (ANC) data, two modes: - direct decoded VBI-data bytes (8-bit) are directly placed in the ANC data field, 00H and FFH codes may appear in data block (violation to ITU-R BT.656) - recoded VBI-data bytes (8-bit) directly placed in ANC data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid ITU-R BT.656 codes. There are no empty cycles in the ancillary code and its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). Optionally, the number range can be further limited.
BIT ICODE[93H[7]], ISWP[1:0] 85H[7:6] and IPE[1:0] 87H[1:0]
K11, J13, I/O I-port data J14, H13, H14, H11, G12 and G14 M14 I/O continuous reference clock at image port, can be input or output, as output decoder LLC or XCLK from X-port O data valid flag at image port, qualifier, with programmable polarity; secondary function: gated clock horizontal reference output signal, copy of the H-gate signal of the scaler, with programmable polarity; alternative function: HRESET pulse vertical reference output signal, copy of the V-gate signal of the scaler, with programmable polarity; alternative function: VRESET pulse general purpose output signal for I-port general purpose output signal for I-port target ready input signals port control, switches I-port into 3-state
ICLK
ICKS[1:0] 80H[1:0] and IPE[1:0] 87H[1:0] ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0] 87H[1:0] IDH[1:0] 84H[1:0], IRHP[85H[1]] and IPE[1:0] 87H[1:0] IDV[1:0] 84H[3:2], IRVP[85H[2]] and IPE[1:0] 87H[1:0] IDG12[86H[4]], IDG1[1:0] 84H[5:4], IG1P[85H[3]] and IPE[1:0] 87H[1:0] IDG02[86H[5]], IDG0[1:0] 84H[7:6], IG0P[85H[4]] and IPE[1:0] 87H[1:0] - IPE[1:0] 87H[1:0]
IDQ
L13
IGPH
K12
O
IGPV
K14
O
IGP1 IGP0 ITRDY ITRI
K13 L14 N12 L12
O O I I
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
9.7 Host port for 16-bit extension of video data I/O (H-port)
SAA7118E
The H-port pins HPD can be used for extension of the data I/O paths to 16-bit. The I-port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled depending on the I-port enable control. For I8_16 = 0, the HPD output is disabled. Table 33 Signals dedicated to the host port SYMBOL HPD7 to HPD0 PIN G13, F14, F13, E14, E12, E13, E11 and D14 I/O I/O DESCRIPTION 16-bit extension for digital I/O (chrominance component) 9.8.2 BIT IPE[1:0] 87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]]
9.8 9.8.1
Basic input and output timing diagrams I-port and X-port I-PORT OUTPUT TIMING
X-PORT INPUT TIMING
At the X-port the input timing requirements are the same as those for the I-port output. But different to those below: * It is not necessary to mark invalid cycles with a 00H code * No constraints on the input qualifier (can be a random pattern) * XCLK may be a gated clock (XCLK AND external XDQ). Remark: All timings illustrated in Figs 36 to 42 are given for an uninterrupted output stream (no handshake with the external hardware).
The following diagrams illustrate the output timing via the I-port. IGPH and IGPV are logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code 00H. The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).
ICLK
IDQ
IPD [ 7:0 ]
00
FF
00
00
SAV
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB550
Fig.36 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB551
Fig.37 Output timing I-port for serial 8-bit data at start of a line (ICODE = 0).
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
FF
00
00
EAV
00
IGPH
MHB552
Fig.38 Output timing I-port for serial 8-bit data at end of a line (ICODE = 1).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB553
Fig.39 Output timing I-port for serial 8-bit data at end of a line (ICODE = 0).
ICLK
IDQ
IPD [ 7:0 ]
00
FF
00
00
Y0
Y1
00
Y2
Y3
Yn - 1
Yn
00
FF
00
00
HPD [ 7:0 ]
00
00
SAV
00
CB
CR
00
CB
CR
CB
CR
00
00
EAV
00
IGPH
MHB554
Fig.40 Output timing for 16-bit data output via I-port and H-port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
IDQ
IGPH
IGPV
MHB555
Fig.41 H-gate and V-gate output timing.
handbook, full pagewidth
ICLK
IDQ
IPD [ 7:0 ]
00
00
FF
FF
DID
SDID
XX
YY
ZZ
CS
BC
00
00
00
HPD [ 7:0 ]
00
FF
00
00
SAV
BC
FF
00
00
EAV
sliced data flag on IGP0 or IGP1
MHB733
Fig.42 Output timing for sliced VBI-data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
10 BOUNDARY SCAN TEST The SAA7118E has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7118E follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 34). Details about the JTAG BST-TEST can be found in specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7118E is available on request. Table 34 BST instructions supported by the SAA7118E INSTRUCTION BYPASS DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. INSTRUCTION IDCODE
SAA7118E
DESCRIPTION This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no customer support available). This private instruction allows testing by the manufacturer (no customer support available).
INTEST
USER1
10.1
Initialization of boundary scan circuit
The TAP (Test Access Port) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 10.2 Device identification codes
EXTEST
SAMPLE
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.43.
CLAMP
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, full pagewidth
MSB 31 TDI 28 27 0111000100011000 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1
LSB 0 1 TDO
nnnn
4-bit version code
MHB734
Fig.43 32 bits of identification code.
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and all supply pins connected together. SYMBOL VDDD VDDA VIA VOA VID VOD VSS Tstg Tamb Tamb(bias) Vesd Notes 1. Maximum 4.6 V. 2. Except pin XTALI. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 37.5 UNIT K/W PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs output voltage at analog output input voltage at digital inputs and outputs output voltage at digital outputs voltage difference between VSSAn and VSSDn storage temperature ambient temperature ambient temperature under bias electrostatic discharge voltage at all pins note 3 outputs in 3-state; note 2 outputs active CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - -65 0 -10 -2000 MAX. +4.6 +4.6 VDDA + +5.5 VDDD + 0.5 100 +150 70 +80 +2000 0.5(1) VDDA + 0.5 V V V V V V mV C C C V UNIT
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
13 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Fig.44; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA digital supply voltage digital supply current power dissipation digital part analog supply voltage analog supply current AOSL1 and AOSL0 = 0 CVBS mode Y/C mode component mode PA power dissipation analog part CVBS mode Y/C mode component mode Ptot(A+D) total power dissipation analog and digital part CVBS mode Y/C mode component mode - - - - - - - - - - 75 130 250 248 430 825 533 710 1105 5 - - - - - - - - 1350 - mA mA mA mW mW mW mW mW mW mW X-port 3-state; 8-bit I-port 3.0 - - 3.1 3.3 85 280 3.3 3.6 - - 3.5 V mA mW V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ptot(A+D)(pd)
total power CE pulled down to ground dissipation analog and digital part in power-down mode total power dissipation analog and digital part in power-save mode
Ptot(A+D)(ps)
I2C-bus controlled via subaddress - 88H = 0FH
75
-
mW
Analog part Iclamp Vi(p-p) clamping current input voltage (peak-to-peak value) input impedance input capacitance channel crosstalk fi < 5 MHz VI = 1 V DC for normal video levels 1 V (p-p), -3 dB termination 18/56 and AC coupling required; coupling capacitor is 47 nF clamping current off - - 8 0.7 - - A V
Zi Ci cs
200 - -
- - -
- 10 -50
k pF dB
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PARAMETER at -3 dB amplifier plus anti-alias filter bypassed amplifier plus anti-alias filter bypassed CONDITIONS - - - 25.4 - - maximum deviation - 1 x 100 ; ------------------------------------------------- minimum deviation note 1 Digital inputs VIL(SCL,SDA) LOW-level input voltage pins SDA and SCL HIGH-level input voltage pins SDA and SCL LOW-level CMOS input voltage pin XTALI HIGH-level CMOS input voltage pin XTALI LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current I/O leakage current input capacitance I/O at high-impedance note 2 -0.5 - - MIN. TYP. - - -
SAA7118E
MAX.
UNIT
9-bit analog-to-digital converters B diff Gdiff fclk(ADC) LEdc(d) LEdc(i) GADC analog bandwidth differential phase differential gain ADC clock frequency DC differential linearity error DC integral linearity error ADC gain inequality 7 2 2 - 0.7 1 3 MHz deg % MHz LSB LSB %
28.6 - - -
+0.3VDD(I2C)
V
VIH(SCL,SDA)
note 2
0.7VDD(I2C) -
VDD(I2C) + 0.5 V
VIL(XTALI)
-0.3
-
+0.8
V
VIH(XTALI)
2.0
-
VDDD + 0.3
V
VIL(n)
-0.3
-
+0.8
V
VIH(n)
2.0
-
5.5
V
ILI ILI/O Ci
- - -
- - -
1 10 8
A A pF
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PARAMETER CONDITIONS - -0.5 2.4 0 MIN. - - - - TYP.
SAA7118E
MAX.
UNIT
Digital outputs; note 3 VOL(SDA) VOL(clk) VOH(clk) VOL(n) LOW-level output voltage pin SDA LOW-level output voltage for clocks HIGH-level output voltage for clocks LOW-level output voltage all other digital outputs HIGH-level output voltage all other digital outputs SDA at 3 mA sink current 0.4 +0.6 VDDD + 0.5 0.4 V V V V
VOH(n)
2.4
-
VDDD + 0.5
V
Clock output timing (LLC and LLC2); note 4 CL Tcy output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time LLC and LLC2 fall time LLC and LLC2 delay time between LLC and LLC2 output pin LLC pin LLC2 CL = 40 pF 15 35 70 40 - - - - 50 39 78 60 pF ns ns %
tr tf td(LLC-LLC2)
0.2 V to VDDD - 0.2 V VDDD - 0.2 V to 0.2 V measured at 1.5 V; CL = 25 pF
- - -4
- - -
5 5 +8
ns ns ns
Horizontal PLL fhor(n) fhor/fhor(n) nominal line frequency permissible static deviation 50 Hz field 60 Hz field - - - 15625 15734 - - - 5.7 Hz Hz %
Subcarrier PLL fsc(n) nominal subcarrier PAL BGHI frequency NTSC M PAL M PAL N fsc lock-in range - - - - 400 4433619 - 3579545 - 3575612 - 3582056 - - - Hz Hz Hz Hz Hz
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PARAMETER CONDITIONS - - MIN. TYP. -
SAA7118E
MAX.
UNIT
Crystal oscillator for 32.11 MHz; note 5 fxtal(nom) fxtal(nom) nominal frequency 3rd harmonic permissible nominal frequency deviation permissible nominal frequency deviation with temperature 32.11 - MHz 70 x 10-6
fxtal(nom)(T)
-
-
30 x 10-6
CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - - - 40 70 - 80 C pF fF pF
1.5 20% - 4.3 20% -
Crystal oscillator for 24.576 MHz; note 5 fxtal(n) fxtal(n) nominal frequency 3rd harmonic permissible nominal frequency deviation permissible nominal frequency deviation with temperature - - 24.576 - - 50 x 10-6 MHz
fxtal(n)(T)
-
-
20 x 10-6
CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - - - 40 70 - 80 C pF fF pF
1.5 20% - 3.5 20% -
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PARAMETER CONDITIONS MIN. - 50 - - 10 3 TYP.
SAA7118E
MAX.
UNIT
Clock input timing (XCLK) Tcy tr tf tSU;DAT tHD;DAT cycle time duty factors for tLLCH/tLLC rise time fall time 31 40 - - - - 45 60 5 5 - - ns % ns ns
Data and control signal input timing X-port, related to XCLK input input data set-up time input data hold time ns ns
Clock output timing CL Tcy tr tf output load capacitance cycle time duty factors for tXCLKH/tXCLKL rise time fall time 0.6 to 2.6 V 2.6 to 0.6 V 15 35 35 - - - - - - - 50 39 65 5 5 pF ns % ns ns
Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default); note 4 CL tOHD;DAT tPD output load capacitance output data hold time CL = 15 pF 15 - - - 14 24 50 - - pF ns ns
propagation delay CL = 15 pF from positive edge of XCLK output
Control signal output timing RT port, related to LLC output CL tOHD;DAT tPD output load capacitance output hold time CL = 15 pF propagation delay CL = 15 pF from positive edge of LLC output 15 - - - 14 24 50 - - pF ns ns
2000 Nov 27
84
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - TYP.
SAA7118E
MAX.
UNIT
ICLK output timing CL Tcy tr tf CL output load capacitance cycle time duty factors for tICLKH/tICLKL rise time fall time 0.6 to 2.6 V 2.6 to 0.6 V 15 31 35 - - 15 50 45 65 5 5 pF ns % ns ns
Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default) output load capacitance at all outputs output data hold time output delay time CL = 15 pF CL = 15 pF 50 pF
tOHD;DAT to(d) Tcy Notes
- - 31
12 22 -
- - 100
ns ns
ICLK input timing cycle time ns
1. ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4. 2. VDD(I2C) is the supply voltage of the I2C-bus. For VDD(I2C) = 3.3 V is VIL(SCL,SDA)(max) = 1 V; for VDD(I2C) = 5 V is VIL(SCL,SDA)(max) = 1.5 V. For VDD(I2C) = 3.3 V is VIH(SCL,SDA)(min) = 2.3 V; for VDD(I2C) = 5 V is VIH(SCL,SDA)(min) = 3.5 V. 3. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 4. The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to drawings and conditions illustrated in Fig.44. 5. The crystal oscillator drive level is typical 0.28 mW.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, full pagewidth
Tcy t XCLKH 2.4 V clock input XCLK 1.5 V 0.6 V t SU;DAT t HD;DAT tf tr
data and control inputs (X port)
2.0 V not valid 0.8 V t SU;DAT t HD;DAT 2.0 V
input XDQ 0.8 V t o(d) t OHD;DAT data and control outputs X port, I port -2.4 V -0.6 V t X(I)CLKH clock outputs LLC, LLC2, XCLK, ICLK and ICLK input t X(I)CLKL -2.6 V -1.5 V -0.6 V tf tr
MHB735
Fig.44 Data input/output timing diagram (X-port, RT port and I-port).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
14 APPLICATION INFORMATION
SAA7118E
handbook, full pagewidth
VDDD 680
VDDD or VSSD for crystal strapping TEST1 to TEST19 4.7 k AMCLK
VDDD VDDD or VSSD for I2C-bus slave address strapping
150 pF
BAT83
FB
680 75
t
BF840
boundary scan(1) TRST TDO TDI A5 FSW B5 C6
4.7 k audio clock I2C-bus port SCL INT_A CE N9 P9 N4 RES P5 L10 N10 M10 N5 P4 B11 D8 C7 A6 B7
AMXCLK TCK TMS B6 D6 A12, M12 A13, B2, B12, B13, B14, C3, C4, C12, C13, C14, D13, N1, N2, N3, N13, N14, P2, P13 P11
ALRCLK ASCLK SDA P12 N11 P10
4.7 k
DGND 18 (3x) CVBS1 CVBS2 S 56 (3x) 18 (4x) VSB1 VSB2 G YS 56 (4x) 18 (4x) Y1 Y2 B PB 56 (4x) 18 (4x) C1 C2 R PR 56 (4x) 47 nF AI11 AI12 AI13 AI14 AI1D AGND AI21 AI22 AI23 AI24 AI2D
M13 J2 K1 K2 L3 K3 C2 G4 G3 H2 J3 H1
RTCO RTS1 RTS0 LLC2 LLC XTRI XRV XRH XRDY XDQ expansion port AD port scaled image port host port real-time
XCLK A7 XPD[7:0] C11, A11, B10, A10, B9, A9, B8, A8 G13, F14, F13, E14, E12, E13, E11, D14 L12 K13 L14 K14 K12 N12 L13 HPD[7:0] ITRI IGP1 IGP0 IGPV IGPH ITRDY IDQ
AI31 AI32 AI33 AI34 AI3D AGNDA AI41 AI42 AI43 AI44 AI4D
E3 F2 F3 G1 F1 L2 B1 D2 D1 E1 D3 M2, J4, H3, E4, C1 M3, K4, H4, F4, D4 D7, D10, F11, J11, L5, L9
SAA7118E
EXMCLR AOUT AOUT
P3 M1
L1, J1, G2, E2
C8, C10, F12, J12, M5, M9
D5, D9, D11, G11, L4, L8, L11
C5, C9, D12, H12, M4, M8, M11
ICLK M14 K11, J13, J14, H13, IPD[7:0] H14, H11, G12, G14 CLKEXT N6 P6, M6, L6, N7, P7, ADP[8:0] L7, M7, P8, N8 A4 VSS(xtal) B3 VDD(xtal) A2 A3 B4
AGND VDDA VDDD
VSSA0 VDDA0 VDDA1A VSSD2 VSSD4 to to to VSSA4 VDDA4 VDDA4A V SSD6 VSSD8 VSSD10 VSSD12 DGND
VDDD2 VDDD4 VDDD6 VDDD8 VDDD10 VDDD12 DGND
VSSD1 VSSD3 VSSD5 VSSD7 VSSD9 VSSD11 VSSD13
VDDD1 VDDD3 VDDD5 VDDD7 VDDD9 VDDD11 VDDD13 DGND
XTALO XTALI
XTOUT
24.576 MHz (3rd harmonic)
10 H 10 F DGND 10 F AGND 2.2 H 100 nF AGND 100 nF 0 100 nF 100 nF 100 nF 100 nF 100 nF DGND 100 nF 10 pF 10 pF
MHB736
1 nF
(1) For board design without boundary scan implementation this pin should be connected to ground.
Fig.45 Application example with 24.576 MHz crystal.
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87
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, full pagewidth
SAA7118E
B4 XTALI 32.11 MHz A3 XTALO B4
SAA7118E
A3 XTALO 32.11 MHz B4 XTALI
SAA7118E
A3 XTALO 32.11 MHz XTALI
4.7 H 1 nF
15 pF
15 pF
33 pF
33 pF
10 pF
10 pF
MHB781
(1a) With 3rd harmonic quartz. Crystal load = 8 pF.
(1b) With fundamental quartz. Crystal load = 20 pF.
(1c) With fundamental quartz. Crystal load = 8 pF
handbook, full pagewidth
SAA7118E
B4 XTALI 24.576 MHz A3 XTALO B4
SAA7118E
A3 XTALO 24.576 MHz B4 XTALI
SAA7118E
A3 XTALO 24.576 MHz XTALI
4.7 H 1 nF
18 pF
18 pF
39 pF
39 pF
15 pF
15 pF
MHB784
(2a) With 3rd harmonic quartz. Crystal load = 8 pF.
(2b) With fundamental quartz. Crystal load = 20 pF.
(2c) With fundamental quartz. Crystal load = 8 pF.
handbook, full pagewidth
SAA7118E
B4 XTALI 32.11 MHz or 24.576 MHz n.c. clock A3 XTALO B4
SAA7118E
A3 XTALO Rs XTALI
MHB786
(3a) With direct clock.
(3b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high a resistance Rs can be placed in series with the output of the oscillator XTALO. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.
Fig.46 Oscillator application.
2000 Nov 27
88
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15 I2C-BUS DESCRIPTION
SAA7118E
The SAA7118E supports the `fast mode' I2C-bus specification extension (data rate up to 400 kbits/s). 15.1 I2C-bus format
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
DATA data transferred (n bytes + acknowledge)
ACK-s
P
MHB339
a. Write procedure.
S Sr
SLAVE ADDRESS W SLAVE ADDRESS R
ACK-s ACK-s
SUBADDRESS DATA
ACK-s ACK-m P
data transferred (n bytes + acknowledge)
MHB340
b. Read procedure (combined).
Fig.47 I2C-bus format.
Table 35 Description of I2C-bus format CODE S Sr SLAVE ADDRESS W SLAVE ADDRESS R ACK-s ACK-m SUBADDRESS DATA P X Note 1. If pin RTCO strapped to ground via a 3.3 k resistor. START condition repeated START condition `0100 0010' (42H, default) or `0100 0000' (40H; note 1) `0100 0011' (43H, default) or `0100 0001' (41H; note 1) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Tables 36 and 37 data byte; see Table 37; if more than one byte DATA is transmitted the subaddress pointer is automatically incremented STOP condition read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) DESCRIPTION
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 36 Subaddress description and access SUBADDRESS 00H F0H to FFH chip version reserved DESCRIPTION
SAA7118E
ACCESS (READ/WRITE) read only - read and write read and write - read only - read and write - read and write - read only - read and write read and write read and write
Video decoder: 01H to 2FH 01H to 05H 06H to 19H 1AH to 1EH 1FH 20H to 2FH front-end part decoder part reserved video decoder status byte reserved
Audio clock generation: 30H to 3FH 30H to 3AH 3BH to 3FH audio clock generator reserved
General purpose VBI-data slicer: 40H to 7FH 40H to 5EH 5FH 60H to 62H 63H to 7FH VBI-data slicer reserved VBI-data slicer status reserved
X-port, I-port and the scaler: 80H to EFH 80H to 8FH 90H to BFH C0H to EFH task independent global settings task A definition task B definition
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90
Table 37 I2C-bus receiver/transmitter overview
2000 Nov 27 91
Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
REGISTER FUNCTION Chip version: register 00H Chip version (read only)
SUB ADDR. (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
00
ID7
ID6
ID5
ID4
-
-
-
-
Video decoder: registers 01H to 1FH FRONT-END PART: REGISTERS 01H TO 05H Increment delay Analog input control 1 Analog input control 2 Analog input control 3 Analog input control 4 01 02 03 04 05
(1)
WPOFF FUSE0 HLNRS GAI16 GAI26
GUDL1 MODE5 VBSL GAI15 GAI25
GUDL0 MODE4 CPOFF GAI14 GAI24
IDEL3 MODE3 HOLDG GAI13 GAI23
IDEL2 MODE2 GAFIX GAI12 GAI22
IDEL1 MODE1 GAI28 GAI11 GAI21
IDEL0 MODE0 GAI18 GAI10 GAI20
FUSE1
(1)
GAI17 GAI27
DECODER PART: REGISTERS 06H TO 1FH Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness control Luminance contrast control Chrominance saturation control Chrominance hue control Chrominance control 1 Chrominance gain control Chrominance control 2 Mode/delay control RT signal control RT/X-port output control Analog/ADC/compatibility control VGATE start, FID change VGATE stop 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 HSB7 HSS7 AUFD BYPS DBRI7 DCON7 DSAT7 HUEC7 CDTO ACGC OFFU1 COLO RTSE13 RTCE CM99 VSTA7 VSTO7 HSB6 HSS6 FSEL YCOMB DBRI6 DCON6 DSAT6 HUEC6 CSTD2 CGAIN6 OFFU0 RTP1 RTSE12 XRHS UPTCV VSTA6 VSTO6 HSB5 HSS5 FOET LDEL DBRI5 DCON5 DSAT5 HUEC5 CSTD1 CGAIN5 OFFV1 HDEL1 RTSE11 XRVS1 AOSL1 VSTA5 VSTO5 HSB4 HSS4 HTC1 LUBW DBRI4 DCON4 DSAT4 HUEC4 CSTD0 CGAIN4 OFFV0 HDEL0 RTSE10 XRVS0 AOSL0 VSTA4 VSTO4 HSB3 HSS3 HTC0 LUFI3 DBRI3 DCON3 DSAT3 HUEC3 DCVF CGAIN3 CHBW RTP0 RTSE03 HLSEL XTOUTE VSTA3 VSTO3 HSB2 HSS2 HPLL LUFI2 DBRI2 DCON2 DSAT2 HUEC2 FCTC CGAIN2 LCBW2 YDEL2 RTSE02 OFTS2 AUTO1 VSTA2 VSTO2 HSB1 HSS1 VNOI1 LUFI1 DBRI1 DCON1 DSAT1 HUEC1 AUTO0 CGAIN1 LCBW1 YDEL1 RTSE01 OFTS1 APCK1 VSTA1 VSTO1 HSB0 HSS0 VNOI0 LUFI0 DBRI0 DCON0 DSAT0 HUEC0 CCOMB CGAIN0 LCBW0 YDEL0
Preliminary specification
RTSE00 OFTS0 APCK0 VSTA0 VSTO0
SAA7118E
2000 Nov 27 92
Philips Semiconductors
REGISTER FUNCTION Miscellaneous, VGATE configuration and MSBs Raw data gain control Raw data offset control Reserved Status byte 1 video decoder (read only) Status byte 2 video decoder (read only)
SUB ADDR. (HEX) 17 18 19 1A to 1D 1E 1F
Multistandard video decoder with adaptive comb filter and component video input
D7 LLCE RAWG7 RAWO7
(1)
D6 LLC2E RAWG6 RAWO6
(1)
D5 LATY2 RAWG5 RAWO5
(1)
D4 LATY1 RAWG4 RAWO4
(1)
D3 LATY0 RAWG3 RAWO3
(1)
D2 VGPS RAWG2 RAWO2
(1)
D1 VSTO8 RAWG1 RAWO1
(1)
D0 VSTA8 RAWG0 RAWO0
(1)
- INTL
HLCK HLVLN
SLTCA FIDT
GLIMT -
GLIMB TYPE3
WIPA COLSTR
DCSTD1 COPRO
DCSTD0 RDCAP
Component processing and interrupt masking part: registers 20H to 2FH Reserved Analog input control 5 Analog input control 6 Analog input control 7 Reserved Component delay Component brightness control Component contrast control Component saturation control Interrupt mask 1 Interrupt mask 2 Interrupt mask 3 20 to 22 23 24 25 26 to 28 29 2A 2B 2C 2D 2E 2F
(1) (1) (1) (1) (1) (1) (1) (1) (1)
AOSL2 GAI37 GAI47
(1)
ADPE GAI36 GAI46
(1)
EXCLK GAI35 GAI45
(1)
REFA GAI34 GAI44
(1)
EXMCE GAI32 GAI42
(1)
GAI48 GAI31 GAI41
(1)
GAI38 GAI30 GAI40
(1)
GAI33 GAI43
(1)
FSWE CBRI7 CCON7 CSAT7
(1) (1)
FSWI CBRI6 CCON6 CSAT6
(1)
FSWDL1 CBRI5 CCON5 CSAT5
(1) (1)
FSWDL0 CBRI4 CCON4 CSAT4 MVPSV
(1) (1)
CMFI CBRI3 CCON3 CSAT3 MPPV
(1)
CPDL2 CBRI2 CCON2 CSAT2 MCCV
(1)
CPDL1 CBRI1 CCON1 CSAT1
(1)
CPDL0 CBRI0 CCON0 CSAT0 MERROF MRDCAP
MHLCK MHLVLN
MDCSTD1 MDCSTD0 MCOPRO
MINTL
MFIDT
MTYPE3
MCOLSTR
Audio clock generator part: registers 30H to 3FH Audio master clock cycles per field 30 31 32 Reserved Audio master clock nominal increment 33 34 35 36 ACPF7 ACPF15
(1) (1)
ACPF6 ACPF14
(1) (1)
ACPF5 ACPF13
(1) (1)
ACPF4 ACPF12
(1) (1)
ACPF3 ACPF11
(1) (1)
ACPF2 ACPF10
(1) (1)
ACPF1 ACPF9 ACPF17
(1)
ACPF0 Preliminary specification ACPF8 ACPF16
(1)
SAA7118E
ACNI7 ACNI15
(1)
ACNI6 ACNI14
(1)
ACNI5 ACNI13 ACNI21
ACNI4 ACNI12 ACNI20
ACNI3 ACNI11 ACNI19
ACNI2 ACNI10 ACNI18
ACNI1 ACNI9 ACNI17
ACNI0 ACNI8 ACNI16
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Philips Semiconductors
REGISTER FUNCTION Reserved Clock ratio AMXCLK to ASCLK Clock ratio ASCLK to ALRCLK Audio clock generator basic setup Reserved
SUB ADDR. (HEX) 37 38 39 3A 3B to 3F
Multistandard video decoder with adaptive comb filter and component video input
D7
(1) (1) (1) (1)
D6
(1) (1) (1) (1)
D5
(1)
D4
(1)
D3
(1)
D2
(1)
D1
(1)
D0
(1)
SDIV5 LRDIV5
(1)
SDIV4 LRDIV4
(1)
SDIV3 LRDIV3 APLL
(1)
SDIV2 LRDIV2 AMVR
(1)
SDIV1 LRDIV1 LRPH
(1)
SDIV0 LRDIV0 SCPH
(1)
(1)
(1)
(1)
(1)
General purpose VBI-data slicer part: registers 40H to 7FH Slicer control 1 LCR2 to LCR24 (n = 2 to 24) Programmable framing code Horizontal offset for slicer Vertical offset for slicer Field offset and MSBs for horizontal and vertical offset Reserved (for testing) Header and data identification (DID) code control Sliced data identification (SDID) code Reserved Slicer status byte 0 (read only) Slicer status byte 1 (read only) Slicer status byte 2 (read only) Reserved 40 41 to 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 to 7F
(1)
HAM_N LCRn_6 FC6 HOFF6 VOFF6 RECODE
(1) (1)
FCE LCRn_5 FC5 HOFF5 VOFF5
(1)
HUNT_N LCRn_4 FC4 HOFF4 VOFF4 VOFF8
(1)
(1)
(1)
(1)
(1)
LCRn_7 FC7 HOFF7 VOFF7 FOFF
(1)
LCRn_3 FC3 HOFF3 VOFF3
(1)
LCRn_2 FC2 HOFF2 VOFF2 HOFF10
(1)
LCRn_1 FC1 HOFF1 VOFF1 HOFF9
(1)
LCRn_0 FC0 HOFF0 VOFF0 HOFF8
(1)
(1)
(1)
FVREF
(1)
DID5 SDID5
(1)
DID4 SDID4
(1)
DID3 SDID3
(1)
DID2 SDID2
(1)
DID1 SDID1
(1)
DID0 SDID0
(1)
(1)
(1)
(1)
- - LN3
(1)
FC8V - LN2
(1)
FC7V F21_N LN1
(1)
VPSV LN8 LN0
(1)
PPV LN7 DT3
(1)
CCV LN6 DT2
(1)
- LN5 DT1
(1)
- LN4 DT0
(1)
X-port, I-port and the scaler part: registers 80H to EFH TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH Global control 1 Reserved X-port I/O enable and output clock phase control 80 81 and 82 83
(1) (1)
Preliminary specification
SAA7118E
SMOD
(1)
TEB
(1)
TEA
(1)
ICKS3
(1)
ICKS2
(1)
ICKS1
(1)
ICKS0
(1)
(1)
(1)
XPCK1
XPCK0
(1)
XRQT
XPE1
XPE0
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Philips Semiconductors
REGISTER FUNCTION I-port signal definitions I-port signal polarities I-port FIFO flag control and arbitration I-port I/O enable, output clock and gated clock phase control Power save/ADC-port control Reserved Status information scaler part
SUB ADDR. (HEX) 84 85 86 87 88 89 to 8E 8F
Multistandard video decoder with adaptive comb filter and component video input
D7 IDG01 ISWP1 VITX1 IPCK3 DOSL1
(1)
D6 IDG00 ISWP0 VITX0 IPCK2 DOSL0
(1)
D5 IDG11 ILLV IDG02 IPCK1 SWRST
(1)
D4 IDG10 IG0P IDG12 IPCK0 DPROG
(1)
D3 IDV1 IG1P FFL1
(1)
D2 IDV0 IRVP FFL0
(1)
D1 IDH1 IRHP FEL1 IPE1 SLM1
(1)
D0 IDH0 IDQP FEL0 IPE0 SLM0
(1)
SLM3
(1)
(1) (1)
XTRI
ITRI
FFIL
FFOV
PRDON
ERROF
FIDSCI
FIDSCO
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window definition
Task handling control X-port formats and configuration X-port input reference signal definition I-port output formats and configuration Horizontal input window start Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F CONLH CONLV XFDV ICODE XO7
(1)
OFIDC HLDFV XFDH I8_16 XO6
(1)
FSKP2 SCSRC1 XDV1 FYSK XO5
(1)
FSKP1 SCSRC0 XDV0 FOI1 XO4
(1)
FSKP0 SCRQE XCODE FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11 YD3 YD11
RPTSK FSC2 XDH FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10 YD2 YD10
STRC1 FSC1 XDQ FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9 YD1 YD9
STRC0 FSC0 XCKS FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0
XS7
(1)
XS6
(1)
XS5
(1)
XS4
(1)
YO7
(1)
YO6
(1)
YO5
(1)
YO4
(1)
YS7
(1)
YS6
(1)
YS5
(1)
YS4
(1)
Preliminary specification
YS8 XD0 XD8 YD0 YD8
XD7
(1)
XD6
(1)
XD5
(1)
XD4
(1)
SAA7118E
YD7
(1)
YD6
(1)
YD5
(1)
YD4
(1)
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Philips Semiconductors
REGISTER FUNCTION
SUB ADDR. (HEX)
Multistandard video decoder with adaptive comb filter and component video input
D7
D6
D5
D4
D3
D2
D1
D0
FIR filtering and prescaling
Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness control Luminance contrast control Chrominance saturation control Reserved A0 A1 A2 A3 A4 A5 A6 A7
(1) (1) (1) (1)
XPSC5 XACL5 PFY1
(1)
XPSC4 XACL4 PFY0
(1)
XPSC3 XACL3 XC2_1
(1)
XPSC2 XACL2 XDCG2
(1)
XPSC1 XACL1 XDCG1
(1)
XPSC0 XACL0 XDCG0
(1)
PFUV1
(1)
PFUV0
(1)
BRIG7 CONT7 SATN7
(1)
BRIG6 CONT6 SATN6
(1)
BRIG5 CONT5 SATN5
(1)
BRIG4 CONT4 SATN4
(1)
BRIG3 CONT3 SATN3
(1)
BRIG2 CONT2 SATN2
(1)
BRIG1 CONT1 SATN1
(1)
BRIG0 CONT0 SATN0
(1)
Horizontal phase scaling
Horizontal luminance scaling increment Horizontal luminance phase offset Reserved Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved A8 A9 AA AB AC AD AE AF XSCY7
(1)
XSCY6
(1)
XSCY5
(1)
XSCY4 XSCY12 XPHY4
(1)
XSCY3 XSCY11 XPHY3
(1)
XSCY2 XSCY10 XPHY2
(1)
XSCY1 XSCY9 XPHY1
(1)
XSCY0 XSCY8 XPHY0
(1)
XPHY7
(1)
XPHY6
(1)
XPHY5
(1)
XSCC7
(1)
XSCC6
(1)
XSCC5
(1)
XSCC4 XSCC12 XPHC4
(1)
XSCC3 XSCC11 XPHC3
(1)
XSCC2 XSCC10 XPHC2
(1)
XSCC1 XSCC9 XPHC1
(1)
XSCC0 XSCC8 XPHC0
(1)
XPHC7
(1)
XPHC6
(1)
XPHC5
(1)
Vertical scaling
Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved Vertical chrominance phase offset `00' B0 B1 B2 B3 B4 B5 to B7 B8 YSCY7 YSCY15 YSCC7 YSCC15
(1) (1)
YSCY6 YSCY14 YSCC6 YSCC14
(1) (1)
YSCY5 YSCY13 YSCC5 YSCC13
(1) (1)
YSCY4 YSCY12 YSCC4 YSCC12 YMIR
(1)
YSCY3 YSCY11 YSCC3 YSCC11
(1) (1)
YSCY2 YSCY10 YSCC2 YSCC10
(1) (1)
YSCY1 YSCY9 YSCC1 YSCC9
(1) (1)
YSCY0 YSCY8 YSCC0 YSCC8 YMODE
(1)
Preliminary specification
SAA7118E
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
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Philips Semiconductors
REGISTER FUNCTION Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' Vertical luminance phase offset `01' Vertical luminance phase offset `10' Vertical luminance phase offset `11'
SUB ADDR. (HEX) B9 BA BB BC BD BE BF
Multistandard video decoder with adaptive comb filter and component video input
D7 YPC17 YPC27 YPC37 YPY07 YPY17 YPY27 YPY37
D6 YPC16 YPC26 YPC36 YPY06 YPY16 YPY26 YPY36
D5 YPC15 YPC25 YPC35 YPY05 YPY15 YPY25 YPY35
D4 YPC14 YPC24 YPC34 YPY04 YPY14 YPY24 YPY34
D3 YPC13 YPC23 YPC33 YPY03 YPY13 YPY23 YPY33
D2 YPC12 YPC22 YPC32 YPY02 YPY12 YPY22 YPY32
D1 YPC11 YPC21 YPC31 YPY01 YPY11 YPY21 YPY31
D0 YPC10 YPC20 YPC30 YPY00 YPY10 YPY20 YPY30
TASK B DEFINITION REGISTERS C0H TO EFH
Basic settings and acquisition window definition
Task handling control X-port formats and configuration Input reference signal definition I-port formats and configuration Horizontal input window start Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CONLH CONLV XFDV ICODE XO7
(1)
OFIDC HLDFV XFDH I8_16 XO6
(1)
FSKP2 SCSRC1 XDV1 FYSK XO5
(1)
FSKP1 SCSRC0 XDV0 FOI1 XO4
(1)
FSKP0 SCRQE XCODE FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11
RPTSK FSC2 XDH FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10
STRC1 FSC1 XDQ FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9
STRC0 FSC0 XCKS FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0 YS8 XD0 XD8
XS7
(1)
XS6
(1)
XS5
(1)
XS4
(1)
YO7
(1)
YO6
(1)
YO5
(1)
YO4
(1)
Preliminary specification
YS7
(1)
YS6
(1)
YS5
(1)
YS4
(1)
SAA7118E
XD7
(1)
XD6
(1)
XD5
(1)
XD4
(1)
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Philips Semiconductors
REGISTER FUNCTION Vertical output window length
SUB ADDR. (HEX) CE CF
Multistandard video decoder with adaptive comb filter and component video input
D7 YD7
(1)
D6 YD6
(1)
D5 YD5
(1)
D4 YD4
(1)
D3 YD3 YD11
D2 YD2 YD10
D1 YD1 YD9
D0 YD0 YD8
FIR filtering and prescaling
Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness control Luminance contrast control Chrominance saturation control Reserved D0 D1 D2 D3 D4 D5 D6 D7
(1) (1) (1) (1)
XPSC5 XACL5 PFY1
(1)
XPSC4 XACL4 PFY0
(1)
XPSC3 XACL3 XC2_1
(1)
XPSC2 XACL2 XDCG2
(1)
XPSC1 XACL1 XDCG1
(1)
XPSC0 XACL0 XDCG0
(1)
PFUV1
(1)
PFUV0
(1)
BRIG7 CONT7 SATN7
(1)
BRIG6 CONT6 SATN6
(1)
BRIG5 CONT5 SATN5
(1)
BRIG4 CONT4 SATN4
(1)
BRIG3 CONT3 SATN3
(1)
BRIG2 CONT2 SATN2
(1)
BRIG1 CONT1 SATN1
(1)
BRIG0 CONT0 SATN0
(1)
Horizontal phase scaling
Horizontal luminance scaling increment Horizontal luminance phase offset Reserved Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved D8 D9 DA DB DC DD DE DF XSCY7
(1)
XSCY6
(1)
XSCY5
(1)
XSCY4 XSCY12 XPHY4
(1)
XSCY3 XSCY11 XPHY3
(1)
XSCY2 XSCY10 XPHY2
(1)
XSCY1 XSCY9 XPHY1
(1)
XSCY0 XSCY8 XPHY0
(1)
XPHY7
(1)
XPHY6
(1)
XPHY5
(1)
XSCC7
(1)
XSCC6
(1)
XSCC5
(1)
XSCC4 XSCC12 XPHC4
(1)
XSCC3 XSCC11 XPHC3
(1)
XSCC2 XSCC10 XPHC2
(1)
XSCC1 XSCC9 XPHC1
(1)
XSCC0 XSCC8 XPHC0
(1)
XPHC7
(1)
XPHC6
(1)
XPHC5
(1)
Vertical scaling
Preliminary specification Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved E0 E1 E2 E3 E4 E5 to E7 YSCY7 YSCY15 YSCC7 YSCC15
(1) (1)
YSCY6 YSCY14 YSCC6 YSCC14
(1) (1)
YSCY5 YSCY13 YSCC5 YSCC13
(1) (1)
YSCY4 YSCY12 YSCC4 YSCC12 YMIR
(1)
YSCY3 YSCY11 YSCC3 YSCC11
(1) (1)
YSCY2 YSCY10 YSCC2 YSCC10
(1) (1)
YSCY1 YSCY9 YSCC1 YSCC9
(1) (1)
YSCY0 YSCY8 YSCC0 YSCC8 YMODE
(1)
SAA7118E
2000 Nov 27 98
Philips Semiconductors
REGISTER FUNCTION Vertical chrominance phase offset `00' Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' Vertical luminance phase offset `01' Vertical luminance phase offset `10' Vertical luminance phase offset `11' Note
SUB ADDR. (HEX) E8 E9 EA EB EC ED EE EF
Multistandard video decoder with adaptive comb filter and component video input
D7 YPC07 YPC17 YPC27 YPC37 YPY07 YPY17 YPY27 YPY37
D6 YPC06 YPC16 YPC26 YPC36 YPY06 YPY16 YPY26 YPY36
D5 YPC05 YPC15 YPC25 YPC35 YPY05 YPY15 YPY25 YPY35
D4 YPC04 YPC14 YPC24 YPC34 YPY04 YPY14 YPY24 YPY34
D3 YPC03 YPC13 YPC23 YPC33 YPY03 YPY13 YPY23 YPY33
D2 YPC02 YPC12 YPC22 YPC32 YPY02 YPY12 YPY22 YPY32
D1 YPC01 YPC11 YPC21 YPC31 YPY01 YPY11 YPY21 YPY31
D0 YPC00 YPC10 YPC20 YPC30 YPY00 YPY10 YPY20 YPY30
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
Preliminary specification
SAA7118E
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2 15.2.1 I2C-bus details SUBADDRESS 00H
SAA7118E
Table 38 Chip Version (CV) identification; 00H[7:4]; read only register LOGIC LEVELS FUNCTION ID7 Chip Version (CV) 15.2.2 SUBADDRESS 01H CV3 ID6 CV2 ID5 CV1 ID4 CV0
The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. Table 39 Horizontal increment delay; 01H[6:0] BIT D6 DESCRIPTION white peak control off SYMBOL WPOFF(1) VALUE 0 FUNCTION white peak control active (AD signal is attenuated, if nominal luminance output white level is exceeded) white peak control disabled off 1 LSB 2 LSB 3 LSB no update minimum delay recommended position maximum delay
1 D[5:4] update hysteresis for 9-bit gain (see Fig.7) GUDL[1:0] 00 01 10 11 D[3:0] increment delay IDEL[3:0] 1111 1110 0111 0000 Note 1. HLNRS = 1 should not be used in combination with WPOFF = 0.
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.3 SUBADDRESS 02H
SAA7118E
Table 40 Analog input control 1 (AICO1); 02H[7:0] BIT DESCRIPTION SYMBOL FUSE[1:0] VALUE 00 01 10 11 CVBS modes 1 D[5:0] mode selection MODE[5:0] 000000 000001 000010 000011 000100 000101 Y + C modes 1 D[5:0] mode selection MODE[5:0] 000110 Mode 06: Y (automatic gain) from AI11 (pin J2) + C (gain adjustable via GAI28 to GAI20) from AI21 (pin G4); note 1; see Fig.54 Mode 07: Y (automatic gain) from AI12 (pin K1) + C (gain adjustable via GAI28 to GAI20) from AI22 (pin G3); note 1; see Fig.55 Mode 08: Y (automatic gain) from AI11 (pin J2) + C (gain adapted to Y gain) from AI21 (pin G4); note 1; see Fig.56 Mode 09: Y (automatic gain) from AI12 (pin K1) + C (gain adapted to Y gain) from AI22 (pin G3); note 1; see Fig.57 Mode 0A: Y (automatic gain) from AI13 (pin K2) + C (gain adjustable via GAI28 to GAI20) from AI23 (pin H2); note 1; see Fig.58 Mode 0B: Y (automatic gain) from AI14 (pin L3) + C (gain adjustable via GAI28 to GAI20) from AI24 (pin J3); note 1; see Fig.59 Mode 0C: Y (automatic gain) from AI13 (pin K2) + C (gain adapted to Y gain) from AI23 (pin H2); note 1; see Fig.60 Mode 0D: Y (automatic gain) from AI14 (pin L3) + C (gain adapted to Y gain) from AI24 (pin J3); note 1; see Fig.61 Mode 00: CVBS (automatic gain) from AI11 (pin J2); see Fig.48 Mode 01: CVBS (automatic gain) from AI12 (pin K1); see Fig.49 Mode 02: CVBS (automatic gain) from AI21 (pin G4); see Fig.50 Mode 03: CVBS (automatic gain) from AI22 (pin G3); see Fig.51 Mode 04: CVBS (automatic gain) from AI23 (pin H2); see Fig.52 Mode 05: CVBS (automatic gain) from AI24 (pin J3); see Fig.53 amplifier active amplifier plus anti-alias filter active FUNCTION amplifier plus anti-alias filter bypassed
D[7:6] analog function select; see Figs 3 and 6
000111
001000 001001 001010
001011
001100 001101
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
BIT DESCRIPTION SYMBOL VALUE FUNCTION
SAA7118E
CVBS modes 2 D[5:0] mode selection MODE[5:0] 001110 001111 010000 010001 010010 010011 010100 010101 Y + C modes 2 D[5:0] mode selection MODE[5:0] 010110 Mode 16: Y (automatic gain) from AI31 (pin E3) + C (gain adjustable via GAI28 to GAI20) from AI41 (pin B1); note 1; see Fig.70 Mode 17: Y (automatic gain) from AI32 (pin F2) + C (gain adjustable via GAI28 to GAI20) from AI42 (pin D2); note 1; see Fig.71 Mode 18: Y (automatic gain) from AI31 (pin E3) + C (gain adapted to Y gain) from AI41 (pin B1); note 1; see Fig.72 Mode 19: Y (automatic gain) from AI32 (pin F2) + C (gain adapted to Y gain) from AI42 (pin D2); note 1; see Fig.73 Mode 1A: Y (automatic gain) from AI33 (pin F3) + C (gain adjustable via GAI28 to GAI20) from AI43 (pin D1); note 1; see Fig.74 Mode 1B: Y (automatic gain) from AI34 (pin G1) + C (gain adjustable via GAI28 to GAI20) from AI44 (pin E1); note 1; see Fig.75 Mode 1C: Y (automatic gain) from AI33 (pin F3) + C (gain adapted to Y gain) from AI43 (pin D1); note 1; see Fig.76 Mode 1D: Y (automatic gain) from AI34 (pin G1) + C (gain adapted to Y gain) from AI44 (pin E1); note 1; see Fig.77 Mode 0E: CVBS (automatic gain) from AI13 (pin K2); see Fig.62 Mode 0F: CVBS (automatic gain) from AI14 (pin L3); see Fig.63 Mode 10: CVBS (automatic gain) from AI31 (pin E3); see Fig.64 Mode 11: CVBS (automatic gain) from AI32 (pin F2); see Fig.65 Mode 12: CVBS (automatic gain) from AI41 (pin B1); see Fig.66 Mode 13: CVBS (automatic gain) from AI42 (pin D2); see Fig.67 Mode 14: CVBS (automatic gain) from AI43 (pin D1); see Fig.68 Mode 15: CVBS (automatic gain) from AI44 (pin E1); see Fig.69
010111
011000 011001 011010
011011
011100 011101 CVBS modes 3 D[5:0] mode selection MODE[5:0] 011110 011111
Mode 1E: CVBS (automatic gain) from AI33 (pin F3); see Fig.78 Mode 1F: CVBS (automatic gain) from AI34 (pin G1); see Fig.79
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
BIT DESCRIPTION SYMBOL VALUE FUNCTION
SAA7118E
Y-PB-PR modes D[5:0] mode selection MODE[5:0] 100000 Mode 20: SY-PB-PR (automatic gain for sync channel only) from AI11, AI21, AI31, AI41 (pins J2, G4, E3, B1); see Fig.80 Mode 21: SY-PB-PR (automatic gain for sync channel only) from AI12, AI22, AI32, AI42 (pins K1, G3, F2, D2); see Fig.81 Mode 2E: SY-PB-PR (automatic gain for sync channel only) from AI13, AI23, AI33, AI43 (pins K2, H2, F3, D1); see Fig.82 Mode 2F: SY-PB-PR (automatic gain for sync channel only) from AI14, AI24, AI34, AI44 (pins L3, J3, G1, E1); see Fig.83
100001
100010 to 101101 reserved 101110
101110
RGB modes D[5:0] mode selection MODE[5:0] 110000 Mode 30: SRGB (automatic gain for sync channel only) from AI11, AI21, AI31, AI41 (pins J2, G4, E3, B1); see Fig.84 Mode 31: SRGB (automatic gain for sync channel only) from AI12, AI22, AI32, AI42 (pins K1, G3, F2, D2); see Fig.85 Mode 3E: SRGB (automatic gain for sync channel only) from AI13, AI23, AI33, AI43 (pins K2, H2, F3, D1); see Fig.86 Mode 3F: SRGB (automatic gain for sync channel only) from AI14, AI24, AI34, AI44 (pins L3, J3, G1, E1); see Fig.87
110001
110010 to 111101 reserved 111110
111111
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
BIT DESCRIPTION SYMBOL VALUE FUNCTION
SAA7118E
VSB modes; see Fig.88 D[5:0] mode selection MODE[5:0] 000000 000001 001110 001111 000010 000011 000100 000101 010000 010001 011110 011111 010010 010011 010100 010101 Note 1. To take full advantage of the Y/C-modes 06 to 1D and 16 to 1D the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Mode 00: input AI11 (pin J2); REFA = 1, DOSL = 0, GAFIX = 1 Mode 01: input AI12 (pin K1); REFA = 1, DOSL = 0, GAFIX = 1 Mode 0E: input AI13 (pin K2); REFA = 1, DOSL = 0, GAFIX = 1 Mode 0F: input AI14 (pin L3); REFA = 1, DOSL = 0, GAFIX = 1 Mode 02: input AI21 (pin G4); REFA = 1, DOSL = 1, GAFIX = 1 Mode 03: input AI22 (pin G3); REFA = 1, DOSL = 1, GAFIX = 1 Mode 04: input AI23 (pin H2); REFA = 1, DOSL = 1, GAFIX = 1 Mode 05: input AI24 (pin J3); REFA = 1, DOSL = 1, GAFIX = 1 Mode 10: input AI31 (pin E3); REFA = 1, DOSL = 2, GAFIX = 1 Mode 11: input AI32 (pin F2); REFA = 1, DOSL = 2, GAFIX = 1 Mode 1E: input AI33 (pin F3); REFA = 1, DOSL = 2, GAFIX = 1 Mode 1F: input AI34 (pin G1); REFA = 1, DOSL = 2, GAFIX = 1 Mode 12: input AI41 (pin B1); REFA = 1, DOSL = 3, GAFIX = 1 Mode 13: input AI42 (pin D2); REFA = 1, DOSL = 3, GAFIX = 1 Mode 14: input AI43 (pin D1); REFA = 1, DOSL = 3, GAFIX = 1 Mode 15: input AI44 (pin E1); REFA = 1, DOSL = 3, GAFIX = 1
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB738
AD4 MUX
R
MHB739
Fig.48 MODE00 CVBS1.
Fig.49 MODE01 CVBS2.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB740
AD4 MUX
R
MHB741
Fig.50 MODE02 CVBS3.
Fig.51 MODE03 CVBS4.
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB742
AD4 MUX
R
MHB743
Fig.52 MODE04 CVBS5.
Fig.53 MODE05 CVBS6.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB744
AD4 MUX
R
MHB745
Fig.54 MODE06 YC1 (gain -> GAI2 level).
Fig.55 MODE07 YC2 (gain -> GAI2 level).
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB746
AD4 MUX
R
MHB747
Fig.56 MODE08 YC1 (gain adapted to Y gain).
Fig.57 MODE09 YC2 (gain adapted to Y gain).
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB748
AD4 MUX
R
MHB749
Fig.58 MODE0A YC3 (gain -> GAI2 level).
Fig.59 MODE0B YC4 (gain -> GAI2 level).
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB750
AD4 MUX
R
MHB751
Fig.60 MODE0C YC3 (gain adapted to Y gain).
Fig.61 MODE0D YC4 (gain adapted to Y gain).
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB752
AD4 MUX
R
MHB753
Fig.62 MODE0E CVBS7.
Fig.63 MODE0F CVBS8.
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB754
AD4 MUX
R
MHB755
Fig.64 MODE10 CVBS9.
Fig.65 MODE11 CVBS10.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB756
AD4 MUX
R
MHB757
Fig.66 MODE12 CVBS11.
Fig.67 MODE13 CVBS12.
2000 Nov 27
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB758
AD4 MUX
R
MHB759
Fig.68 MODE14 CVBS13.
Fig.69 MODE15 CVBS14.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB760
AD4 MUX
R
MHB761
Fig.70 MODE16 YC5 (gain -> GAI2 level).
Fig.71 MODE17 YC6 (gain -> GAI2 level).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB762
AD4 MUX
R
MHB763
Fig.72 MODE18 YC5 (gain adapted to Y gain).
Fig.73 MODE19 YC6 (gain adapted to Y gain).
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB764
AD4 MUX
R
MHB765
Fig.74 MODE1A YC7 (gain -> GAI2 level).
Fig.75 MODE1B YC8 (gain -> GAI2 level).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB766
AD4 MUX
R
MHB767
Fig.76 MODE1C YC7 (gain adapted to Y gain).
Fig.77 MODE1D YC8 (gain adapted to Y gain).
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
LUMA
CHROMA AD2
CHROMA AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB768
AD4 MUX
R
MHB769
Fig.78 MODE1E CVBS15.
Fig.79 MODE1F CVBS16.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
(CHROMA) AD2
(CHROMA) AD2
Y AD3 CB
Y AD3 CB
AD4 MUX
CR
MHB770
AD4 MUX
CR
MHB771
Fig.80 MODE20 SY-PB-PR1.
Fig.81 MODE21 SY-PB-PR2.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
(CHROMA) AD2
(CHROMA) AD2
Y AD3 CB
Y AD3 CB
AD4 MUX
CR
MHB772
AD4 MUX
CR
MHB773
Fig.82 MODE2E SY-PB-PR3.
Fig.83 MODE2F SY-PB-PR4.
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
(CHROMA) AD2
(CHROMA) AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB774
AD4 MUX
R
MHB775
Fig.84 MODE30 SRGB1.
Fig.85 MODE31 SRGB2.
handbook, halfpage AI11
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
SYNC (LUMA)
(CHROMA) AD2
(CHROMA) AD2
G AD3 B
G AD3 B
AD4 MUX
R
MHB776
AD4 MUX
R
MHB777
Fig.86 MODE3E SRGB3.
Fig.87 MODE3F SRGB4.
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113
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
handbook, halfpage AI11
AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44
AD1
ADP [8:0]
AD2
AD3
AD4 MUX
DOSL [1:0]
MHB778
Fig.88 VSB MODES (use CVBS modes with REFA = 1, DOSL = 0 to 3 and GAFIX = 1).
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.4 SUBADDRESS 03H
SAA7118E
Table 41 Analog input control 2 (AICO2); 03H[6:0] BIT DESCRIPTION SYMBOL VALUE HLNRS(1) VBSL 0 1 D5 AGC hold during vertical blanking period 0 1 FUNCTION normal clamping if decoder is in unlocked state reference select if decoder is in unlocked state short vertical blanking (AGC disabled during equalization and serration pulses); recommended setting long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) colour peak control active (AD signal is attenuated, if maximum input level is exceeded, avoids clipping effects on screen) colour peak off AGC active AGC integration hold (freeze) automatic gain controlled by MODE5 to MODE0 gain is user programmable via GAI[17:10] and GAI[27:20] see Table 43 see Table 42
D6 HL not reference select
D4 colour peak off
CPOFF(1)
0
1 D3 automatic gain control integration D2 gain control fix D1 static gain control channel 2 sign bit D0 static gain control channel 1 sign bit Note HOLDG GAFIX GAI28 GAI18 0 1 0 1
1. HLNRS = 1 cannot be used in combination with CPOFF = 0. a) HLNRS = 0 and CPOFF = 0 is possible b) HLNRS = 0 and CPOFF = 1 is possible c) HLNRS = 1 and CPOFF = 0 is not recommended d) HLNRS = 1 and CPOFF = 1 is possible. 15.2.5 SUBADDRESS 04H
Table 42 Analog input control 3 (AICO3): static gain control channel 1; 03H[0] and 04H[7:0] DECIMAL VALUE 0... ...144 145... ...511 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[0] GAI18 0 0 0 1 GAI17 0 1 1 1 GAI16 0 0 0 1 CONTROL BITS D7 TO D0 GAI15 0 0 0 1 GAI14 0 1 1 1 GAI13 0 0 0 1 GAI12 0 0 0 1 GAI11 0 0 0 1 GAI10 0 0 1 1
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.6 SUBADDRESS 05H
SAA7118E
Table 43 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0] DECIMAL VALUE 0... ...144 145... ...511 15.2.7 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[1] GAI28 0 0 0 1 GAI27 0 1 1 1 GAI26 0 0 0 1 CONTROL BITS D7 TO D0 GAI25 0 0 0 1 GAI24 0 1 1 1 GAI23 0 0 0 1 GAI22 0 0 0 1 GAI21 0 0 0 1 GAI20 0 0 1 1
SUBADDRESS 06H
Table 44 Horizontal sync start; 06H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 15.2.8 SUBADDRESS 07H 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1
forbidden (outside available central counter range)
Table 45 Horizontal sync stop; 07H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 1 1 0 0 0 0 1 1 CONTROL BITS D7 TO D0 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
forbidden (outside available central counter range) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1
forbidden (outside available central counter range)
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.9 SUBADDRESS 08H
SAA7118E
Table 46 Sync control; 08H[7:0] BIT D7 D6 D5 DESCRIPTION automatic field detection field selection; active if AUFD = 0 forced ODD/EVEN toggle SYMBOL VALUE AUFD FSEL FOET 0 1 0 1 0 1 D[4:3] horizontal time constant selection HTC[1:0] 00 01 10 11 D2 horizontal PLL HPLL VNOI[1:0] 0 1 D[1:0] vertical noise reduction 00 01 10 11 FUNCTION field state directly controlled via FSEL automatic field detection; recommended setting 50 Hz, 625 lines 60 Hz, 525 lines ODD/EVEN signal toggles only with interlaced source ODD/EVEN signal toggles fieldwise even if source is non-interlaced TV mode, recommended for poor quality TV signals only; do not use for new applications VTR mode, recommended if a deflection control circuit is directly connected at the output of the decoder reserved fast locking mode; recommended setting PLL closed PLL open; horizontal frequency fixed normal mode; recommended setting fast mode, applicable for stable sources only; automatic field detection (AUFD) must be disabled free running mode vertical noise reduction bypassed
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.10 SUBADDRESS 09H Table 47 Luminance control; 09H[7:0] BIT D7 DESCRIPTION chrominance trap/comb filter bypass SYMBOL VALUE BYPS 0 1 D6 D5 adaptive luminance comb filter processing delay in non comb filter mode YCOMB LDEL 0 1 0 1 D4 remodulation bandwidth for luminance; see Figs 12 to 15 LUBW 0 1 D[3:0] sharpness control, luminance filter characteristic; see Fig.16 LUFI[3:0] 0001 0010 0011 0100 0101 0110 0111 0000 1000 1001 1010 1011 1100 1101 1110 1111 15.2.11 SUBADDRESS 0AH Table 48 Luminance brightness control: decoder part; 0AH[7:0] CONTROL BITS D7 TO D0 OFFSET DBRI7 255 (bright) 128 (ITU level) 0 (dark) 1 1 0 DBRI6 1 0 0 DBRI5 1 0 0 DBRI4 1 0 0 DBRI3 1 0 0 DBRI2 1 0 0 FUNCTION
SAA7118E
chrominance trap or luminance comb filter active; default for CVBS mode chrominance trap or luminance comb filter bypassed; default for S-video mode disabled (= chrominance trap enabled, if BYPS = 0) active, if BYPS = 0 processing delay is equal to internal pipelining delay; recommended setting one (NTSC standards) or two (PAL standards) video lines additional processing delay small remodulation bandwidth (narrow chroma notch higher luminance bandwidth) large remodulation bandwidth (wider chroma notch smaller luminance bandwidth) resolution enhancement filter 8.0 dB at 4.1 MHz resolution enhancement filter 6.8 dB at 4.1 MHz resolution enhancement filter 5.1 dB at 4.1 MHz resolution enhancement filter 4.1 dB at 4.1 MHz resolution enhancement filter 3.0 dB at 4.1 MHz resolution enhancement filter 2.3 dB at 4.1 MHz resolution enhancement filter 1.6 dB at 4.1 MHz plain low-pass filter 2 dB at 4.1 MHz low-pass filter 3 dB at 4.1 MHz low-pass filter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz low-pass filter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz low-pass filter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz low-pass filter 3 dB at 2.2 MHz; notch at 3.4 MHz low-pass filter 3 dB at 1.9 MHz; notch at 3.0 MHz low-pass filter 3 dB at 1.7 MHz; notch at 2.5 MHz
DBRI1 1 0 0
DBRI0 1 0 0
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.12 SUBADDRESS 0BH Table 49 Luminance contrast control: decoder part; 0BH[7:0] CONTROL BITS D7 TO D0 GAIN DCON7 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) 15.2.13 SUBADDRESS 0CH Table 50 Chrominance saturation control: decoder part; 0CH[7:0] CONTROL BITS D7 TO D0 GAIN DSAT7 1.984 (maximum) 1.0 (ITU level) 0 (colour off) -1 (inverse chrominance) -2 (inverse chrominance) 15.2.14 SUBADDRESS 0DH Table 51 Chrominance hue control; 0DH[7:0] CONTROL BITS D7 TO D0 HUE PHASE (DEG) HUEC7 +178.6... ...0... ...-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 0 0 0 1 1 DSAT6 1 1 0 1 0 DSAT5 1 0 0 0 0 DSAT4 1 0 0 0 0 DSAT3 1 0 0 0 0 DSAT2 1 0 0 0 0 0 0 0 0 1 1 DCON6 1 1 1 0 1 0 DCON5 1 0 0 0 0 0 DCON4 1 0 0 0 0 0 DCON3 1 0 0 0 0 0 DCON2 1 1 0 0 0 0
SAA7118E
DCON1 1 0 0 0 0 0
DCON0 1 0 0 0 0 0
DSAT1 1 0 0 0 0
DSAT0 1 0 0 0 0
HUEC1 1 0 0
HUEC0 1 0 0
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.15 SUBADDRESS 0EH Table 52 Chrominance control 1; 0EH[7:0] FUNCTION BIT D7 DESCRIPTION clear DTO SYMBOL CDTO VALUE 50 Hz/625 LINES 0 1 disabled
SAA7118E
60 Hz/525 LINES
Every time CDTO is set, the internal subcarrier DTO phase is reset to 0 and the RTCO output generates a logic 0 at time slot 68 (see document "RTC Functional Description", available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder); if a DTO reset is programmed via CDTO it has always to be executed in the following way: 1. Set CDTO = 0 2. Set CDTO = 1.
D[6:4]
colour standard selection in non AUTO mode
CSTD[2:0]
000 001 010 011 100 101 110 111
PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz) NTSC 4.43 (50 Hz) Combination-PAL N (3.58 MHz) NTSC N (3.58 MHz) reserved SECAM PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) PAL M (3.58 MHz) NTSC-Japan (3.58 MHz) reserved reserved; do not use reserved; do not use preferred standard(1) is preferred standard(1) is PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz) reserved; do not use reserved; do not use reserved; do not use preferred standard(1) is preferred standard(1) is PAL BGDHI (4.43 MHz) NTSC-Japan (3.58 MHz, no 7.5 IRE offset) preferred standard(1) is SECAM preferred standard(1) is NTSC M (3.58 MHz)
D[6:4]
colour standard selection in AUTO mode (AUTO mode is selected, if either AUTO0 or AUTO1 is set; see below)
CSTD[2:0]
000 001 010 011 100
101 110 111 D3 disable chrominance vertical filter and PAL phase error correction fast colour time constant DCVF 0 1 FCTC 0 1
reserved; do not use reserved; do not use chrominance vertical filter and PAL phase error correction on (during active video lines) chrominance vertical filter and PAL phase error correction permanently off nominal time constant fast time constant for special applications (high quality input source, fast chroma lock required, automatic standard detection off)
D2
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
FUNCTION BIT DESCRIPTION SYMBOL VALUE 50 Hz/625 LINES 14H[2] automatic chrominance AUTO[1:0] and standard detection control 0EH[1] 00 01 disabled
SAA7118E
60 Hz/525 LINES
active, filter settings and sharpness control are preset to default values according to the detected standard and mode; recommended setting active, filter settings are preset to default values according to the detected standard and mode active, but no filter presets disabled active
10 11 D0 adaptive chrominance comb filter CCOMB 0 1
Note 1. The meaning of `preferred standard' is, that the internal search machine will always give priority to the selected standard, thus the recognition time for these standards is kept short. 15.2.16 SUBADDRESS 0FH Table 53 Chrominance gain control; 0FH[7:0] BIT D7 DESCRIPTION automatic chrominance gain control SYMBOL ACGC VALUE 0 1 FUNCTION on; recommended setting programmable gain via CGAIN6 to CGAIN0; need to be set for SECAM standard
D[6:0] chrominance gain value (if ACGC is set to logic 1)
CGAIN[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5)
15.2.17 SUBADDRESS 10H Table 54 Chrominance control 2; 10H[7:0] BIT DESCRIPTION SYMBOL OFFU[1:0] VALUE 00 01 10 11 D[5:4] fine offset adjustment R - Y component OFFV[1:0] 00 01 10 11 D3 chrominance bandwidth; see Figs 10 and 11 CHBW 0 1 0 LSB
1 1 3 1 1 3 4 2 4
FUNCTION LSB LSB LSB
D[7:6] fine offset adjustment B - Y component
0 LSB
4LSB 2LSB 4LSB
small wide
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
BIT DESCRIPTION SYMBOL LCBW[2:0] VALUE 000
SAA7118E
FUNCTION smallest chrominance bandwidth/largest luminance bandwidth ... to ... largest chrominance bandwidth/smallest luminance bandwidth
D[2:0] combined luminance/chrominance bandwidth adjustment; see Figs 10 to 16
... 111
15.2.18 SUBADDRESS 11H Table 55 Mode/delay control; 11H[7:0] BIT D7 colour on DESCRIPTION SYMBOL COLO VALUE 0 1 D6 polarity of RTS1 output signal RTP1 HDEL[1:0] 0 1 D[5:4] fine position of HS (steps in 2/LLC) 00 01 10 11 D3 polarity of RTS0 output signal RTP0 YDEL[2:0] 0 1 D[2:0] luminance delay compensation (steps in 2/LLC) 100 000 011 FUNCTION automatic colour killer enabled; recommended setting colour forced on non-inverted inverted 0 1 2 3 non-inverted inverted -4... ...0... ...3
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.19 SUBADDRESS 12H Table 56 RT signal control: RTS0 output; 12H[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]]. RTS0 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.28) CREF2 (6.75 MHz toggling pulse; see Fig.28) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.28). HS: programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4] (see Fig.28) HQ; HREF gated with VGATE Reserved V123; vertical sync (see vertical timing diagrams Figs 26 and 27) VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] LSBs of the 9-bit ADC's FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 26 and 27 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1
SAA7118E
RTSE03 RTSE02 RTSE01 RTSE00 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
0
1
1
0
1 0
1 0
1
0
0
1
1 1 0 0 1 1
0 1 0 1 0 1
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs).
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 57 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]]. RTS1 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.28) CREF2 (6.75 MHz toggling pulse; see Fig.28) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Fig.28). HS: programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4] (see Fig.28) HQ; HREF gated with VGATE Reserved V123; vertical sync (see vertical timing diagrams Figs 26 and 27) VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] Reserved FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 26 and 27 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1
SAA7118E
RTSE13 RTSE12 RTSE11 RTSE10 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
0
1
1
0
1 0
1 0
1
0
0
1
1 1 0 0 1 1
0 1 0 1 0 1
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs).
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.20 SUBADDRESS 13H Table 58 RT/X-port output control; 13H[7:0] BIT D7 D6 DESCRIPTION RTCO output enable X-port XRH output selection SYMBOL VALUE RTCE XRHS 0 1 0 1 3-state enabled HREF (see Fig.28) HS: FUNCTION
SAA7118E
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4] (see Fig.28) D[5:4] X-port XRV output selection XRVS[1:0] 00 01 10 11 D3 horizontal lock indicator selection HLSEL OFTS[2:0] 0 1 000 001 V123 (see Figs 26 and 27) ITU 656 related field ID (see Figs 26 and 27) inverted V123 inverted ITU 656 related field ID copy of inverted HLCK status bit (default) fast horizontal lock indicator (for special applications only) ITU 656 ITU 656 like format with modified field blanking according to VGATE position (programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]]) Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted) reserved multiplexed AD2/AD1 or AD4/AD3 bypass (bits 8 to 1) dependent on mode settings (see Section 15.2.4); if two ADCs are selected AD2/AD4 is output at CREF = 1 and AD1/AD3 is output at CREF = 0 multiplexed AD2/AD1 or AD4/AD3 bypass (bits 7 to 0) dependent on mode settings (see Section 15.2.4); if two ADCs are selected AD2/AD4 is output at CREF = 1 and AD1/AD3 is output at CREF = 0 reserved multiplexed ADC MSB/LSB bypass dependent on mode settings; only one ADC should be selected at a time; ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0 are outputs at CREF0
D[2:0] XPD7 to XPD0 (port output format selection); see Section 9.5
010 011 100
101
110 111
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.21 SUBADDRESS 14H Table 59 Analog/ADC/auto/compatibility control; 14H[7:0] BIT D7 DESCRIPTION compatibility bit for SAA7199 update time interval for AGC value SYMBOL CM99 VALUE 0 1 UPTCV AOSL[2:0] 0 1 000 001 010 011 100 101 110 111 D3 D2 XTOUT output enable automatic chrominance standard detection control 1 ADC sample clock phase delay XTOUTE AUTO1 0 1 off (default) FUNCTION
SAA7118E
on (to be set only if SAA7199 is used for re-encoding in conjunction with RTCO active) horizontal update (once per line) vertical update (once per field) AOUT connected to ground AOUT connected to input AD1 AOUT connected to input AD2 AOUT connected to input AD3 AOUT connected to input AD4 reserved reserved AOUT connected to internal test point BPFOUT pin A2 (XTOUT) 3-stated pin A2 (XTOUT) enabled see Section 15.2.15
D6
23H[7] analog test select and 14H[5:4]
D[1:0]
APCK[1:0]
00 01 10 11
application dependent
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15.2.22 SUBADDRESS 15H Table 60 VGATE pulse; FID polarity change; 17H[0] and 15H[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 26 and 27. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 DECIMAL VALUE 312 MSB 17H[0] VSTA8 50 Hz 1 VSTA7 0 VSTA6 0 CONTROL BITS D7 TO D0 VSTA5 1 VSTA4 1 VSTA3 1 VSTA2 0 VSTA1 0 VSTA0 0
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Multistandard video decoder with adaptive comb filter and component video input
FIELD
Preliminary specification
SAA7118E
15.2.23 SUBADDRESS 16H
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Philips Semiconductors
Multistandard video decoder with adaptive comb filter and component video input
Table 61 VGATE stop; 17H[1] and 16H[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 26 and 27. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 DECIMAL VALUE 312 MSB 17H[1] VSTO8 50 Hz 1 VSTO7 0 VSTO6 0 CONTROL BITS D7 TO D0 VSTO5 1 VSTO4 1 VSTO3 1 VSTO2 0 VSTO1 0 VSTO0 0
FIELD
Preliminary specification
SAA7118E
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.24 SUBADDRESS 17H Table 62 Miscellaneous/VGATE MSBs; 17H[7:0] BIT D7 D6 DESCRIPTION LLC output enable LLC2 output enable SYMBOL VALUE LLCE LLC2E LATY[2:0] 0 1 0 1 D[5:3] standard detection search loop latency 000 001 010 011 ... 111 D2 D1 D0 alternative VGATE position MSB VGATE stop MSB VGATE start VGPS VSTO8 VSTA8 0 1 enable 3-state enable 3-state reserved one field two fields three fields; recommended setting ... to ... seven fields FUNCTION
SAA7118E
VGATE position according to Tables 60 and 61 VGATE occurs one line earlier during field 2 see Table 61 see Table 60
15.2.25 SUBADDRESS 18H Table 63 Raw data gain control; RAWG[7:0] 18H[7:0]; see Fig.18 CONTROL BITS D7 TO D0 GAIN RAWG7 255 (double amplitude) 128 (nominal level) 0 (off) 15.2.26 SUBADDRESS 19H Table 64 Raw data offset control; RAWO[7:0] 19H[7:0]; see Fig.18 CONTROL BITS D7 TO D0 OFFSET RAWO7 -128 LSB 0 LSB +128 LSB 0 1 1 RAWO6 0 0 1 RAWO5 0 0 1 RAWO4 0 0 1 RAWO3 0 0 1 RAWO2 0 0 1 RAWO1 0 0 1 RAWO0 0 0 1 0 0 0 RAWG6 1 1 0 RAWG5 1 0 0 RAWG4 1 0 0 RAWG3 1 0 0 RAWG2 1 0 0 RAWG1 1 0 0 RAWG0 1 0 0
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.2.27 SUBADDRESS 1EH Table 65 Status byte 1 video decoder; 1EH[6:0]; read only register BIT D6 D5 D4 D3 D2 D[1:0] DESCRIPTION status bit for locked horizontal frequency slow time constant active in WIPA mode gain value for active luminance channel is limited; maximum (top) gain value for active luminance channel is limited; minimum (bottom) white peak loop is activated detected colour standard I2C-BUS CONTROL BIT HLCK SLTCA GLIMT GLIMB WIPA DCSTD[1:0] VALUE 0 1 0 1 0 1 0 1 0 1 00 01 10 11 15.2.28 SUBADDRESS 1FH Table 66 Status byte 2 video decoder; 1FH[7:5] and 1FH[3:0]; read only register BIT D7 D6 D5 D3 D2 D1 D0 DESCRIPTION status bit for interlace detection status bit for horizontal and vertical loop identification bit for detected field frequency macrovision encoded colour stripe burst type 3 (4 line version) detected macrovision encoded colour stripe burst detected (any type) copy protected source detected according to macrovision version up to 7.01 ready for capture (all internal loops locked) I2C-BUS CONTROL BIT INTL HLVLN FIDT TYPE3 COLSTR COPRO RDCAP VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SAA7118E
FUNCTION locked unlocked not active active not active active not active active not active active no colour (black-white) NTSC PAL SECAM
FUNCTION non-interlaced interlaced both loops locked unlocked 50 Hz 60 Hz not active active not active active not active active not active active
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.3 15.3.1 Programming register RGB/Y-PB-PR component input processing SUBADDRESS 23H
SAA7118E
Table 67 Analog input control 5 (AICO5); 23H[7:4] and 23H[2:0] BIT DESCRIPTION SYMBOL VALUE AOSL2 ADPE 0 1 D5 ADC clock selector EXCLK 0 1 D4 clamping/reference selection for all ADCs D2 enable external source switch indicator input EXMCLR D1 static gain control channel 2 sign bit D0 static gain control channel 1 sign bit 15.3.2 SUBADDRESS 24H REFA EXMCE 0 1 0 1 GAI48 GAI38 FUNCTION see Table 59 AD port (pins P6, M6, L6, N7, P7, L7, M7, P8 and N8) is set to 3-state AD port (pins P6, M6, L6, N7, P7, L7, M7, P8 and N8) is enabled all ADCs are clocked by the internal generated line-locked clock all ADCs are clocked by the external input clock on pin N6 (CLKEXT) clamping is dependent on HLNRS[03H[6]] reference selection (input signal is pulled into ADC range) disabled enabled (any slope on EXMCLR input will reset the internal gain control loop) see Table 69 see Table 68
D7 analog output select D6 AD port output enable
Table 68 Analog input control 6 (AICO6): static gain control channel 3; 23H[0] and 24H[7:0] DECIMAL VALUE 0... ...144 145... ...511 15.3.3 GAIN (dB) -3 0 0 +6 SIGN BIT 23H[0] GAI38 0 0 0 1 GAI37 0 1 1 1 GAI36 0 0 0 1 CONTROL BITS D7 TO D0 GAI35 0 0 0 1 GAI34 0 1 1 1 GAI33 0 0 0 1 GAI32 0 0 0 1 GAI31 0 0 0 1 GAI30 0 0 1 1
SUBADDRESS 25H
Table 69 Analog input control 7 (AICO7): static gain control channel 4; 23H[1] and 25H[7:0] DECIMAL VALUE 0... ...144 145... ...511 GAIN (dB) -3 0 0 +6 SIGN BIT 23H[1] GAI48 0 0 0 1 GAI47 0 1 1 1 GAI46 0 0 0 1 CONTROL BITS D7 TO D0 GAI45 0 0 0 1 GAI44 0 1 1 1 GAI43 0 0 0 1 GAI42 0 0 0 1 GAI41 0 0 0 1 GAI40 0 0 1 1
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.3.4 SUBADDRESS 29H
SAA7118E
Table 70 Component delay/fast switch control; 29H[7:0] BIT D7 DESCRIPTION fast switch enable SYMBOL FSWE VALUE 0 1 disabled pixelwise switching between decoded CVBS signal and component input signal is enabled (should only be used for component sources synchronous to CVBS input) FSW = 0: decoded CVBS signal, FSW = 1: component signal FSW = 1: decoded CVBS signal, FSW = 0: component signal 0 pixel (default) +1 pixel -2 pixel -1 pixel disabled enabled (+1.5 dB at 5 MHz) 0 pixel (default) +4 pixel +8 pixel +12 pixel -16 pixel -12 pixel -8 pixel -4 pixel FUNCTION
D6
fast switch input polarity
FSWI FSWDL[1:0]
0 1 00 01 10 11
D[5:4] fast switch input delay adjustment relative to component input signal D3 component luminance peaking
CMFI CPDL[2:0]
0 1 000 001 010 011 100 101 110 111
D[2:0] component input delay adjustment relative to decoded CVBS signal
15.3.5
SUBADDRESS 2AH
Table 71 Luminance brightness control component part; 2AH[7:0] CONTROL BITS D7 TO D0 OFFSET CBRI7 255 (bright) 128 (ITU level) 0 (dark) 15.3.6 SUBADDRESS 2BH 1 1 0 CBRI6 1 0 0 CBRI5 1 0 0 CBRI4 1 0 0 CBRI3 1 0 0 CBRI2 1 0 0 CBRI1 1 0 0 CBRI0 1 0 0
Table 72 Luminance contrast control component part; 2BH[7:0] CONTROL BITS D7 TO D0 GAIN CCON7 1.984 (maximum) 1.0 (ITU level) 0 (luminance off) -1.0 (inverse luminance) -2.0 (inverse luminance) 2000 Nov 27 0 0 0 1 1 CCON6 1 1 0 1 0 CCON5 1 0 0 0 0 132 CCON4 1 0 0 0 0 CCON3 1 0 0 0 0 CCON2 1 0 0 0 0 CCON1 1 0 0 0 0 CCON0 1 0 0 0 0
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.3.7 SUBADDRESS 2CH
SAA7118E
Table 73 Chrominance saturation control component part; 2CH[7:0] CONTROL BITS D7 TO D0 GAIN CSAT7 1.984 (maximum) 1.0 (ITU level) 0 (colour off) -1.0 (inverse chrominance) -2.0 (inverse chrominance) 15.4 Interrupt mask registers 0 0 0 1 1 CSAT6 1 1 0 1 0 CSAT5 1 0 0 0 0 CSAT4 1 0 0 0 0 CSAT3 1 0 0 0 0 CSAT2 1 0 0 0 0 CSAT1 1 0 0 0 0 CSAT0 1 0 0 0 0
See also Section 9.4 15.4.1 SUBADDRESS 2DH
Table 74 Interrupt mask 1; 2DH[4:2] and 2DH[1] BIT DESCRIPTION SYMBOL MVPSV MPPV MCCV MERROF VALUE FUNCTION 0 1 D3 interrupt enable `PALplus detected/lost' (corresponding flag: 60H[3]) D2 interrupt enable `closed caption detected/lost' (corresponding flag: 60H[2]) D0 interrupt enable `error output formatter' (corresponding flag: 8FH[2]) 0 1 0 1 0 1 15.4.2 SUBADDRESS 2EH disabled enabled disabled enabled disabled enabled disabled enabled
D4 interrupt enable `VPS signal detected/lost' (corresponding flag: 60H[4])
Table 75 Interrupt mask 2; 2EH[6] and 2EH[1:0] BIT DESCRIPTION SYMBOL MHLCK MDCSTD1 MDCSTD0 VALUE FUNCTION 0 1 0 1 D0 interrupt enable `colour standard changed 0' (corresponding flag: 1EH[0]) 0 1 disabled enabled disabled enabled disabled enabled
D6 interrupt enable `horizontal PLL locked/unlocked' (corresponding flag: 1EH[6]) D1 interrupt enable `colour standard changed 1' (corresponding flag: 1EH[1])
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.4.3 SUBADDRESS 2FH
SAA7118E
Table 76 Interrupt mask 3; 2FH[7:5] and 2FH[3:0] BIT DESCRIPTION SYMBOL MINTL MHLVLN MFIDT MTYPE3 MCOLSTR MCOPRO MRDCAP VALUE FUNCTION 0 1 0 1 0 1 D3 interrupt enable `colour stripe type 3 burst detected/lost' (corresponding flag: 1FH[3]) D2 interrupt enable `colour stripe burst (any type) detected/lost' (corresponding flag: 1FH[2]) D1 interrupt enable `copy protected signal found/lost' (corresponding flag: 1FH[1]) D0 interrupt enable `ready for capture/not ready' (corresponding flag: 1FH[0]) 0 1 0 1 0 1 0 1 15.5 Programming register audio clock generation disabled enabled disabled enabled disabled enabled disabled enabled disabled enabled disabled enabled disabled enabled
D7 interrupt enable `interlaced/non-interlaced source' (corresponding flag: 1FH[7]) D6 interrupt enable `horizontal and vertical lock reached/lost' (corresponding flag: 1FH[6]) D5 interrupt enable `field frequency has changed' (corresponding flag: 1FH[5])
See equations in Section 8.7 and examples in Tables 22 and 23. 15.5.1 SUBADDRESSES 30H TO 32H
Table 77 Audio master clock (AMCLK) cycles per field SUBADDRESS 30H 31H 32H 15.5.2 ACPF7 ACPF15 - ACPF6 ACPF14 - ACPF5 ACPF13 - CONTROL BITS D7 TO D0 ACPF4 ACPF12 - ACPF3 ACPF11 - ACPF2 ACPF10 - ACPF1 ACPF9 ACPF17 ACPF0 ACPF8 ACPF16
SUBADDRESSES 34H TO 36H
Table 78 Audio master clock (AMCLK) nominal increment SUBADDRESS 34H 35H 36H 15.5.3 ACNI7 ACNI15 - ACNI6 ACNI14 - ACNI5 ACNI13 ACNI21 CONTROL BITS D7 TO D0 ACNI4 ACNI12 ACNI20 ACNI3 ACNI11 ACNI19 ACNI2 ACNI10 ACNI18 ACNI1 ACNI9 ACNI17 ACNI0 ACNI8 ACNI16
SUBADDRESS 38H
Table 79 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) SUBADDRESS 38H - - SDIV5 CONTROL BITS D7 TO D0 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.5.4 SUBADDRESS 39H
SAA7118E
Table 80 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK) SUBADDRESS 39H 15.5.5 - - LRDIV5 CONTROL BITS D7 TO D0 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0
SUBADDRESS 3AH
Table 81 Audio clock control; 3AH[3:0] BIT D3 D2 D1 D0 DESCRIPTION audio PLL modes audio master clock vertical reference ALRCLK phase ASCLK phase SYMBOL VALUE APLL AMVR LRPH SCPH 0 1 0 1 0 1 0 1 15.6 15.6.1 Programming register VBI-data slicer SUBADDRESS 40H FUNCTION PLL active, AMCLK is field-locked PLL open, AMCLK is free-running vertical reference pulse is taken from internal decoder vertical reference is taken from XRV input (expansion port) ALRCLK edges triggered by falling edges of ASCLK ALRCLK edges triggered by rising edges of ASCLK ASCLK edges triggered by falling edges of AMCLK ASCLK edges triggered by rising edges of AMCLK
Table 82 Slicer control 1; 40H[6:4] BIT D6 DESCRIPTION Hamming check SYMBOL VALUE HAM_N 0 1 D5 D4 framing code error amplitude searching FCE HUNT_N 0 1 0 1 FUNCTION Hamming check for 2 bytes after framing code, dependent on data type (default) no Hamming check one framing code error allowed no framing code errors allowed amplitude searching active (default) amplitude searching stopped
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.6.2 SUBADDRESSES 41H TO 57H
SAA7118E
Table 83 Line control register; LCR2 to LCR24 (41H to 57H) See Sections 8.3 and 8.5. D[7:4] (41H TO 57H) NAME DESCRIPTION FRAMING CODE DT[3:0] 62H[3:0] (FIELD 1) WST625 CC625 VPS WSS WST525 CC525 Test line Intercast VITC625 VITC525 Reserved NABTS Japtext JFS teletext EuroWST, CCST European closed caption video programming service wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region raw data VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) 27H 001 9951H 1E3C1FH 27H 001 - - programmable programmable programmable - - programmable (A7H) programmable - 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DT[3:0] 62H[3:0] (FIELD 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D[3:0] (41H TO 57H)
General text teletext
Active video video component signal, active video region (default) 15.6.3 SUBADDRESS 58H
Table 84 Programmable framing code; slicer set 58H[7:0] According to Tables 15 and 83. FRAMING CODE FOR PROGRAMMABLE DATA TYPES Default value 15.6.4 SUBADDRESS 59H CONTROL BITS D7 TO D0 FC[7:0] = 40H
Table 85 Horizontal offset for slicer; slicer set 59H and 5BH HORIZONTAL OFFSET Recommended value CONTROL BITS 5BH[2:0] HOFF[10:8] = 3H CONTROL BITS 59H[7:0] HOFF[7:0] = 47H
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.6.5 SUBADDRESS 5AH
SAA7118E
Table 86 Vertical offset for slicer; slicer set 5AH and 5BH CONTROL BIT 5BH[4] VERTICAL OFFSET VOFF8 Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input 15.6.6 SUBADDRESS 5BH 0 1 0 0 VOFF[7:0] 00H 38H 03H 06H CONTROL BITS 5AH[7:0]
Table 87 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6] See Sections 15.6.4 and 15.6.5 for HOFF[10:8] 5BH[2:0] and VOFF8[5BH[4]]. BIT D7 DESCRIPTION field offset SYMBOL FOFF VALUE 0 1 D6 recode RECODE 0 1 15.6.7 SUBADDRESS 5DH FUNCTION no modification of internal field indicator (default for 50 Hz 625 lines input sources) invert field indicator (default for 60 Hz 525 lines input sources) leave data unchanged (default) convert 00H and FFH data bytes into 03H and FCH
Table 88 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0] BIT D7 DESCRIPTION field ID and V-blank selection for text output (F and V reference selection) SYMBOL FVREF VALUE 0 1 DID[5:0] FUNCTION F and V output of slicer is LCR table dependent F and V output is taken from decoder real-time signals EVEN_ITU and VBLNK_ITU
D[5:0] default; DID[5:0] = 00H special cases of DID programming 15.6.8 SUBADDRESS 5EH
00 0000 ANC header framing; see Fig.35 and Table 21 11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1 11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0
Table 89 Sliced data identification (SDID) code; slicer set 5EH[5:0] BIT DESCRIPTION SYMBOL SDID[5:0] VALUE 00H default FUNCTION
D[5:0] SDID codes
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.6.9 SUBADDRESS 60H
SAA7118E
Table 90 Slicer status byte 0; 60H[6:2]; read only register BIT D6 D5 D4 D3 D2 DESCRIPTION framing code valid framing code valid VPS valid PALplus valid closed caption valid SYMBOL FC8V FC7V VPSV PPV CCV VALUE 0 1 0 1 0 1 0 1 0 1 15.6.10 SUBADDRESSES 61H AND 62H Table 91 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]; read only registers SUBADDRESS 61H 62H BIT D5 D[4:0] D[7:4] D[3:0] 15.7 15.7.1 SYMBOL F21_N LN[8:4] LN[3:0] DT[3:0] data type; according to Table 15 line number DESCRIPTION field ID as seen by the VBI slicer; for field 1: D5 = 0 FUNCTION no framing code (0 error) in the last frame detected framing code with 0 error detected no framing code (1 error) in the last frame detected framing code with 1 error detected no VPS in the last frame VPS detected no PALplus in the last frame PALplus detected no closed caption in the last frame closed caption detected
Programming register interfaces and scaler part SUBADDRESS 80H
Table 92 Global control 1; global set 80H[6:4] SWRST moved to subaddress 88H[5]; X = don't care. CONTROL BITS D6 TO D4 TASK ENABLE CONTROL SMOD Task of register set A is disabled Task of register set A is enabled Task of register set B is disabled Task of register set B is enabled The scaler window defines the F and V timing of the scaler output VBI-data slicer defines the F and V timing of the scaler output X X X X 0 1 TEB X X 0 1 X X TEA 0 1 X X X X
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 93 Global control 1; global set 80H[3:0] X = don't care.
SAA7118E
CONTROL BITS D3 TO D0 I-PORT AND SCALER BACK-END CLOCK SELECTION ICKS3 ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X-port ICLK output is LLC and back-end clock is LLC2 clock Back-end clock is the ICLK input IDQ pin carries the data qualifier IDQ pin carries a gated back-end clock (DQ AND CLK) IDQ generation only for valid data IDQ qualifies valid data inside the scaling region and all data outside the scaling region Note 1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1. 15.7.2 SUBADDRESSES 83H TO 87H X X X X X X 0 1 ICKS2 X X X(1) X 0 1 X X ICKS1 0 0 1 1 X X X X ICKS0 0 1 0 1 X X X X
Table 94 X-port I/O enable and output clock phase control; global set 83H[5:4] CONTROL BITS D5 AND D4 OUTPUT CLOCK PHASE CONTROL XPCK1 XCLK default output phase, recommended value XCLK output inverted XCLK phase shifted by approximately 3 ns XCLK output inverted and shifted by approximately 3 ns Table 95 X-port I/O enable and output clock phase control; global set 83H[2:0] X = don't care. CONTROL BITS D2 TO D0 X-PORT I/O ENABLE XRQT X-port output is disabled by software X-port output is enabled by software X-port output is enabled by pin XTRI at logic 0 X-port output is enabled by pin XTRI at logic 1 XRDY output signal is A/B task flag from event handler (A = 1) XRDY output signal is ready signal from scaler path (XRDY = 1 means the SAA7118E is ready to receive data) X X X X 0 1 XPE1 0 0 1 1 X X XPE0 0 1 0 1 X X 0 0 1 1 XPCK0 0 1 0 1
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 96 I-port signal definitions; global set 84H[7:6] and 86H[5]
SAA7118E
CONTROL BITS I-PORT SIGNAL DEFINITIONS 86H[5] IDG02 IGP0 is output field ID, as defined by OFIDC[90H[6]] IGP0 is A/B task flag, as defined by CONLH[90H[7]] IGP0 is sliced data flag, framing the sliced VBI-data at the I-port IGP0 is set to logic 0 (default polarity) IGP0 is the output FIFO almost filled flag IGP0 is the output FIFO overflow flag IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86H Table 97 I-port signal definitions; global set 84H[5:4] and 86H[4] CONTROL BITS I-PORT SIGNAL DEFINITIONS 86H[4] IDG12 IGP1 is output field ID, as defined by OFIDC[90H[6]] IGP1 is A/B task flag, as defined by CONLH[90H[7]] IGP1 is sliced data flag, framing the sliced VBI-data at the I-port IGP1 is set to logic 0 (default polarity) IGP1 is the output FIFO almost filled flag IGP1 is the output FIFO overflow flag IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86H Table 98 I-port output signal definitions; global set 84H[3:0] X = don't care. CONTROL BITS D3 TO D0 I-PORT OUTPUT SIGNAL DEFINITIONS IDV1 IGPH is a H-gate signal, framing the scaler output IGPH is an extended H-gate (framing H-gate during scaler output and scaler input H-reference outside the scaler window) IGPH is a horizontal trigger pulse, on active going edge of H-gate IGPH is a horizontal trigger pulse, on active going edge of extended H-gate IGPV is a V-gate signal, framing scaled output lines IGPV is the V-reference signal from scaler input IGPV is a vertical trigger pulse, derived from V-gate IGPV is a vertical trigger pulse derived from input V-reference X X X X 0 0 1 1 IDV0 X X X X 0 1 0 1 IDH1 0 0 1 1 X X X X IDH0 0 1 0 1 X X X X 0 0 0 0 1 1 1 1 84H[5:4] IDG11 0 0 1 1 0 0 1 1 IDG10 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 84H[7:6] IDG01 0 0 1 1 0 0 1 1 IDG00 0 1 0 1 0 1 0 1
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 99 X-port signal definitions text slicer; global set 85H[7:5] X = don't care.
SAA7118E
CONTROL BITS D7 TO D5 X-PORT SIGNAL DEFINITIONS TEXT SLICER ISWP1 Video data limited to range 1 to 254 Video data limited to range 8 to 247 Dword byte swap, influences serial output timing D0 D1 D2 D3 FF 00 00 SAV CB0 Y0 CR0 Y1 D1 D0 D3 D2 00 FF SAV 00 Y0 CB0 Y1 CR0 D2 D3 D0 D1 00 SAV FF 00 CR0 Y1 CB0 Y0 D3 D2 D1 D0 SAV 00 00 FF Y1 CR0 Y0 CB0 Table 100 I-port reference signal polarities; global set 85H[4:0] X = don't care. CONTROL BITS D4 TO D0 I-PORT REFERENCE SIGNAL POLARITIES IGP0P IDQ at default polarity (1 = active) IDQ is inverted IGPH at default polarity (1 = active) IGPH is inverted IGPV at default polarity (1 = active) IGPV is inverted IGP1 at default polarity IGP1 is inverted IGP0 at default polarity IGP0 is inverted X X X X X X X X 0 1 IGP1P X X X X X X 0 1 X X IGVP X X X X 0 1 X X X X IGHP X X 0 1 X X X X X X IDQP 0 1 X X X X X X X X X X 0 0 1 1 ISWP0 X X 0 1 0 1 ILLV 0 1 X X X X
Table 101 I-port FIFO flag control and arbitration; global set 86H[7:4] X = don't care. CONTROL BITS D7 TO D4 FUNCTION VITX1 See subaddress 84H: IDG11 and IDG10 See subaddress 84H: IDG01 and IDG00 I-port signal definitions I-port data output inhibited Only video data is transferred Only text data is transferred (no EAV, SAV will occur) Text and video data is transferred, text has priority 0 0 1 1 0 1 0 1 X X X X X X X X X X X X VITX0 X X X X IDG02 X X 0 1 IDG12 0 1 X X
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 102 I-port FIFO flag control and arbitration; global set 86H[3:0] X = don't care.
SAA7118E
CONTROL BITS D3 TO D0 I-PORT FIFO FLAG CONTROL AND ARBITRATION FFL1 FAE FIFO flag almost empty level <16 Dwords <8 Dwords <4 Dwords 0 Dwords FAF FIFO flag almost full level 16 Dwords 24 Dwords 28 Dwords 32 Dwords 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X 0 0 1 1 0 1 0 1 FFL0 FEL1 FEL0
Table 103 I-port I/O enable, output clock and gated clock phase control; global set 87H[7:4] CONTROL BITS D7 TO D4(1) OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL ICLK default output phase ICLK phase shifted by 12 clock cycle recommended for ICKS1 = 1 and ICKS0 = 0 (subaddress 80H) ICLK phase shifted by approximately 3 ns ICLK phase shifted by 2 clock cycle + approximately 3 ns alternatively to setting `01' IDQ = gated clock default output phase IDQ = gated clock phase shifted by for gated clock output IDQ = gated clock phase shifted by 3 ns alternatively to setting `01' Notes 1. X = don't care. 2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1). Table 104 I-port I/O enable, output clock and gated clock phase control; global set 87H[1:0] CONTROL BITS D1 AND D0 I-PORT I/O ENABLE IPE1 I-port output is disabled by software I-port output is enabled by software I-port output is enabled by pin ITRI at logic 0 I-port output is enabled by pin ITRI at logic 1 0 0 1 1 IPE0 0 1 0 1
1 2 1
IPCK3(2) X X X X 0 0 1 1
IPCK2(2) X X X X 0 1 0 1
IPCK1 0 0 1 1 X X X X
IPCK0 0 1 0 1 X X X X
clock cycle recommended
IDQ = gated clock phase shifted by approximately 3 ns
1 2
clock cycle + approximately
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.7.3 SUBADDRESS 88H
SAA7118E
Table 105 ADC-port control; global set 88H[7:4] CONTROL BITS D7 TO D4(1) ADC-PORT OUTPUT CONTROL/START-UP CONTROL DOSL1 DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a logic 0 a power-up or start-up fail has occurred Scaler path is reset to its idle state, software reset Scaler is switched back to operation Digitized ADC1 signal is fed to port ADP[8:0] Digitized ADC2 signal is fed to port ADP[8:0] Digitized ADC3 signal is fed to port ADP[8:0] Digitized ADC4 signal is fed to port ADP[8:0] Notes 1. X = don't care. 2. Bit SWRST is now located here. Table 106 Power save control; global set 88H[3] and 88H[1:0] X = don't care. CONTROL BITS D3, D1 AND D0 POWER SAVE CONTROL SLM3 Decoder and VBI slicer are in operational mode Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler input and ICLK source is the X-port (refer to subaddresses 80H and 91H/C1H) Scaler is in operational mode Scaler is in power-down mode; scaler in power-down stops I-port output Audio clock generation active Audio clock generation in power-down and output disabled X X X X 0 1 SLM1 X X 0 1 X X SLM0 0 1 X X X X X X DOSL0 X X SWRST(2) X X DPROG 0 1
X X 0 0 1 1
X X 0 1 0 1
0 1 X X X X
X X X X X X
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.7.4 SUBADDRESS 8FH
SAA7118E
Table 107 Status information scaler part; 8FH[7:0]; read only register BIT D7 D6 D5 D4 D3 D2 I2C-BUS STATUS BIT XTRI ITRI FFIL FFOV PRDON ERROF FUNCTION(1) status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use status of the internal `FIFO almost filled' flag status of the internal `FIFO overflow' flag copy of bit DPROG, can be used to detect power-up and start-up fails error flag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all internal FIFO capacity used status of the field sequence ID at the scalers input status of the field sequence ID at the scalers output, scaler processing dependent
D1 D0 Note
FIDSCI FIDSCO
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read. 15.7.5 SUBADDRESSES 90H AND C0H
Table 108 Task handling control; register set A [90H[7:6]] and B [C0H[7:6]] X = don't care. CONTROL BITS D7 AND D6 EVENT HANDLER CONTROL CONLH Output field ID is field ID from scaler input Output field ID is task status flag, which changes every time an selected task is activated (not synchronized to input field ID) Scaler SAV/EAV byte bit D7 and task flag = 1, default Scaler SAV/EAV byte bit D7 and task flag = 0 Table 109 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]] CONTROL BITS D5 TO D3 EVENT HANDLER CONTROL FSKP2 Active task is carried out directly 1 field is skipped before active task is carried out ... fields are skipped before active task is carried out 6 fields are skipped before active task is carried out 7 fields are skipped before active task is carried out 0 0 ... 1 1 FSKP1 0 0 ... 1 1 FSKP0 0 1 ... 0 1 X X 0 1 OFIDC 0 1 X X
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 110 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]] X = don't care.
SAA7118E
CONTROL BITS D2 TO D0 EVENT HANDLER CONTROL RPTSK Event handler triggers immediately after finishing a task Event handler triggers with next V-sync Event handler triggers with field ID = 0 Event handler triggers with field ID = 1 If active task is finished, handling is taken over by the next task Active task is repeated once, before handling is taken over by the next task 15.7.6 SUBADDRESSES 91H TO 93H X X X X 0 1 STRC1 0 0 1 1 X X STRC0 0 1 0 1 X X
Table 111 X-port formats and configuration; register set A [91H[7:3]] and B [C1H[7:3]] X = don't care. SCALER INPUT FORMAT AND CONFIGURATION SOURCE SELECTION Only if XRQT[83H[2]] = 1: scaler input source reacts on SAA7118E request Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAA7118E decoder part is source of scaler or XRQT[83H[2]] = 0) Scaler input source is data from decoder, data type is provided according to Table 15 Scaler input source is Y-CB-CR data from X-port Scaler input source is raw digital CVBS from selected analog channel, for backward compatibility only, further use is not recommended Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR, if no 16-bit outputs are active) from X-port SAV/EAV code bits D6 and D5 (F and V) may change between SAV and EAV SAV/EAV code bits D6 and D5 (F and V) are synchronized to scalers output line start SAV/EAV code bit D5 (V) and V-gate on pin IGPV as generated by the internal processing; see Fig.41 SAV/EAV code bit D5 (V) and V-gate are inverted CONTROL BITS D7 TO D3 CONLV X X HLDFV X X SCSRC1 SCSRC0 X X X X SCRQE 0 1
X X X
X X X
0 0 1
0 1 0
X X X
X X X 0 1
X 0 1 X X
1 X X X X
1 X X X X
X X X X X
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 112 X-port formats and configuration; register set A [91H[2:0]] and B [C1H[2:0]] SCALER INPUT FORMAT AND CONFIGURATION FORMAT CONTROL Input is Y-CB-CR 4 : 2 : 2 like sampling scheme Input is Y-CB-CR 4 : 1 : 1 like sampling scheme Chroma is provided every line, default Chroma is provided every 2nd line Chroma is provided every 3rd line Chroma is provided every 4th line Notes 1. X = don't care.
SAA7118E
CONTROL BITS D2 TO D0(1) FSC2(2) X X 0 0 1 1 FSC1(2) X X 0 1 0 1 FSC0 0 1 X X X X
2. FSC2 and FSC1 only to be used, if X-port input source don't provide chroma information for every input line. X-port input stream must contain dummy chroma bytes. Table 113 X-port input reference signal definitions; register set A [92H[7:4]] and B [C2H[7:4]] X = don't care. CONTROL BITS D7 TO D4 X-PORT INPUT REFERENCE SIGNAL DEFINITIONS XFDV Rising edge of XRV input and decoder V123 is vertical reference Falling edge of XRV input and decoder V123 is vertical reference XRV is a V-sync or V-gate signal XRV is a frame sync, V-pulses are generated internally on both edges of FS input X-port field ID is state of XRH at reference edge on XRV (defined by XFDV) Field ID (decoder and X-port field ID) is inverted Reference edge for field detection is falling edge of XRV Reference edge for field detection is rising edge of XRV X X X X X X 0 1 XFDH X X X X 0 1 X X XDV1 X X 0 1 X X X X XDV0 0 1 X X X X X X
Table 114 X-port input reference signal definitions; register set A [92H[3:0]] and B [C2H[3:0]] X = don't care. CONTROL BITS D3 TO D0 X-PORT INPUT REFERENCE SIGNAL DEFINITIONS XCODE XCLK input clock and XDQ input qualifier are needed Data rate is defined by XCLK only, no XDQ signal used Data are qualified at XDQ input at logic 1 Data are qualified at XDQ input at logic 0 Rising edge of XRH input is horizontal reference Falling edge of XRH input is horizontal reference Reference signals are taken from XRH and XRV Reference signals are decoded from EAV and SAV X X X X X X 0 1 XDH X X X X 0 1 X X XDQ X X 0 1 X X X X XCKS 0 1 X X X X X X
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 115 I-port output format and configuration; register set A [93H[7:5]] and B [C3H[7:5]] X = don't care.
SAA7118E
CONTROL BITS D7 TO D5 I-PORT OUTPUT FORMATS AND CONFIGURATION ICODE All lines will be output Skip the number of leading Y only lines, as defined by FOI1 and FOI0 Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0 Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits ISWP1 and ISWP0 No ITU 656 like SAV/EAV codes are available ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a qualifier Table 116 I-port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]] X = don't care. CONTROL BITS D4 TO D0 I-PORT OUTPUT FORMATS AND CONFIGURATION FOI1 4 : 2 : 2 Dword formatting 4 : 1 : 1 Dword formatting 4 : 2 : 0, only every 2nd line Y + CB-CR output, in between Y only output 4 : 1 : 0, only every 4th line Y + CB-CR output, in between Y only output Y only Not defined Not defined Not defined No leading Y only line, before 1st Y + CB-CR line is output 1 leading Y only line, before 1st Y + CB-CR line is output 2 leading Y only lines, before 1st Y + CB-CR line is output 3 leading Y only lines, before 1st Y + CB-CR line is output X X X X X X X X 0 0 1 1 FOI0 X X X X X X X X 0 1 0 1 FSI2 0 0 0 0 1 1 1 1 X X X X FSI1 0 0 1 1 0 0 1 1 X X X X FSI0 0 1 0 1 0 1 0 1 X X X X X X X X 0 1 I8_16 X X 0 1 X X FYSK 0 1 X X X X
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Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.7.7 SUBADDRESSES 94H TO 9BH
SAA7118E
Table 117 Horizontal input window start; register set A [94H[7:0]; 95H[3:0]] and B [C4H[7:0]; C5H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN X (HORIZONTAL) DIRECTION(1) A minimum of `2' should be kept, due to a line counting mismatch Odd offsets are changing the CB-CR sequence in the output stream to CR-CB sequence Maximum possible pixel offset = 4095 Note 1. Reference for counting are luminance samples. Table 118 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be rounded up to even lengths Maximum possible number of input pixels = 4095 Note 1. Reference for counting are luminance samples. Table 119 Vertical input window start; register set A [98H[7:0]; 99H[3:0]] and B [C8H[7:0]; C9H[3:0]] VERTICAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN Y (VERTICAL) DIRECTION(1) Line offset = 0 Line offset = 1 Maximum line offset = 4095 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YO > (number of input lines per field - 2), will result in field dropping. CONTROL BITS A(98H[3:0]) B(C8H[3:0]) A(98H[7:0]) B(C8H[7:0]) CONTROL BITS A (97H[3:0]) B (C7H[3:0]) A(96H[7:0]) B(C6H[7:0]) CONTROL BITS A(95H[3:0]) B(C5H[3:0]) A(94H[7:0]) B(C4H[7:0])
XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
1
1
1
1
1
1
1
1
1
1
1
1
XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SAA7118E
Table 120 Vertical input window length; register set A [9AH[7:0]; 9BH[3:0]] and B [CAH[7:0]; CBH[3:0]] VERTICAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN Y (VERTICAL) DIRECTION(1) No input lines 1 input line Maximum possible number of input lines = 4095 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YS > (number of input lines per field - 2), will result in field dropping. 15.7.8 SUBADDRESSES 9CH TO 9FH CONTROL BITS A(9BH[3:0]) B(CBH[3:0]) YS11 YS10 0 0 1 0 0 1 YS9 0 0 1 YS8 0 0 1 A(9AH[7:0]) B(CAH[7:0]) YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
Table 121 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]] HORIZONTAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT PIXEL IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be filled up to even lengths Maximum possible number of input pixels = 4095; note 2 Notes 1. Reference for counting are luminance samples. 2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. Table 122 Vertical output window length; register set A [9EH[7:0]; 9FH[3:0]] and B [CEH[7:0]; CFH[3:0]] VERTICAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT LINES IN Y (VERTICAL) DIRECTION No output 1 pixel Maximum possible number of output lines = 4095; note 1 Note 1. If the desired output length is greater than the number of scaled output lines, the processing is cut. CONTROL BITS A(9FH[3:0]) B(CFH[3:0]) A(9EH[7:0]) B(CEH[7:0]) CONTROL BITS A(9DH[3:0]) B(CDH[3:0]) A(9CH[7:0]) B(CCH[7:0])
XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.7.9 SUBADDRESSES A0H TO A2H
SAA7118E
Table 123 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]] CONTROL BITS D5 TO D0 HORIZONTAL INTEGER PRESCALING RATIO (XPSC) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Not allowed Downscale = 1 Downscale = ... Downscale = 163
1 2
0 0 0 ... 1
0 0 0 ... 1
0 0 0 ... 1
0 0 0 ... 1
0 0 1 ... 1
0 1 0 ... 1
Table 124 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]] HORIZONTAL PRESCALER ACCUMULATION SEQUENCE LENGTH (XACL) Accumulation length = 1 Accumulation length = 2 ... Accumulation length = 64 CONTROL BITS D5 TO D0 XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 1 ... 1
Table 125 Prescaler DC gain and FIR prefilter control; register set A [A2H[7:4]] and B [D2H[7:4]] X = don't care. CONTROL BITS D7 TO D4 FIR PREFILTER CONTROL PFUV1 PFUV0 Luminance FIR filter bypassed H_y(z) = H_y(z) = H_y(z) =
1 4 1 8 1 8
PFY1 0 0 1 1 X X X X
PFY0 0 1 0 1 X X X X
X X X X 0 0 1 1
X X X X 0 1 0 1
(1 2 1) (-1 1 1.75 4.5 1.75 1 -1) (1 2 2 2 1)
Chrominance FIR filter bypassed H_uv(z) = 14 (1 2 1) H_uv(z) = H_uv(z) =
1 1 32 8
(3 8 10 8 3)
(1 2 2 2 1)
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 126 Prescaler DC gain and FIR prefilter control; register set A [A2H[3:0]] and B [D2H[3:0]] X = don't care.
SAA7118E
CONTROL BITS D3 TO D0 PRESCALER DC GAIN XC2_1 Prescaler output is renormalized by gain factor = 1 Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor =
1 1 1 1 1 2
XDCG2 0 0 0 0 1 1 1 1 X X
XDCG1 0 0 1 1 0 0 1 1 X X
XDCG0 0 1 0 1 0 1 0 1 X X
X X X X X X X X 0 1
Prescaler output is renormalized by gain factor = 14
8 16
Prescaler output is renormalized by gain factor = 132
64 128
Weighting of all accumulated samples is factor `1'; e.g. XACL = 4 sequence 1 + 1 + 1 + 1 + 1 Weighting of samples inside sequence is factor `2'; e.g. XACL = 4 sequence 1 + 2 + 2 + 2 + 1 15.7.10 SUBADDRESSES A4H TO A6H
Table 127 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]] LUMINANCE BRIGHTNESS CONTROL Value = 0 Nominal value = 128 Value = 255 CONTROL BITS D7 TO D0 BRIG7 0 1 1 BRIG6 0 0 1 BRIG5 0 0 1 BRIG4 0 0 1 BRIG3 0 0 1 BRIG2 0 0 1 BRIG1 0 0 1 BRIG0 0 0 1
Table 128 Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]] LUMINANCE CONTRAST CONTROL Gain = 0 Gain = 164 Nominal gain = 64 Gain =
127 64
CONTROL BITS D7 TO D0 CONT7 0 0 0 0 CONT6 0 0 1 1 CONT5 0 0 0 1 CONT4 0 0 0 1 CONT3 0 0 0 1 CONT2 0 0 0 1 CONT1 0 0 0 1 CONT0 0 1 0 1
Table 129 Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]] CHROMINANCE SATURATION CONTROL Gain = 0 Gain =
1 64
CONTROL BITS D7 TO D0 SATN7 0 0 0 0 SATN6 0 0 1 1 SATN5 0 0 0 1 SATN4 0 0 0 1 SATN3 0 0 0 1 SATN2 0 0 0 1 SATN1 0 0 0 1 SATN0 0 1 0 1
Nominal gain = 64 Gain = 12764
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
15.7.11 SUBADDRESSES A8H TO AEH
SAA7118E
Table 130 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]] CONTROL BITS HORIZONTAL LUMINANCE SCALING INCREMENT
1024 (theoretical) zoom 1 1024 294, lower limit defined
A(A9H[7:4]) B(D9H[7:4]) XSCY[15:12](1)
A(A9H[3:0]) B(D9H[3:0]) XSCY[11:8] 0000 0001 0011 0100 0100 1111
A(A8H[7:4]) B(D8H[7:4]) XSCY[7:4] 0000 0010 1111 0000 0000 1111
A(A8H[3:0]) B(D8H[3:0]) XSCY[3:0] 0000 0110 1111 0000 0001 1111
Scale =
0000 by 0000 0000 0000 0000 0001
Scale = data path structure
Scale = 10241023 zoom Scale = 1, equals 1024 Scale = 10241025 downscale Scale = Note
1024 8191
downscale
1. Bits XSCY[15:13] are reserved and are set to logic 0. Table 131 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]] HORIZONTAL LUMINANCE PHASE OFFSET Offset = 0 Offset = Offset = Offset =
1 pixel 32 32 = 1 pixel 32 255 pixel 32
CONTROL BITS D7 TO D0 XPHY7 0 0 0 1 XPHY6 0 0 0 1 XPHY5 0 0 1 1 XPHY4 0 0 0 1 XPHY3 0 0 0 1 XPHY2 0 0 0 1 XPHY1 0 0 0 1 XPHY0 0 1 0 1
Table 132 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]] CONTROL BITS HORIZONTAL CHROMINANCE SCALING INCREMENT A [ADH[7:4]] B [DDH[7:4]] XSCC[15:12](1) This value must be set to the luminance value 12XSCY[15:0] 0000 0000 0001 Note 1. Bits XSCC[15:13] are reserved and are set to logic 0. A [ADH[3:0]] B [DDH[3:0]] XSCC[11:8] 0000 0000 1111 A [ACH[7:4]] B [DCH[7:4]] XSCC[7:4] 0000 0000 1111 A [ACH[3:0]] B [DCH[3:0]] XSCC[3:0] 0000 0001 1111
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 133 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]] HORIZONTAL CHROMINANCE PHASE OFFSET This value must be set to
1 XPHY[7:0] 2
SAA7118E
CONTROL BITS D7 TO D0 XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
15.7.12 SUBADDRESSES B0H TO BFH Table 134 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]] CONTROL BITS VERTICAL LUMINANCE SCALING INCREMENT Scale = 10241 (theoretical) zoom Scale = Scale = Scale =
1024 1023
A [B1H[7:4]] B [E1H[7:4]] YSCY[15:12] 0000 0000 0000 0000 1111
A [B1H[3:0]] B [E1H[3:0]] YSCY[11:8] 0000 0011 0100 0100 1111
A [B0H[7:4]] B [E0H[7:4]] YSCY[7:4] 0000 1111 0000 0000 1111
A [B0H[3:0]] B [E0H[3:0]] YSCY[3:0] 0001 1111 0000 0001 1111
zoom
Scale = 1, equals 1024
1024 1025 downscale 1 63.999 downscale
Table 135 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]] CONTROL BITS VERTICAL CHROMINANCE SCALING INCREMENT A [B3H[7:4]] B [E3H[7:4]] YSCC[15:12] This value must be set to the luminance value YSCY[15:0] 0000 1111 A [B3H[3:0]] B [E3H[3:0]] YSCC[11:8] 0000 1111 A [B2H[7:4]] B [E2H[7:4]] YSCC[7:4] 0000 1111 A [B2H[3:0]] B [E2H[3:0]] YSCC[3:0] 0001 1111
Table 136 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]] X = don't care. CONTROL BITS D4 AND D0 VERTICAL SCALING MODE CONTROL YMIR Vertical scaling performs linear interpolation between lines Vertical scaling performs higher order accumulating interpolation, better alias suppression No mirroring Lines are mirrored X X 0 1 YMODE 0 1 X X
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
Table 137 Vertical chrominance phase offset `00'; register set A [B8H[7:0]] and B [E8H[7:0]] VERTICAL CHROMINANCE PHASE OFFSET Offset = 0 Offset = 3232 = 1 line Offset = 25532 lines CONTROL BITS D7 TO D0 YPC07 0 0 1 YPC06 0 0 1 YPC05 0 1 1 YPC04 0 0 1 YPC03 0 0 1 YPC02 0 0 1
SAA7118E
YPC01 0 0 1
YPC00 0 0 1
Table 138 Vertical luminance phase offset `00'; register set A [BCH[7:0]] and B [ECH[7:0]] VERTICAL LUMINANCE PHASE OFFSET Offset = 0 Offset = 3232 = 1 line Offset = 25532 lines 16 PROGRAMMING START SET-UP 16.1 Decoder part CONTROL BITS D7 TO D0 YPY07 0 0 1 YPY06 0 0 1 YPY05 0 1 1 YPY04 0 0 1 YPY03 0 0 1 YPY02 0 0 1 YPY01 0 0 1 YPY00 0 0 1
The given values force the following behaviour of the SAA7118E decoder part: * The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias filter and AGC active * Automatic field detection enabled * Standard ITU 656 output format enabled on expansion (X) port * Contrast, brightness and saturation control in accordance with ITU standards * Adaptive comb filter for luminance and chrominance activated * Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state. Table 139 Decoder part start set-up values for the three main standards SUB ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 VALUES (HEX) REGISTER FUNCTION chip version increment delay analog input control 1 analog input control 2 analog input control 3 analog input control 4 horizontal sync start horizontal sync stop sync control ID7 to ID4 X, WPOFF, GUDL1, GUDL0 and IDEL3 to IDEL0 FUSE1, FUSE0 and MODE5 to MODE0 X, HLNRS, VBSL, CPOFF, HOLDG, GAFIX, GAI28 and GAI18 GAI17 to GAI10 GAI27 to GAI20 HSB7 to HSB0 HSS7 to HSS0 AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 47 C0 10 90 90 EB E0 98 BIT NAME(1) NTSC M PAL B, D, G, H AND I read only 47 C0 10 90 90 EB E0 98 47 C0 10 90 90 EB E0 98 SECAM
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
SUB ADDRESS (HEX) 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A to 1D 1E 1F Note 1. All X values must be set to logic 0.
SAA7118E
VALUES (HEX) REGISTER FUNCTION luminance control luminance brightness control luminance contrast control chrominance saturation control chrominance hue control chrominance control 1 chrominance gain control chrominance control 2 mode/delay control RT signal control RT/X-port output control analog/ADC/compatibility control VGATE start, FID change VGATE stop miscellaneous, VGATE configuration and MSBs raw data gain control raw data offset control reserved status byte 1 video decoder status byte 2 video decoder BIT NAME(1) NTSC M BYPS, YCOMB, LDEL, LUBW and LUFI3 to LUFI0 DBRI7 to DBRI0 DCON7 to DCON0 DSAT7 to DSAT0 HUEC7 to HUEC0 CDTO, CSTD2 to CSTD0, DCVF, FCTC, AUTO0 and CCOMB ACGC and CGAIN6 to CGAIN0 OFFU1, OFFU0, OFFV1, OFFV0, CHBW and LCBW2 to LCBW0 COLO, RTP1, HDEL1, HDEL0, RTP0 and YDEL2 to YDEL0 RTSE13 to RTSE10 and RTSE03 to RTSE00 RTCE, XRHS, XRVS1, XRVS0, HLSEL and OFTS2 to OFTS0 CM99, UPTCV, AOSL1, AOSL0, XTOUTE, AUTO1, APCK1 and APCK0 VSTA7 to VSTA0 VSTO7 to VSTO0 LLCE, LLC2E, LATY2 to LATY0, VGPS, VSTO8 and VSTA8 RAWG7 to RAWG0 RAWO7 to RAWO0 X, X, X, X, X, X, X, X -, HLCK, SLTCA, GLIMT, GLIMB, WIPA, DCSTD1 and DCSTD0 INTL, HLVLN, FIDT, -, TYPE3, COLSTR, COPRO and RDCAP 40 80 44 40 00 89 2A 0E 00 00 00 00 11 FE C0 40 80 00 PAL B, D, G, H AND I 40 80 44 40 00 81 2A 06 00 00 00 00 11 FE C0 40 80 00 read only read only SECAM 1B 80 44 40 00 D0 80 00 00 00 00 00 11 FE C0 40 80 00
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Preliminary specification
Multistandard video decoder with adaptive comb filter and component video input
16.2 Component video part and interrupt mask
SAA7118E
The given values force the following behaviour of the SAA7118E component video part: * The analog inputs AI11, AI21, AI31 and AI41 expect an RGBS signal; analog anti-alias filters and AGC for the sync channel active * For other settings see decoder part (Section 16.1). Table 140 Component video part and interrupt mask start set-up values SUB ADDRESS (HEX) 23 24 25 26 to 28 29 2A 2B 2C 2D 2E 2F Note 1. All X values must be set to logic 0. REGISTER FUNCTION analog input control 5 analog input control 6 analog input control 7 reserved component delay component contrast control component saturation control interrupt mask 1 interrupt mask 2 interrupt mask 3 BIT NAME(1) AOSL2, ADPE, EXCLK, REFA, X, EXMCE, GAI48 and GAI38 GAI37 to GAI30 GAI47 to GAI40 X, X, X, X, X, X, X, X FSWE, FSWI, FSWDL1, FSWDL0, CMFI, CPDL2 to CPDL0 CCON7 to CCON0 CSAT7 to CSAT0 X, X, X, MVPSV, MPPV, MCCV, X and MERROF X, MHLCK, X, X, X, X, MDCSTD1 and MDCSTD0 MINTL, MHLVLN, MFIDT, X, MTYPE3, MCOLSTR, MCOPRO and MRDCAP VALUES (HEX) 00 90 90 00 00 80 40 47 00 00 00
component brightness control CBRI7 to CBRI0
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16.3 Audio clock generation part
SAA7118E
The given values force the following behaviour of the SAA7118E audio clock generation part: * Used crystal is 24.576 MHz * Expected field frequency is 59.94 Hz (e.g. NTSC M standard) * Generated audio master clock frequency at pin AMCLK is 256 x 44.1 kHz = 11.2896 MHz * AMCLK is externally connected to AMXCLK (short-cut between pins P11 and M12) * ASCLK = 32 x 44.1 kHz = 1.4112 MHz * ALRCLK is 44.1 kHz. Table 141 Audio clock part set-up values SUB ADDRESS (HEX) 30 31 32 33 34 35 36 37 38 39 3A 3B to 3F Note 1. All X values must be set to logic 0. START VALUES REGISTER FUNCTION audio master clock cycles per field; bits 7 to 0 audio master clock cycles per field; bits 15 to 8 audio master clock cycles per field; bits 17 and 16 reserved audio master clock nominal increment; bits 7 to 0 audio master clock nominal increment; bits 15 to 8 audio master clock nominal increment; bits 21 to 16 reserved clock ratio AMXCLK to ASCLK clock ratio ASCLK to ALRCLK audio clock generator basic set-up reserved BIT NAME(1) 7 ACPF7 to ACPF0 ACPF15 to ACPF8 X, X, X, X, X, X, ACPF17 and ACPF16 X, X, X, X, X, X, X, X ACNI7 to ACNI0 ACNI15 to ACNI8 X, X, ACNI21 to ACNI16 X, X, X, X, X, X, X, X X, X, SDIV5 to SDIV0 X, X, LRDIV5 to LRDIV0 X, X, X, X, APLL, AMVR, LRPH, SCPH X, X, X, X, X, X, X, X 1 1 0 0 1 1 0 0 0 0 0 0 6 0 1 0 0 1 1 0 0 0 0 0 0 5 1 0 0 0 0 0 1 0 0 0 0 0 4 1 1 0 0 0 0 1 0 0 1 0 0 3 1 1 0 0 1 1 1 0 0 0 0 0 2 1 1 0 0 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 HEX BC DF 02 00 CD CC 3A 00 03 10 00 00
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Multistandard video decoder with adaptive comb filter and component video input
16.4 Data slicer and data type control part
SAA7118E
The given values force the following behaviour of the SAA7118E VBI-data slicer part: * Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system) * All other lines are processed as active video * Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH MSB of SAV/EAV = 1). Table 142 Data slicer start set-up values SUB ADDRESS (HEX) 40 41 to 53 54 55 to 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 Notes 1. All X values must be set to logic 0. 2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H. START VALUES REGISTER FUNCTION slicer control 1 line control register 2 to 20 line control register 21 line control register 22 to 24 programmable framing code horizontal offset for slicer vertical offset for slicer field offset and MSBs for horizontal and vertical offset reserved header and data identification code control reserved slicer status byte 0 slicer status byte 1 slicer status byte 2 BIT NAME(1) 7 X, HAM_N, FCE, HUNT_N, X, X, X, X LCRn_7 to LCRn_0 (n = 2 to 20) LCR21_7 to LCR21_0 LCRn_7 to LCRn_0 (n = 22 to 24) FC7 to FC0 HOFF7 to HOFF0 VOFF7 to VOFF0 FOFF, RECODE, X, VOFF8, X, HOFF10 to HOFF8 X, X, X, X, X, X, X, X FVREF, X, DID5 to DID0 0 1 0 1 0 0 0 1 0 0 0 0 6 1 1 1 1 0 1 0 0 0 0 0 0 5 0 1 0 1 0 0 0 0 0 1 0 0 4 0 1 1 1 0 0 0 0 0 1 0 0 3 0 1 1 1 0 0 0 0 0 1 0 0 2 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 HEX 40 FF 5F FF 00 47 06(2) 83(2) 00 3E 00 00
sliced data identification code X, X, SDID5 to SDID0 X, X, X, X, X, X, X, X -, FC8V, FC7V, VPSV, PPV, CCV, -, - -, -, F21_N, LN8 to LN4 LN3 to LN0, DT3 to DT0
read-only register read-only register read-only register
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Multistandard video decoder with adaptive comb filter and component video input
16.5 Scaler and interfaces 16.5.1 TRIGGER CONDITION
SAA7118E
Table 143 shows some examples for the scaler programming with: * prsc = prescale ratio * fisc = fine scale ratio * vsc = vertical scale ratio. number of input pixel The ratio is defined as: ---------------------------------------------------------number of output pixel In the following settings the VBI-data slicer is inactive. To activate the VBI-data slicer, VITX[1:0] 86H[7:6] has to be set to `11'. Depending on the VBI-data slicer settings, the sliced VBI-data is inserted after the end of the scaled video lines, if the regions of VBI-data slicer and scaler overlaps. To compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288, respectively 240 lines. 16.5.3 EXAMPLES
For trigger condition STRC[1:0] 90H[1:0] not equal to `00'. If the value of (YO + YS) is greater than or equal to 262 (NTSC), respectively 312 (PAL) the output field rate is reduced to 30 Hz, respectively 25 Hz. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window. As this adjustment is application dependent, the listed values are only dummy values. 16.5.2 MAXIMUM ZOOM FACTOR
The maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8 or 16-bit output). The maximum horizontal zoom is limited to approximately 3.5, due to internal data path restrictions.
Table 143 Example of configurations EXAMPLE NUMBER 1 SCALER SOURCE AND REFERENCE EVENTS analog input to 8-bit I-port output, with SAV/EAV codes, 8-bit serial byte stream decoder output at X-port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V-gates on IGPH and IGPV, IGP0 = VBI sliced data flag, IGP1 = FIFO almost full, level 24, IDQ qualifier logic 1 active INPUT OUTPUT WINDOW WINDOW SCALE RATIOS
720 x 240 720 x 240 prsc = 1; fisc = 1; vsc = 1
2
analog input to 16-bit output, without SAV/EAV codes, Y on 704 x 288 768 x 288 prsc = 1; I-port, CB-CR on H-port and decoder output at X-port; fisc = 0.91667; acquisition trigger at falling edge vertical and rising edge vsc = 1 horizontal reference signal; H and V-pulses on IGPH and IGPV, output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active X-port input 8-bit with SAV/EAV codes, no reference signals on 720 x 240 352 x 288 prsc = 2; XRH and XRV, XCLK as gated clock; field detection and fisc = 1.022; acquisition trigger on different events; acquisition triggers at vsc = 0.8333 rising edge vertical and rising edge horizontal; I-port output 8-bit with SAV/EAV codes like example number 1 X-port and H-port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 16-bit output selected); XRH and XRV as references; field detection and acquisition trigger at falling edge vertical and rising edge horizontal; I-port output 8-bit with SAV/EAV codes, but Y only output 720 x 288 200 x 80 prsc = 2; fisc = 1.8; vsc = 3.6
3
4
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Multistandard video decoder with adaptive comb filter and component video input
Table 144 Scaler and interface configuration example I2C-BUS ADDRESS (HEX) Global settings 80 83 84 85 86 87 task enable, IDQ and back-end clock definition XCLK output phase and X-port output enable IGPH, IGPV, IGP0 and IGP1 output definition signal polarity control and I-port byte swapping FIFO flag thresholds and video/text arbitration ICLK and IDQ output phase and I-port enable 10 01 A0 10 45 01A [B2H[ 3:0]] B [E2 H[3:0]] F0 - - - - - - 10 01 C5 09 40 01 - - - - - - 10 00 A0 10 45 01 EXAMPLE 1 MAIN FUNCTIONALITY HEX DEC HEX DEC HEX
SAA7118E
EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 DEC HEX DEC
- - - - - -
10 00 A0 10 45 01
- - - - - -
88
power save control and software reset
- - - - - 16 - 720 - 10 - 242 - 720 - 240 -
F0
- - - - - 16 - 704 - 10 - 290 - 768 - 288 -
F0
- - - - - 16 - 720 - 10 - 242 - 352 - 288 -
F0
- - - - - 16 - 720 - 10 - 290 - 200 - 80 -
Task A: scaler input configuration and output format settings 90 91 92 93 task handling scaler input source and format definition reference signal definition at scaler input I-port output formats and configuration 00 08 10 80 00 08 10 40 00 18 10 80 00 38 10 84
Input and output window definition 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F horizontal output (destination) window length (XD) vertical output (destination) window length (YD) vertical input (source) window length (YS) vertical input offset (YO) horizontal input (source) window length (XS) horizontal input offset (XO) 10 00 D0 02 0A 00 F2 00 D0 02 F0 00 10 00 C0 02 0A 00 22 01 00 03 20 01 10 00 D0 02 0A 00 F2 00 60 01 20 01 10 00 D0 02 0A 00 22 01 C8 00 50 00
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Multistandard video decoder with adaptive comb filter and component video input
I2C-BUS ADDRESS (HEX) EXAMPLE 1 MAIN FUNCTIONALITY HEX DEC HEX DEC HEX
SAA7118E
EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 DEC HEX DEC
Prefiltering and prescaling A0 A1 A2 A4 A5 A6 integer prescale (value `00' not allowed) accumulation length for prescaler FIR prefilter and prescaler DC normalization scaler brightness control scaler contrast control scaler saturation control 01 00 00 80 40 40 - - - 128 64 64 01 00 00 80 40 40 - - - 128 64 64 02 02 AA 80 40 40 - - - 128 64 64 02 03 F2 80 11 11 - - - 128 17 17
Horizontal phase scaling A8 A9 AA AC AD AE horizontal phase offset luminance horizontal scaling increment for chrominance horizontal phase offset chrominance horizontal scaling increment for luminance 00 04 00 00 02 00 1024 - - 512 - - 1024 - 1024 - - AA 03 00 D5 01 00 938 - - 469 - - 1024 - 1024 - - 18 04 00 0C 02 00 1048 - - 524 - - 853 - 853 - - 34 07 00 9A 03 00 1844 - - 922 - - 3686 - 3686 - -
Vertical scaling B0 B1 B2 B3 B4 B8 to BF vertical scaling mode control vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) vertical scaling increment for chrominance vertical scaling increment for luminance 00 04 00 04 00 00 04 00 04 00 55 03 55 03 00 66 0E 66 0E 01
start with B8 to BF at 00H, if there are no problems with the interlaced scaled output optimize according to Section 8.4.3.2
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17 PACKAGE OUTLINE BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
D D1 B A
SAA7118E
SOT472-1
ball A1 index area A E1 E A1 detail X A2
k
k e1 e P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.75 A1 0.5 0.3 A2 1.25 1.05 b 0.6 0.4 D 15.2 14.8 D1 13.7 13.0 E 15.2 14.8 E1 13.7 13.0 e 1.0 e1 13.0 k 1.65 1.10 v 0.3 w 0.1 y 0.15 y1 0.35 5 scale 10 mm X vMB b
w M
C y1 C y
vMA
e
e1
OUTLINE VERSION SOT472-1
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-12-02 00-03-04
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Multistandard video decoder with adaptive comb filter and component video input
18 SOLDERING 18.1 Introduction to soldering surface mount packages
SAA7118E
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Multistandard video decoder with adaptive comb filter and component video input
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SAA7118E
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Multistandard video decoder with adaptive comb filter and component video input
19 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
SAA7118E
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 20 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 PURCHASE OF PHILIPS I2C COMPONENTS 21 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Multistandard video decoder with adaptive comb filter and component video input
NOTES
SAA7118E
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Multistandard video decoder with adaptive comb filter and component video input
NOTES
SAA7118E
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/03/pp168
Date of release: 2000
Nov 27
Document order number:
9397 750 07787

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