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| CMOS RAM SAE 81C54 Preliminary DataACMOS IC Features q q q q q q q q q q 512 x 8 bit-organization Multiplexed address and data bus Tristate address and data lines On-chip address register Very low current consumption: 1 A at 5.5 V during standby Dual chip selection Wide supply voltage range from 2.5 V to 5.5 V Fully compatible 5 V 10 % Data retention up to 1.0 V Temperature range - 40 to 110 C P-DIP-16-1 Type SAE 81C54 P Ordering Code Q67100-H8486 Package P-DIP-16-1 The SAE 81C54 P is a static 4096-bit RAM (512 words by 8 bits) in Advanced CMOS technology. The address and data bus in the multiplex operation allows directly interfaces to 8-bit microprocessors/microcontroller families, e.g. SAB 8086, SAB 8088, SAB 8051. Due to its low power dissipation of less than 1 A in standby mode this component requires only minimum supply current. Semiconductor Group 1 09.94 SAE 81C54 Pin Configurations (top view) Pin Definitions and Functions Pin No. 1-7, 10 8 9 11 12 13 14 15 16 Symbol AD0-7 Function Address/data lines Ground Chip select Address line Chip select Address signal latch enable Write enable Read enable Supply voltage VSS CS A8 CS ALE WR RD VDD Semiconductor Group 2 SAE 81C54 Logic Symbol Truth Table for Control and Data Bus Pin Status CS H X L L CS X L H H RD X X L H WR X X H L AD0-7 During Data Phase Floating Floating Data from memory Data to memory Function None None Read Write Semiconductor Group 3 SAE 81C54 Block Diagram Semiconductor Group 4 SAE 81C54 Absolute Maximum Ratings Parameter Ambient temperature Storage temperature range Thermal resistance system - air Symbol Limit Values - 40 to 110 - 55 to 125 70 Unit C C K/W TA Tstg Rth SA DC Characteristics TA = - 40 to 110 C; VDD = 2.5 to 5.5 V; VSS = 0 V Parameter Symbol min. Standby supply current Operating supply current Operating supply voltage Standby supply voltage Input current Output leakage current L-input voltage (VDD < 4.5 V) L-input voltage (VDD > 4.5 V) H-input voltage H-input voltage Limit Values typ. max. 1 500 2.5 1.0 5.5 5.5 1 1 - 0.8 - 0.8 0.6 x VDD 0.6 0.8 Unit Test Condition A A V V A A V V V V Data retention IDD IDD VDD VDD IIL IQL VI VIL VIH VIH TA = 25 C 100-kHz ALE VI = 0 - 5.5 V VQ = 0 - 5.5 V floating VDD + 0.8 VDD + 0.8 VDD = 5 V Semiconductor Group 5 SAE 81C54 DC Characteristics (cont'd) TA = - 40 to 110 C; VDD = 2.5 to 5.5 V; VSS = 0 V Parameter Symbol min. L-output voltage (VDD < 4.5 V) L-output voltage (VDD > 4.5 V) H-output voltage (VDD < 4.5 V) H-output voltage (VDD > 4.5 V) Limit Values typ. max. 0.4 0.4 0.75 x VDD 0.75 x VDD Unit Test Condition V V V V VQL VQL VQH VQH IQL = 1 mA IQL = 2 mA IQH = 1 mA IQH = 2 mA AC Characteristics TA = - 40 to 110 C; VDD = 4.5 to 5.5 V; VSS = 0 V Parameter Symbol min. ALE pulse width Address setup before ALE Address hold after ALE WR pulse width RD pulse width Data setup before WR Data hold after WR Data hold after RD Access time RD to data output Address floating to RD CS before ALE CS after WR or RD ALE to RD or WR RD or WR to ALE = high Limit Values max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tLL tAL tLA tCC tCW tDW tWD tDR tRD tAFC tCS tSC tLC tCL 40 25 25 60 130 70 20 30 130 0 30 10 35 25 Semiconductor Group 6 SAE 81C54 AC Characteristics TA = - 40 to 110 C; VDD = 2.5 to 5.5 V; VSS = 0 V Parameter Symbol min. ALE pulse width Address setup before ALE Address hold after ALE WR pulse width RD pulse width Data setup before WR Data hold after WR Data hold after RD Access time RD to data output Address floating to RD CS before ALE CS after WR or RD ALE to RD or WR RD or WR to ALE = high Limit Values max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tLL tAL tLA tCC tCW tDW tWD tDR tRD tAFC tCS tSC tLC tCL 60 40 60 200 350 200 60 95 350 0 80 30 60 30 Semiconductor Group 7 SAE 81C54 Diagrams Semiconductor Group 8 |
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