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54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
D D D D D D D D
Members of the Texas Instruments WidebusTM Family Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54ACT16544 . . . WD PACKAGE 74ACT16544 . . . DL PACKAGE (TOP VIEW)
description
The 'ACT16544 are 16-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. They can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data to B. Having CEAB low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition at LEAB puts the A latches in the storage mode. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs.
1OEAB 1LEAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2LEAB 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2LEBA 2OEBA
The 74ACT16544 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16544 is characterized for operation over the full military temperature range of -55C to 125C. The 74ACT16544 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
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54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
FUNCTION TABLE INPUTS CEAB H L L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 H
L A-to-B data flow is shown: B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
logic symbol
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 29 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 9 12D 1 1 11D 10 31 30 28 26 27 55 1 3 2 56 54 1 EN3 G1 1 C5 2 EN4 G2 2 C6 7 EN9 G7 7 C11 8 EN10 G8 8 C12 3 6D 1 1 5D 4 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
logic diagram (positive logic)
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 2 5 C1 1D 52 1B1 56 54 55 1 3
C1 1D
To Seven Other Channels 29 31 30 28 26 2CEAB 2LEAB 2A1 27 15 C1 1D 42 2B1
2OEBA 2CEBA 2LEBA 2OEAB
C1 1D
To Seven Other Channels
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Input voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Maximum power package dissipation at TA = 55C (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16544 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 -55 0 0 4.5 2 0.8 VCC VCC -24 24 10 125 0 -40 0 0 NOM 5 MAX 5.5 74ACT16544 MIN 4.5 2 0.8 VCC VCC -24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A 50 VOH IOH = -24 mA 24 IOH = -75 mA IOL = 50 A VOL IOL = 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND Control inputs A or B ports VI = VCC or GND VO = VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 5V 4.5 12 0.1 0.5 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25C TYP MAX 54ACT16544 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 MAX 74ACT16544 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 A A A mA pF pF V V MAX UNIT
II IOZ ICC ICC Ci Cio
Control inputs A or B ports
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration Setup time Hold time LEAB or LEBA low Data before LEAB or LEBA Data before CEAB or CEBA Data after LEAB or LEBA Data after CEAB or CEBA 5.5 1.5 1.5 3 3 54ACT16544 MIN 5.5 1.5 1.5 3 3 MAX 74ACT16544 MIN 5.5 1.5 1.5 3 3 MAX UNIT ns ns ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B A or B A or B A or B MIN 2.8 4 2.7 2.8 3.2 3.8 5.8 5 2.8 3.6 5.2 3.4 TA = 25C TYP MAX 6.7 7.5 9 8.5 7.2 8.2 8.2 7.4 6.9 7.9 7.7 6.8 10 10 13.3 12.1 10.5 12 10.3 9.4 10.2 11.7 9.8 8.8 54ACT16544 MIN 2.8 4 2.7 2.8 3.2 3.8 5.8 5 2.8 3.6 5.2 3.4 MAX 11.2 11.2 14 13.5 11.7 13.6 11.1 10.2 11.4 13.3 10.5 9.6 74ACT16544 MIN 2.8 4 2.7 2.8 3.2 3.8 5.8 5 2.8 3.6 5.2 3.4 MAX 11.2 11.2 14 13.5 11.7 13.6 11.1 10.2 11.4 13.3 10.5 9.6 UNIT ns ns ns ns ns ns
LEBA or LEAB CEBA or CEAB CEBA or CEAB OEBA or OEAB OEBA or OEAB
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 60 13 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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54ACT16544, 74ACT16544 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS161A - AUGUST 1990 - REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V Input 1.5 V tPHL 1.5 V 0V tPLH VOH 50% VCC VOL Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH VOLTAGE WAVEFORMS Data Input tsu 1.5 V 1.5 V
3V 0V th 3V 1.5 V 0V
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VCC
VOL
Output
50% VCC
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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