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74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
* * * * * * * *
Inputs Are TTL-Voltage Compatible 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Asynchronous Clear Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125C
DW PACKAGE (TOP VIEW)
description
The 74ACT11874 contains dual 4-bit registers featuring 3-state outputs designed specifically for bus driving. This makes this device particularly suitable for implementing buffer registers, I/O ports, and working registers.
1CLK 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1OE 1CLR 1D1 1D2 1D3 1D4 VCC VCC 2D1 2D2 2D3 2D4 2CLR 2OE
The D-type edge-triggered flip-flops enter data on the low-to-high transition of the clock. The 74ACT11874 has CLR inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock. The 74ACT11874 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L L H CLR L H H H X CLK X L X D X H L X X OUTPUT Q L H L Q0 Z
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
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74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
logic symbol
1OE 1CLK 1CLR 1D1 1D2 1D3 1D4 28 1 27 23 22 21 20 EN C1 R 1D 1 2 3 4 5 1Q1 1Q2 1Q3 1Q4
logic diagram (each 4-bits) (positive logic)
OE CLK CLR R C1 D1 1D Q1
2OE 2CLK 2CLR 2D1 2D2 2D3 2D4
15 14 16 20 19 18 17
EN C1 R 1D 1 10 11 12 13 2Q1 2Q2 2Q3 2Q4 D3 D2
R C1 1D
Q2
R C1 1D
Q3
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. D4
R C1 1D
Q4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
recommended operating conditions
MIN VCC VIH VIL VI VO IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 - 40 0 0 4.5 2 0.8 VCC VCC - 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V C
Dt/Dv
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 3V IOH = - 50 mA VOH IOH = - 4 mA IOH = - 24 mA IOH = - 75 mA IOL = 50 mA VOL IOL = 12 mA IOL = 24 mA IOL = 75 mA IOZ II ICC Ci VO = VCC or GND VI = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 0.5 0.1 8 0.1 0.1 0.1 0.36 0.36 0.36 MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25C TYP MAX MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 5 1 80 V V MAX UNIT
mA mA mA
pF pF
Co VO = VCC or GND 5V 10 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-3
74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
MIN fclock tw tsu th Clock frequency Pulse duration CLR low CLK high or low Data Setup time before CLK Hold time after CLK CLR low Data 0 2 2 1 2 2 TA = 25C TYP MAX 125 MIN 0 4 4 5 2 1 ns ns MAX 125 UNIT MHz ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 125 CLK CLR OE OE Any Q Any Q Any Q Any Q 7.5 8.1 8.8 6.4 8.6 6.9 6.8 TA = 25C TYP MAX MIN 125 3.7 4.1 3.5 1.6 2.4 5.4 4.9 9.4 10.6 11.8 7.4 9.5 9.4 9.1 MAX UNIT MHz ns ns ns ns
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 76 64 UNIT pF
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74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT Timing Input (see Note B) tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
Input (see Note B) tPLH In-Phase Output tPHL Out-of-Phase Output
3V 1.5 V 1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
Output Control (low-level enabling) Output Waveform 1 S1 at 2 x VCC (see Note C) Output Waveform 2 S1 at GND (see Note C)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VCC
VOL
tPZH
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS212 - D3447, MARCH 1990 - REVISED APRIL 1993
2-6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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