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74AC11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS236 - MARCH 1990 - REVISED APRIL 1993
* * * * * * *
3-State Buffer-Type Outputs Drive Bus Lines Directly Asynchronous Clear Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR NT PACKAGE (TOP VIEW)
description
1CLK 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1OE 1CLR 1D1 1D2 1D3 1D4 VCC VCC 2D1 2D2 2D3 2D4 2CLR 2OE
This dual 4-bit D-type edge-triggered flip-flop features 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, and working registers. The flip-flops enter data on the low-to-high transition of the clock. The 74AC11874 has clear (1CLR and 2CLR) inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock. The 74AC11874 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each 4-bit flip-flop) INPUTS OE L L L L H CLR L H H H X CLK X L X D X H L X X OUTPUT Q L H L Q0 Z
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
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74AC11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS236 - MARCH 1990 - REVISED APRIL 1993
logic symbol
28 1OE 1CLK 1CLR 1D1 1D2 1D3 1D4 1 27 26 25 24 23 EN C1 R 1D 1 2 3 4 5 1Q1 1Q2 1Q3 1Q4
logic diagram, each quad flip-flop (positive logic)
OE
CLK
CLR D1
R C1 1D Q1
R 15 2OE 2CLK 2CLR 2D1 2D2 2D3 2D4 14 16 20 19 18 17 EN C1 R 1D 1 10 11 12 13 R 2Q1 2Q2 2Q3 2Q4 R C1 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. D4 1D Q4 D3 C1 1D Q3 D2 C1 1D Q2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
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74AC11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS236 - MARCH 1990 - REVISED APRIL 1993
recommended operating conditions
MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VCC = 4.5 V VCC = 5.5 V VI VO IOH Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VCC = 4.5 V VCC = 5.5 V 0 - 40 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC -4 - 24 - 24 12 24 24 10 85 ns/V C mA mA V V V V NOM 5 MAX 5.5 UNIT V
VIL
Low-level input voltage
IOL t/v TA
Low-level output current Input transition rise or fall rate Operating free-air temperature
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 3V IOH = - 50 A VOH IOH = - 4 mA IOH = - 24 mA A IOH = - 75 mA IOL = 50 A VOL IOL = 12 mA IOL = 24 mA IOL = 75 mA II IOZ ICC Ci VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4.5 0.1 0.5 8 0.1 0.1 0.1 0.36 0.36 0.36 TA = 25C MIN TYP MAX 2.9 4.4 5.4 2.58 3.94 4.94 MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 1 5 80 A A A pF pF V V MAX UNIT
Co VO = VCC or GND 5V 13.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
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74AC11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS236 - MARCH 1990 - REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time before CLK Hold time after CLK CLR low CLK high or low Data CLR inactive Data 0 4 8.3 3 1.5 1 60 MIN 0 4 8.3 3 1.5 1 MAX 60 UNIT MHz ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time before CLK Hold time after CLK CLR low CLK high or low Data CLR inactive Data 0 4 4 2 1.5 1 125 MIN 0 4 4 2 1.5 1 MAX 125 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 60 CLK CLR OE OE Q Q Q Q 2.9 3.7 3.9 2.1 3.1 4 3.9 7.3 8.8 9.3 5.6 8.4 6.2 6.3 11 13.1 14 8.7 13.1 8.2 8.5 TA = 25C TYP MAX MIN 60 2.9 3.7 3.9 2.1 3.1 4 3.9 12.5 14.6 15.7 9.8 14.9 8.7 9 MAX UNIT MHz ns ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 125 CLK CLR OE OE Q Q Q Q 2.3 2.9 2.9 1.5 2.3 3.8 3.7 5.2 6.1 6.3 4 5.4 5.7 5.5 7.4 8.6 8.9 5.9 7.8 7.3 7.1 TA = 25C TYP MAX MIN 125 2.3 2.9 2.9 1.5 2.3 3.8 3.7 8.3 9.6 10 6.6 8.8 7.7 7.5 MAX UNIT MHz ns ns ns ns
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
74AC11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS236 - MARCH 1990 - REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per flip-flop flip flop Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 31 13 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT FOR OUTPUTS Input VCC Timing Input 50% 0V tsu Data Input 50% th VCC 50% 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC 50% 50% 0V tPLH tPHL VOH 50%VCC VOL Output Waveform 2 S1 at GND (see Note C) 50%
tw VCC 50% 0V VOLTAGE WAVEFORMS PULSE DURATION
VCC 50% 50% 0V tPLZ VCC 50%VCC tPHZ VOH 50%VCC 80%VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 20%VCC VOL
Input (see Note B)
Output Waveform 1 S1 at 2 x VCC (see Note C) tPZH
Output (see Note D)
50%VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 3 ns, tf 3 ns. For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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