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54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
D D D D D D D D
Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54ACT16474 . . . WD PACKAGE 74ACT16474 . . . DL PACKAGE (TOP VIEW)
description
The 'ACT16474 are noninverting 18-bit registered bus transceivers composed of two 9-bit sections with separate control signals. For either 9-bit transceiver section, data flow in the A-to-B mode is controlled by output-enable (1OEAB or 2OEAB) and clock (1CLKAB or 2CLKAB) inputs. When 1OEAB or 2OEAB is low, the corresponding outputs are active (high or low) and take on either the current data on low-to-high transition of 1CLKAB or 2CLKAB or the previously stored data if 1CLKAB or 2CLKAB is low.
1OEAB 1CLKAB 1A1 GND 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 1A9 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2CLKAB 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1CLKBA 1B1 GND 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 1B9 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2B9 2CLKBA 2OEBA
When 1OEAB or 2OEAB is high, the corresponding outputs are in the high-impedance state. 1OEAB or 2OEAB does not affect the operation on the internal registers. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Data flow from B to A is similar, but uses 1OEBA and/or 2OEBA and 1CLKBA and/or 2CLKBA. The 74ACT16474 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16474 is characterized for operation over the full military temperature range of -55C to 125C. The 74ACT16474 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
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54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
FUNCTION TABLE INPUTS CLKAB X L OEAB H L L L A X X H OUTPUT B Z B0 H
L L A-to-B data flow is shown: B-to-A flow is similar but uses CLKBA, and OEBA. Output level before the indicated steadystate input conditions were established
logic symbol
1CLKAB 1OEAB 1CLKBA 1OEBA 2CLKAB 2OEAB 2CLKBA 2OEBA 1A1 3 2 1 55 56 27 28 30 29 C1 EN2 C3 EN4 C5 EN6 C7 EN8 1D 4 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A1 5 6 8 9 10 12 13 14 15 5D 8 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 16 17 19 20 21 23 24 26 1 1 6 7D 41 40 38 37 36 34 33 31 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 1 1 2 5D 52 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 2B1 54 1B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
logic diagram (positive logic)
1CLKBA 55
1OEBA
56
1OEAB
1
1CLKAB
2 C1 1D
1A1
3
54
1B1
C1 1D
To Eight Other Channels 30 29
2CLKBA 2OEBA
2OEAB
28
2CLKAB
27
C1 1D 2A1 15 42 2B1
C1 1D
To Eight Other Channels
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Input voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mA Maximum package power dissipation at TA = 55C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16474 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 0 4.5 2 0.8 VCC VCC -24 24 10 125 0 -40 0 0 NOM 5 MAX 5.5 74ACT16474 MIN 4.5 2 0.8 VCC VCC -24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V C
TA Operating free-air temperature -55 NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A 50 VOH IOH = -24 mA 24 IOH = -75 mA IOL = 50 A VOL IOL = 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 3 0.1 0.5 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25C TYP MAX 54ACT16474 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 MAX 74ACT16474 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 A A A mA pF pF V V MAX UNIT
II IOZ ICC ICC Ci
Control inputs A or B ports
One input at 3.4 V, Other inputs at VCC or GND Control inputs VI = VCC or GND VO = VCC or GND
Cio A or B ports 5V 11.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time Hold time CLK high CLK low Data before CLK Data after CLK 0 4 6.6 5.5 1 75 54ACT16474 MIN 0 4 6.6 5.5 1 MAX 75 74ACT16474 MIN 0 4 6.6 5.5 1 MAX 75 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25C MIN TYP MAX 75 CLK A or B A or B A or B 4 4.2 3 3.7 4.8 4.4 8 8 7.8 9.2 7.1 6.6 10.2 10.2 10.3 11.6 8.8 8.4 54ACT16474 MIN 75 4 4.2 3 3.7 4.8 4.4 11.5 11.4 11.7 13.1 9.5 9 MAX 74ACT16474 MIN 75 4 4.2 3 3.7 4.8 4.4 11.5 11.4 11.7 13.1 9.5 9 MAX UNIT MHz ns ns ns
OE OE
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS238A - MAY 1992 - REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 61 37 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
3V Input 1.5 V tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
Output Control (low-level enabling) Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VCC
VOL
tPZH
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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