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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
D D D D D D D
Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability Mailbox Register in Each Direction Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic Input-Ready and Almost-Full Flags Synchronized by CLKA
D D D D D D
Output-Ready and Almost-Empty Flags Synchronized by CLKB Low-Power 0.8-m Advanced CMOS Technology Supports Clock Frequencies up to 67 MHz Fast Access Times of 11 ns Pin-to-Pin Compatible With the SN74ACT3641 and SN74ACT3651 Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages
description
The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 512 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is possible in word depth. The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input. The SN74ACT3631 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports:
D D D
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA007) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)
Metastability Performance of Clocked FIFOs (literature number SCZA004).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
PCB PACKAGE (TOP VIEW)
NC - No internal connection
2
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC
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B7 B8 B9 B10 B11
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
GND CLKA ENA W/RA CSA IR OR VCC AF AE VCC MBF2 MBA RST GND FS0/SD FS1/SEN RTM RFM VCC NC MBB GND MBF1 GND CSB W/RB ENB CLKB VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
PQ PACKAGE (TOP VIEW)
17 16 15 14 13 12 11 10 9
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC
NC NC VCC CLKB ENB W/RB CSB GND MBF1 GND MBB NC VCC RFM RTM FS1/SEN FS0/SD GND RST MBA MBF2 VCC AE AF VCC OR IR CSA W/RA ENA CLKA GND NC
8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118 129 121 119 131 127 125 123 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
NC - No internal connection Uses Yamaichi socket IC51-1324-828
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
functional block diagram
MBF1 Mail1 Register Port-A Control Logic
512 x 36 SRAM
RST
Reset Logic
Synch Retransmit Logic
Output Register
Input Register
CLKA CSA W/RA ENA MBA
36
RTM RFM
Write Pointer A0 - A35 IR AF
Read Pointer
B0 - B35 Status-Flag Logic OR AE
FS0/SD FS1/SEN 10
Flag-Offset Register Port-B Control Logic Mail2 Register
CLKB CSB W/RB ENB MBB
MBF2
4
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
Terminal Functions
TERMINAL NAME A0 - A35 AE AF B0 - B35 CLKA CLKB CSA CSB ENA ENB I/O I/O O O I/O I I I I I I DESCRIPTION Port-A data. The 36-bit bidirectional data port for side A. Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less than or equal to the value in the almost-empty offset register (X). Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y). Port-B data. The 36-bit bidirectional data port for side B. Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA. Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB. Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0 - A35 outputs are in the high-impedance state when CSA is high. Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0 - B35 outputs are in the high-impedance state when CSB is high. Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During a device reset, FS1/SEN and FS0/SD select the flag offset programming method. Three offset register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load. When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into the X- and Y-offset registers. The number of bit writes required to program the offset register is 18. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset. Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0 - B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO data for output. Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a reset. Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by a reset. Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory. Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data. Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection. Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO out of retransmit mode.
FS1/SEN, FS0/SD
I
IR MBA MBB
O I I
MBF1
O
MBF2
O
OR
O
RFM RST
I I
RTM
I
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Terminal Functions (Continued)
TERMINAL NAME W/RA W/RB I/O I I DESCRIPTION Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0 - A35 outputs are in the high-impedance state when W/RA is high. Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0 - B35 outputs are in the high-impedance state when W/RB is low.
detailed description
reset The SN74ACT3631 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR) flag high, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. almost-empty flag and almost-full flag offset programming Two registers in the SN74ACT3631 are used to hold the offset values for the almost-empty and almost-full flags. The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y. The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high transition on the RST input (see Table 1). Table 1. Flag Programming
FS1 H H L FS0 H L H RST X AND Y REGISTERS Serial load 64 8
L L Parallel load from port A X register holds the offset for AE; Y register holds the offset for AF.
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the SN74ACT3631 uses port-A inputs (A8 - A0). The highest number input is used as the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to 508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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serial load
To serially program the X and Y registers, the device is reset with FS0/SD and FS1/SEN high during the low-to-high transition of RST. After this reset is complete, the X- and Y-register values are loaded bitwise through FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Writes of 18 bits are needed to complete the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores the least-significant bit of the X register. Each register value can be programmed from 1 to 508. When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded to allow normal FIFO operation. FIFO write/read operation The state of the port-A data (A0 - A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0 - A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0 - A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the A0 - A35 inputs on a low-to-high transition of CLKA when CSA and the port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high (see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads. Table 2. Port-A Enable Function Table
CSA H L L L L L L L W/RA X H H H L L L L ENA X L H H L H L H MBA X X L H L L H H CLKA X X X X A0 - A35 OUTPUTS In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, mail2 register Active, mail2 register Active, mail2 register Active, mail2 register PORT FUNCTION None None FIFO write Mail1 write None None None Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0 - B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 - B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0 - B35 outputs are active when CSB is low and W/RB is high. Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high (see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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FIFO write/read operation (continued) Table 3. Port-B Enable Function Table
CSB H L L L L L L L W/RB X L L L H H H H ENB X L H H L H L H MBB X X L H L L H H CLKB X X X X B0 - B35 OUTPUTS In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO output register Active, FIFO output register Active, mail1 register Active, mail1 register PORT FUNCTION None None None Mail2 write None FIFO read None Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setup- and hold-time window of the cycle. When the output-ready (OR) flag is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB), write/read select (W/RB), enable (ENB), and mailbox select (MBB). synchronized FIFO flags Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flags' reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the number of words stored in memory. Table 4. FIFO Flag Operation
NUMBER OF WORDS IN FIFO 0 1 to X (X + 1) to [512 - (Y + 1)] (512 - Y) to 511 512 SYNCHRONIZED TO CLKB OR L H H H H AE L L H H H SYNCHRONIZED TO CLKA AF H H H L L IR H H H H
L X is the almost-empty offset for AE. Y is the almost-full offset for AF. When a word is present in the FIFO output register, its previous memory location is free.
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output-ready flag (OR)
The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore, an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition of CLKB occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register. A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 6).
input-ready flag (IR)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When the input-ready flag is high, a memory location is free in the SRAM to write new data. No memory locations are free when the input-ready flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of three cycles of CLKA; therefore, an input-ready flag is low if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second low-to-high transition on CLKA after the read sets the input-ready flag high, and data can be written in the following cycle. A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 7).
almost-empty flag (AE)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-empty flag is low when the FIFO contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of CLKB are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk(2), or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 8).
almost-full flag (AF)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full state is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-full flag is low when the number of words in the FIFO is greater than or equal to (512 - Y). The almost-full flag is high when the number of words in the FIFO is less than or equal to [512 - (Y + 1)]. A data word present in the FIFO output register has been read from memory.
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Two low-to-high transitions of CLKA are required after a FIFO read for its almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [512 - (Y + 1)] or fewer words remains low if two cycles of CLKA have not elapsed since the read that reduced the number of words in memory to [512 - (Y + 1)]. An almost-full flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words in memory to [512 - (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to [512 - (Y + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9). synchronous retransmit The synchronous-retransmit feature of the SN74ACT3631 allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode at any time and allow normal device operation. The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low. When two or more reads occur after the initial retransmit word, a retransmit is initiated by a low-to-high transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takes the FIFO out of retransmit mode. When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that stores (512 - Y) words after the first retransmit word. The IR flag is set low by the 512th write after the first retransmit word. When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising CLKB edge (see Figure 14). mailbox registers Two 36-bit bypass registers pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A low-to-high transition on CLKA writes A0 - A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0 - B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is low.
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When the port-B data (B0 - B35) outputs are active, the data on the bus comes from the FIFO output register when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data is always present on the port-A data (A0 - A35) outputs when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read and changes only when new data is written to the register.
CLKA th(RS) CLKB tsu(RS) RST FS1, FS0 th(FS) tsu(FS)
IR
OR
AE
AF MBF1, MBF2
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0,1 tpd(C-IR) tpd(C-IR) tpd(C-OR) tpd(R-F) tpd(R-F) tpd(R-F)
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
CLKA
4
RST tsu(FS) FS1, FS0 th(FS)
IR
ENA
A0 - A35
NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register bits on consecutive clock cycles.
CLKA
RST tpd(C-IR) IR tsu(FS) FS1/SEN th(SP) tsu(SEN) th(SEN) tsu(SEN) th(SEN)
FS0/SD
NOTE A: It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.
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tpd(C-IR) tsu(D) th(D) AF Offset (Y) AE Offset (X) First Word Stored in FIFO
Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A
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tsu(FS)
th(SD)
th(FS)
tsu(SD)
tsu(SD)
th(SD)
AF Offset (Y) MSB
AE Offset (X) LSB
Figure 3. Serially Programming the AF Flag and AE Flag Offset Values
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tsu(EN)
th(EN)
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
tc tw(CLKH) CLKA tw(CLKL)
IR
High tsu(EN) th(EN)
CSA tsu(EN) W/RA
tsu(EN)
MBA
tsu(EN)
ENA
tsu(D)
A0 - A35
W1
tc tw(CLKH) CLKB tw(CLKL)
OR
High
CSB
W/RB
MBB
tsu(EN) th(EN)
ENB
tpd(M-DV) B0 - B35
ten
W1
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th(EN) th(EN) th(EN) tsu(EN) th(EN) tsu(EN) th(EN) th(D) W2 No Operation
tsu(EN) th(EN)
tsu(EN)
ta
ta
No Operation
W2
W3
Figure 5. FIFO Read-Cycle Timing
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IIIIII IIIIII
III III IIIIII IIIIII IIIIIII IIIIIII IIIIII IIIIII IIIIIII IIIIIII
IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII III III
Figure 4. FIFO Write-Cycle Timing
th(EN)
tdis
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
tc tw(CLKH) CLKA tw(CLKL)
CSA W/RA MBA ENA
Low High tsu(EN)
th(EN) th(EN)
IR
A0 - A35
CLKB OR
CSB W/RB MBB
ENB
B0 - B35
tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), then the transition of OR high and the first word load to the output register can occur one CLKB cycle later than shown.
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tsu(EN) High tsu(D) th(D) W1 tsk(1) tw(CLKH) tc tw(CLKL) 2 1 3 tpd(C-OR) Old Data in FIFO Output Register Low tpd(C-OR) High Low tsu(EN) th(EN)
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ta Old Data in FIFO Output Register W1
Figure 6. OR-Flag Timing and First Data-Word Fall-Through When the FIFO Is Empty
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
tc tw(CLKH) CLKB CSB W/RB MBB ENB Low tw(CLKL)
High Low
OR
High
B0 - B35
FIFO Output Register tsk(1) tw(CLKH)
CLKA IR CSA W/RA MBA ENA Low High FIFO Full
tsu(EN) tsu(D)
A0 - A35
Write
tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown.
Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full
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ta Next Word From FIFO tc tw(CLKL) 1 tpd(C-IR) 2 tpd(C-IR) tsu(EN) th(EN) th(EN) th(D) 15
tsu(EN)
th(EN)
SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
CLKA
ENA
CLKB AE
ENB
tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(2), then AE can transition high one CLKB cycle later than shown. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 8. Timing for AE When FIFO Is Almost Empty
tsk(2) CLKA 1 2 tsu(EN) th(EN)
ENA
tpd(C-AF)
AF
[512 - (Y + 1)] Words in FIFO
(512 - Y) Words in FIFO
CLKB
ENB
tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 9. Timing for AF When the FIFO Is Almost Full
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tsu(EN)
th(EN)
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tsk(2) 1 X Words in FIFO
tsu(EN)
th(EN)
2 tpd(C-AE)
tpd(C-AE) (X + 1) Words in FIFO tsu(EN) th(EN)
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tpd(C-AF)
SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
CLKB tsu(EN) ENB th(EN) tsu(EN) th(EN)
tsu(EN)
th(EN)
RTM
tsu(EN)
RFM
OR
High ta ta W1
B0 - B35
W0 Initiate Retransmit Mode With W0 as First Word
NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown only to relate retransmit operations to the FIFO output register.
Figure 10. Retransmit Timing Showing Minimum Retransmit Length
CLKB
1
RTM
High tsu(RM) th(RM)
RFM
AE
X or Fewer Words From Empty
NOTE A: X is the value loaded in the AE flag offset register.
Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X
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II III IIII III IIII
tsu(EN) th(EN) th(EN) ta W2 Retransmit From Selected Position W0 End Retransmit Mode ta W1 2 tpd(C-AE) (X + 1) or More Words From Empty 17
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III III III III
SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
tsk(1) CLKA 1 tpd(C-IR) IR FIFO Filled to First Retransmit Word One or More Write Locations Available 2
CLKB tsu(EN) RTM th(EN)
tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown.
Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available
CLKA
AF
(512 - Y) or More Words Past First Retransmit Word
CLKB tsu(EN) RTM th(EN)
tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown. NOTE A: Y is the value loaded in the AF flag offset register.
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tsk(2) 1
2 tpd(C-AE) (Y + 1) or More Write Locations Available
IIIII IIII IIIII IIII
Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1) or More Write Locations Are Available
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
CLKA tsu(EN) CSA th(EN)
W/RA
MBA
ENA
tsu(D)
A0 - A35
W1
CLKB
MBF1 CSB
MBB ENB
ten B0 - B35
FIFO Output Register
Figure 14. Timing for Mail1 Register and MBF1 Flag
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IIII
W/RB
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th(D) tpd(C-MF) tpd(C-MF) tsu(EN) th(EN) tpd(M-DV) tpd(C-MR) tdis W1 (remains valid in mail1 register after read)
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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CLKB tsu(EN) CSB th(EN)
MBB
ENB
tsu(D)
B0 - B35
W1
CLKA
MBF2 CSA
MBA ENA
ten
tpd(C-MR)
A0 - A35
W1 (remains valid in mail2 register after read)
Figure 15. Timing for Mail2 Register and MBF2 Flag
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W/RA
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th(D) tpd(C-MF) tpd(C-MF) tsu(EN) th(EN) tdis
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W/RB
SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Package thermal impedance, qJA (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings can be exceeded provided the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 0 4.5 2 0.8 -4 8 70 MAX 5.5 UNIT V V V mA mA C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS IOH = - 4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 VI = VCC - 0.2 V or 0 CSA = VIH ICC VCC = 5.5 V, One input at 3 4 V 55V O i t t 3.4 V, Other in uts at VCC or GND inputs CSB = VIH CSA = VIL CSB = VIL A0 - A35 B0 - B35 A0 - A35 B0 - B35 4 8 0 0 1 1 1 pF pF mA MIN 2.4 0.5 5 5 400 TYP MAX UNIT V V A A A
All other inputs Ci Co VI = 0, VO = 0, f = 1 MHz f = 1 MHz
All typical values are at VCC = 5 V, TA = 25C. This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 16)
'ACT3631-15 MIN fclock tc tw(CH) tw(CL) tsu(D) tsu(SEN) tsu(EN2) tsu(RM) tsu(RS) tsu(FS) tsu(SD) tsu(EN1) th(D) th(EN1) th(EN2) th(RM) th(RS) th(FS) th(SP) th(SD) th(SEN) tsk(1) Clock frequency, CLKA or CLKB Clock cycle time, CLKA or CLKB Pulse duration, CLKA and CLKB high Pulse duration, CLKA and CLKB low Setup time, A0 - A35 before CLKA and B0 - B35 before CLKB Setup time, FS1/SEN before CLKA Setup time, CSA, W/RA, and MBA to CLKA; CSB, W/RB, and MBB before CLKB Setup time, RTM and RFM to CLKB Setup time, RST low before CLKA or CLKB Setup time, FS0 and FS1 before RST high Setup time, FS0/SD before CLKA Setup time, ENA to CLKA; ENB to CLKB Hold time, A0 - A35 after CLKA and B0 - B35 after CLKB Hold time, ENA after CLKA; ENB after CLKB Hold time, CSA, W/RA, and MBA after CLKA; CSB, W/RB, and MBB after CLKB Hold time, RTM and RFM after CLKB Hold time, RST low after CLKA or CLKB Hold time, FS0 and FS1 after RST high Hold time, FS1/SEN high after RST high Hold time, FS0/SD after CLKA Hold time, FS1/SEN after CLKA Skew time between CLKA and CLKB for OR and IR 15 6 6 7 5 7 6 5 9 5 5 0 0 0 0 5 0 0 0 0 9 MAX 66.7 20 8 8 7.5 6 7.5 6.5 6 10 6 6 0 0 0 0 6 0 0 0 0 11 'ACT3631-20 MIN MAX 50 30 12 12 8 7 8 7 7 11 7 7 0 0 0 0 7 0 0 0 0 13 'ACT3631-30 MIN MAX 33.4 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsk(2) Skew time between CLKA and CLKB for AE and AF 12 16 20 ns Requirement to count the clock edge as one of at least four needed to reset a FIFO Applies only when serial load method is used to program flag offset registers Skew time is not a timing constraint for proper device operation and is included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figures 1 through 15)
PARAMETER fmax ta tpd(C-IR) tpd(C-OR) tpd(C-AE) tpd(C-AF) tpd(C-MF) tpd(C-MR) tpd(M-DV) tpd(R-F) ten tdis 'ACT3631-15 MIN 66.7 Access time, CLKB to B0 - B35 Propagation delay time, CLKA to IR Propagation delay time, CLKB to OR Propagation delay time, CLKB to AE Propagation delay time, CLKA to AF Propagation delay time, CLKA to MBF1 low or MBF2 high and CLKB to MBF2 low or MBF1 high Propagation delay time, CLKA to B0 - B35 and CLKB to A0 - A35 Propagation delay time, MBB to B0 - B35 valid Propagation delay time, RST low to AE low and AF high Enable time, CSA and W/RA low to A0 - A35 active and CSB low and W/RB high to B0 - B35 active Disable time, CSA or W/RA high to A0 - A35 at high impedance and CSB high or W/RB low to B0 - B35 at high impedance 3 0 1 1 1 0 3 3 1 2 1 11 8 8 8 8 8 13.5 13 15 12 10 MAX 'ACT3631-20 MIN 50 3 0 1 1 1 0 3 3 1 2 1 13 10 10 10 10 10 15 15 20 13 11 0 1 1 1 0 3 3 1 2 1 MAX 'ACT3631-30 MIN 33.4 15 12 12 12 12 12 17 17 30 14 12 MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Writing data to the mail1 register when the B0 - B35 outputs are active and MBB is high Writing data to the mail2 register when the A0 - A35 outputs are active and MBA is high
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
5V
1100 From Output Under Test 680 30 pF (see Note A)
LOAD CIRCUIT
Timing Input tsu Data, Enable Input 1.5 V
3V 1.5 V th 1.5 V GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V tPLZ 1.5 V GND tPZL 1.5 V VOL tPZH VOH 1.5 V tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 0V 3V GND
High-Level Input
3V 1.5 V tw 1.5 V GND
3V Low-Level Input 1.5 V 1.5 V
3V GND VOLTAGE WAVEFORMS PULSE DURATIONS
Output Enable
Low-Level Output
3V Input tpd In-Phase Output 1.5 V 1.5 V 1.5 V GND tpd VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
High-Level Output
NOTES: A. Includes probe and jig capacitance B. tPZL and tPZH are the same as ten. C. tPLZ and tPHZ are the same as tdis.
Figure 16. Load Circuit and Voltage Waveforms
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SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G - AUGUST 1993 - REVISED APRIL 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs CLOCK FREQUENCY
250 fdata = 1/2 fclock TA = 25C CL = 0 pF VCC = 5 V 150 VCC = 4.5 V 100
VCC = 5.5 V
I CC(f) - Supply Current - mA
200
50
0 0 10 20 30 40 50 60 70 fclock - Clock Frequency - MHz
Figure 17
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Copyright (c) 1999, Texas Instruments Incorporated

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