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SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS307A - MARCH 1993 - REVISED JULY 1995
D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE
description
This 10-bit bus-interface D-type latch is designed for 2.7-V to 3.6-V VCC operation; it can interface to a 5-V system environment. The SN74LVC841 is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output-enable (OE) input does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC841 is characterized for operation from - 40C to 85C.
FUNCTION TABLE INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1995, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS307A - MARCH 1993 - REVISED JULY 1995
logic symbol
OE LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 13 2 3 4 5 6 7 8 9 10 11 EN C1 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
PRODUCT PREVIEW
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE 1
LE
13
C1 1D 2 1D
23
1Q
To Nine Other Channels
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS307A - MARCH 1993 - REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Voltage range applied to any output in the high impedance state or power off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate High or low state 3 state VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 Operating Data retention only VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2 1.5 2 0.8 0 0 0 5.5 VCC 5.5 - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
PRODUCT PREVIEW
SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS307A - MARCH 1993 - REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC Ci Co IOL = 12 mA IOL = 24 mA VI = 5.5 V or GND VO = 5.5 V or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V 2.7 V to 3.6 V 3.3 V 3.3 V MIN TYP MAX UNIT VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.55 5 10 10 500 A A A A pF pF V
V
nICC
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V, TA = 25C.
PRODUCT PREVIEW
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POST OFFICE BOX 655303
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Copyright (c) 1999, Texas Instruments Incorporated

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