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CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
* * * * * * * * *
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Two Banks Distribute One Clock Input to Three Same-Frequency Clock Outputs One Bank Distributes One Clock Input to Four Half-Frequency Clock Outputs Internal Power-Up Circuit Distributed VCC and Ground Pins Reduce Switching Noise Symmetrical Output Drive (- 32-mA IOH, 32-mA IOL) State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Packaged in Plastic Small-Outline Package
DW PACKAGE (TOP VIEW)
GND 1Y1 1Y2 GND 2Q1 2OE 2A 2Q2 GND 3Y1 3Y2 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
1OE 1Y3 1A VCC PRE 2Q3 GND 2Q4 VCC 3OE 3Y3 3A
description
The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring output signals at both the primary clock frequency and one-half the primary clock frequency. This device contains two banks that fan out one input to three same-frequency outputs and one bank that fans out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the frequency of their clock (2A) input. When the output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to the high level. When a bank's OE input is high, the outputs are in the high-impedance state. The CDC330 is characterized for operation from 0C to 70C.
FUNCTION TABLES INPUTS nOE H L L n = 1, 3 INPUTS 2OE H L L PRE X L H 2A X L OUTPUTS 2Q1 - 2Q3 Z H Toggle nA X L H OUTPUTS nY1 - nY3 Z L H
EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
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CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
logic symbol
1A 22 2 3 24 7 2A 20 PRE 2OE 3A 6 13 EN T PR EN 23 5 8 17 19 10 11 15 3OE 14 EN 1Y1 1Y2 1Y3 2Q1 2Q2 2Q3 2Q4 3Y1 3Y2 3Y3
logic diagram (positive logic)
1OE 1A 24 22 2
1Y1
1OE
3
1Y2
23 2OE 2A PRE 6 7 20 5
1Y3
T R
2Q1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
8
2Q2
17
2Q3
19 15 13 10
2Q4
3OE 3A
3Y1
11
3Y2
14
3Y3
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI IOH IOL Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current 0 0 4.75 2 0.8 VCC - 32 32 70 MAX 5.25 UNIT V V V V mA mA C
TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL IIH IIL IOZ IO ICC Ci VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5 25 V 5.25 V, VI = VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V TEST CONDITIONS II = -18 mA IOH = - 32 mA IOL = 32 mA VI = 2.7 V VI = 0.5 V VO = VCC or GND VO = 2.5 V Outputs high IO = 0 0, Outputs low Outputs disabled - 30 11 15 10 3 9 MIN 2 0.5 50 - 50 50 -180 40 30 30 pF pF mA TYP MAX -1.2 UNIT V V V A A A mA
Co All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
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* DALLAS, TEXAS 75265
2-3
CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN fclock lk Clock frequency 1A/3A (duty cycle 40 - 60%) 2A (duty cycle 40 - 60%) 1A/3A low 1A/3A high tw Pulse duration 2A low 2A high PRE low tsu Setup time PRE inactive before 2A 5.9 5.9 2.8 4.5 3 2 ns ns MAX 67 100 UNIT MHz MHz
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figures 1 and 2)
PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) 1A or 3A 2A Any An A or A PRE Any An OE Any An OE 1A tsk(o) k( ) 3A 1A or 3A 2A tsk(pr) Any A or A Duty cycle 40 - 60% NOTE 4: All specifications are valid only for all outputs switching. TO (OUTPUT) Any 1Y or 3Y Any Q Any Y or Q Any Q Any Y or Q Any Y or Q Any 1Y Any 3Y Any 1Y or 3Y Any Q Any Y or Q MIN 67 100 11 10.5 12.5 9 8.5 8.5 9 0.4 0.4 0.5 0.4 1 ns ns MAX UNIT MHz ns ns ns ns
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CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
tw LOAD CIRCUIT Input 3V Timing Input 1.5 V 0V tsu Data Input 1.5 V VOLTAGE WAVEFORMS th 3V 1.5 V 0V Output Control (low-level enabling) tPZL 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V tPHZ VOH 1.5 V VOH - 0.3 V 0V VOLTAGE WAVEFORMS VOL + 0.3 V VOL 3V VOLTAGE WAVEFORMS 1.5 V 1.5 V 0V 3V
Input 1.5 V tPLH 1.5 V
3V 0V tPHL 2V 0.8 V tr 2V 0.8 V VOH VOL Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C)
Output
1.5 V tf
tPZH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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2-5
CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS329A - OCTOBER 1993 - REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
nA
nY1 tPLH1 nY2 tPLH2 nY3 tPLH3 tPHL3 tPLH10 tPHL10 tPHL2 tPLH9 tPHL9 tPHL1 tPLH8 tPHL8
2A
2Q1 tPLH4 2Q2 tPLH5 2Q3 tPLH6 2Q4 tPLH7 tPHL7 tPHL6 tPHL5 tPHL4
NOTES: A. Output skew, tsk(o), is calculated as the greater of: - The difference between the fastest and slowest of tPLHn (n = 1, 2, 3) - The difference between the fastest and slowest of tPLHn (n = 4, 5, 6, 7) - The difference between the fastest and slowest of tPLHn (n = 8, 9, 10) - The difference between the fastest and slowest of tPHLn (n = 1, 2, 3) - The difference between the fastest and slowest of tPHLn (n = 4, 5, 6, 7) - The difference between the fastest and slowest of tPHLn (n = 8, 9, 10) B. Process skew, tsk(pr), is calculated the same as output skew, tsk(o), across multiple CDC330 devices under identical operating conditions.
Figure 2. Waveforms for Calculation of tsk(o), tsk(pr)
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* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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