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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
D D D D D D D
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (- 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink
DW PACKAGE (TOP VIEW)
VCC 1G 2G A P0 P1 VCC 2Y4 2Y3 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Y1 1Y2 GND 1Y3 1Y4 GND 2Y1 2Y2 GND
description
The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC340 is characterized for operation from 0C to 70C.
FUNCTION TABLE INPUTS 1G X L L H H 2G X L H L H A L H H H H OUTPUTS 1Y1 - 1Y4 H H H L L 2Y1 - 2Y4 H H L H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
logic symbol
1G 2G 2 3 G1 G2 1 1 A 4 1 1 2 2 2 2 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 19 18 16 15 13 12 9 8 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
logic diagram (positive logic)
1G 2 19 1Y1
2G
3
18
1Y2
16
1Y3
15 4 13
1Y4
A
2Y1
12
2Y2
9
2Y3
8
2Y4
2
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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations Application Note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI IOH IOL fclock lk Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input clock frequency One output back loaded Both output banks loaded 0 0 4.75 2 0.8 VCC - 48 48 80 40 70 MAX 5.25 UNIT V V V V mA mA MHz C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IO ICC VCC = 4.75 V, VCC = 4.75 V, VCC = 5 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, , VI = VCC or GND TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 48 mA IOL = 48 mA VI = VCC or GND VO = 2.5 V IO = 0, , Outputs high Outputs low - 50 - 100 2 24 MIN 2.5 3 2 1 - 200 - 50 TA = 25C TYP MAX -1.2 2.5 3 2 0.5 1 - 200 3.5 33 V A mA mA pF V MIN MAX -1.2 UNIT V
Ci VI = 2.5 V or 0.5 V 3 All typical values are at VCC = 5 V. No more than one output should be tested at a time, and the duration of the test should not exceed one second.
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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
switching characteristics, CL = 50 pF (see Figure 1 and Figure 2)
PARAMETER tPLH tPHL tPLH tPHL tsk(o) tsk(p) tsk(pr) tr tf Propagation delay time, low-to-high level Propagation delay time, high-to-low level Propagation delay time, low-to-high level Propagation delay time, high-to-low level Skew time, output Skew time, pulse Skew time, process Rise time Fall time A A Y Y A Y FROM (INPUT) A G TO (OUTPUT) Y Y VCC = 5 V, TA = 25C MIN TYP MAX 3.4 3.2 2 2 0.3 0.6 4.5 4.3 3.8 3.8 0.5 0.8 1.1 VCC = 4.75 V to 5.25 V, TA = 0C to 70C MIN MAX 3 2.8 2 2 4.8 4.7 4 4 0.6 0.9 1.1 1.5 1.5 ns ns ns UNIT
ns ns
tpd performance information relative to VCC and temperature variation (see Note 4)
PARAMETER tPLH(TA) tPHL(TA) tPLH(VCC) tPHL(VCC) Temperature drift of tPLH from 0C to 70C Temperature drift of tPHL from 0C to 70C VCC drift of tPLH from 4.75 V to 5.25 V VCC drift of tPHL from 4.75 V to 5.25 V change - 53 ps / 10C - 58 ps / 10C 43 ps / 100 mV - 33 ps / 100 mV
Virtually independent of VCC Virtually independent of temperature NOTE 4: The data extracted is from a wide range of characterization material.
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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 500
LOAD CIRCUIT
Input (see Note B) tPLH
3V 1.5 V 1.5 V 0V tPHL 2V 1.5 V 0.8 V tf VOH VOL
Output
1.5 V 0.8 V tr
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
A
1G
2G
1Yn tPLH1 2Yn tPLH2 tPHL2 tPHL1
NOTES: A. Output skew, tsk(o), is calculated as the greater of: - The difference between the fastest and slowest of tPLHn (n = 1, 2) - The difference between the fastest and slowest of tPHLn (n = 1, 2) B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn - tPHLn | (n = 1, 2). C. Process skew, tsk(pr), is calculated as the greater of: - The difference between the fastest and slowest of tPLHn (n = 1, 2) across multiple devices under identical operating conditions - The difference between the fastest and slowest of tPHLn (n = 1, 2) across multiple devices under identical operating conditions
Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)
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CDC340 1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B - DECEMBER 1992 - REVISED MAY 1997
MECHANICAL INFORMATION
DW (R-PDSO-G**)
16 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) DIM 0.020 (0,51) 0.014 (0,35) 16 9 0.010 (0,25) M
PINS **
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78)
A MAX
A MIN
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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Copyright (c) 1998, Texas Instruments Incorporated

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