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| SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 D D D D D D EPIC TM ( Enhanced-Performance Implanted CMOS) Submicron Process Member of the Texas Instruments Widebus TM Family ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DGG OR DL PACKAGE (TOP VIEW) description The SN74ALVC16269 is a 12-bit to 24-bit registered bus transceiver, which is intended for applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors. The SN74ALVC16269 is designed specifically for low-voltage (3.3-V ) VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC. Data is stored in the internal B-port registers on 28 29 the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA) NC - No internal connection inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period that the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVC16269 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16269 is characterized for operation from - 40C to 85C. OEA OEB1 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 NC SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 OEB2 CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 Function Tables OUTPUT ENABLE INPUTS CLK OEA H H L L OEB H L H L OUTPUTS A Z Z Active Active 1B, 2B Z Active Z Active A-TO-B STORAGE (OEB = L) INPUTS CLKENA1 H L L X X CLKENA2 H X X L L CLK X A X L H L H OUTPUTS 1B 1B0 L H X 2B 2B0 X X L H X Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEA = L) INPUTS CLK X X SEL H L H H L 1B X X L H X 2B X X X X L OUTPUT A A0 A0 L H L L X H H Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 logic diagram (positive logic) CLK OEB1 29 2 C1 1D C1 OEB2 CLKENA1 CLKENA2 SEL 56 30 55 C1 28 1D 1 1D OEA 1D C1 G1 C1 A1 8 1D 1 1 CE C1 1D 6 CE C1 1D 1 of 12 Channels 23 1B1 2B1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) MIN VCC VIH VIL VI VO IOH Supply voltage High-level High level input voltage Low-level Low level input voltage Input voltage Output voltage High-level output current VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 2.3 1.7 2 0.7 0.8 VCC VCC - 12 - 12 - 24 12 12 24 10 85 ns / V C mA mA MAX 3.6 UNIT V V V V V IOL t /v Low-level output current Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = - 100 A IOH = - 6 mA, VOH IOH = - 12 mA IOH = - 24 mA, IOL = 100 A IOL = 6 mA, VOL IOL = 12 mA IOL = 24 mA, VI = VCC or GND VI = 0.7 V VI = 1.7 V II(hold) ( ) VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND IO = 0 TEST CONDITIONS VCC MIN to MAX VIH = 1.7 V VIH = 1.7 V VIH = 2 V VIH = 2 V VIH = 2 V VIL = 0.7 V VIL = 0.7 V VIL = 0.8 V VIL = 0.8 V 2.3 V 2.3 V 2.7 V 3V 3V MIN to MAX 2.3 V 2.3 V 2.7 V 3V 3.6 V 23V 2.3 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 V 3.3 V 3.5 9 45 -45 75 -75 500 10 40 750 A A A pF pF A TA = - 40C to 85C MIN TYP MAX VCC - 0.2 2 1.7 2.2 2.4 2 0.2 0.4 0.7 0.4 0.55 5 A V V UNIT II IOZ ICC nICC Ci Cio For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V. For I/O ports, the parameter IOZ includes the input-leakage current. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 2.5 V 0.2 V MIN fclock tw Clock frequency Pulse duration, CLK high or low A data before CLK B data before CLK tsu Setup St time SEL before CLK CLKENA1 or CLKENA2 before CLK OE before CLK A data after CLK B data after CLK th Hold time SEL after CLK CLKENA1 or CLKENA2 after CLK OE after CLK High or low High or low High or low High or low High or low High or low High or low High or low High or low High or low 3.3 2 2.2 1.6 1 1.5 0.7 0.7 1.1 1 0.8 MAX 135 3.3 2 2.1 1.6 1.2 1.6 0.6 0.6 0.7 0.8 0.8 VCC = 2.7 V MIN MAX 135 3.3 1.7 1.8 1.3 0.9 1.3 0.6 0.6 0.7 1.1 0.8 ns ns VCC = 3.3 V 0.3 V MIN MAX 135 MHz ns UNIT switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2) PARAMETER fmax tpd d ten tdis di CLK B A B CLK CLK A B A FROM (INPUT) TO (OUTPUT) VCC = 2.5 V 0.2 V MIN 135 1 1 1 1 1.4 1.5 8.8 7 8.4 8.1 8.3 7.7 MAX VCC = 2.7 V MIN 135 7.3 5.8 6.7 6.2 6.9 6.8 MAX VCC = 3.3 V 0.3 V MIN 135 1 1 1 1 1 1 6.2 5 6.1 5.9 6.1 5.6 MAX ns ns ns ns UNIT operating characteristics, TA = 25C PARAMETER Outputs enabled Outputs disabled TEST CONDITIONS VCC = 2.5 V 0.2 V TYP Cpd d Power dissipation capacitance CL = 50 pF pF, f = 10 MHz 55 46 VCC = 3.3 V 0.3 V TYP 59 49 pF UNIT 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 0.2 V VCC = 2.5 V 4.6 V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 4.6 V GND " LOAD CIRCUIT tw 2.3 V Timing Input tsu Data Input 1.2 V 2.3 V 1.2 V 0V th 2.3 V 1.2 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.2 V 1.2 V 0V VOLTAGE WAVEFORMS PULSE DURATION Output Control (low-level enabling) tPZL 2.3 V 1.2 V 1.2 V 0V tPLZ 2.3 V 1.2 V tPHZ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL 2.3 V Input tPLH 1.2 V 1.2 V 0V tPHL VOH Output 1.2 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.2 V VOL Output Waveform 1 S1 at 4.6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH 1.2 V VOH - 0.3 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 , tr ns, tf ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v10 v2.5 v2.5 Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN74ALVC16269 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS417B - OCTOBER 1993 - REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 0.3 V VCC = 2.7 V AND 3.3 V 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND " LOAD CIRCUIT 1.5 V tw 2.7 V Timing Input tsu Data Input 1.5 V 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Output Control (low-level enabling) tPZL 2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH 1.5 V VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL 2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 , tr ns, tf ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v10 v2.5 v2.5 Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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