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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
D D D D D D D D
D D
Generates Clocks for PentiumTM III Class Microprocessors Supports a Single Pentium III Microprocessor Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies Includes Spread Spectrum Clocking (SSC), 0.5% Downspread for Reduced EMI Performance Power Management Control Terminals Low Output Skew and Jitter for Clock Distribution Operates from Dual 2.5-V and 3.3-V Supplies Generates the Following Clocks: - 3 CPU (2.5 V, 100/133 MHz) - 10 PCI (3.3 V, 33.3 MHz) - 1 CPU/2 (2.5 V, 50/66 MHz) - 1 APIC (2.5 V, 16.67 MHz) - 3 3V66 (3.3 V, 66 MHz) - 2 REF (3.3 V, 14.318 MHz) - 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package Designed for Use with TI's Direct RambusTM Clock Generators (CDCR81, CDCR82, CDCR83)
DL PACKAGE (TOP VIEW)
REF0 REF1 VDD3.3V XIN XOUT GND PCI0 PCI1 VDD3.3V PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDD3.3V PCI8 PCI9 GND 3V66(0) 3V66(1) 3V66(2) VDD3.3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND VDD2.5V APIC GND VDD2.5V CPU_DIV2 GND VDD2.5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND SEL133/100
description
The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III class microprocessor. All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
description (continued)
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33 MHz. Since the CDC921 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts. Function Tables
SELECT FUNCTIONS INPUTS SEL133/ 100 L L L L H H H H SEL1 L L H H L L H H SEL0 L H L H L H L H CPU Hi-Z N/A 100 MHz 100 MHz TCLK/2 N/A 133 MHz 133 MHz CPU_DIV2 Hi-Z N/A 50 MHz 50 MHz TCLK/4 N/A 66 MHz 66 MHz 3V66 Hi-Z N/A 66 MHz 66 MHz TCLK/4 N/A 66 MHz 66 MHz OUTPUTS PCI Hi-Z N/A 33 MHz 33 MHz TCLK/8 N/A 33 MHz 33 MHz 48MHz Hi-Z N/A Hi-Z 48 MHz TCLK/2 N/A Hi-Z 48 MHz REF Hi-Z N/A 14.318 MHz 14.318 MHz TCLK N/A 14.318 MHz 14.318 MHz APIC Hi-Z N/A 16.67 MHz 16.67 MHz TCLK/16 N/A 16.67 MHz 16.67 MHz FUNCTION 3-state Reserved 48-MHz PLL off 48-MHz PLL on Test Reserved 48-MHz PLL off 48-MHz PLL on
ENABLE FUNCTIONS INPUTS PWR_DWN L H CPU L On CPU_DIV2 L On OUTPUTS APIC L On 3V66 L On PCI L On REF, 48MHz L On INTERNAL CRYSTAL Off On VCOs Off On
OUTPUT BUFFER SPECIFICATIONS BUFFER NAME CPU, CPU_DIV2, APIC 48MHz, REF PCI, 3V66 VDD RANGE (V) 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465 IMPEDANCE () 13.5 - 45 20 - 60 12 - 55 BUFFER TYPE TYPE 1 TYPE 3 TYPE 5
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
Terminal Functions
TERMINAL NAME 3V66 [0-2] 48MHz APIC CPU [0-2] CPU_DIV2 GND NO. 21-23 27 46 36, 37, 40 43 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 7, 8, 10-13, 15, 16, 18, 19 32 1, 2 29, 30 25 31 38, 41, 44, 47 3, 9, 17, 24, 28, 34 4 5 I O O I O I I I I/O O O O O O 3.3 V, Type 5, 66-MHz clock outputs 3.3 V, Type 3, 48-MHz clock output 2.5 V, Type 2, APIC clock output at 16.67 MHz 2.5 V, Type 1, CPU clock outputs 2.5 V, Type 1, CPU_DIV2 clock output Ground for PCI, 3V66, 48MHz, CPU, CPU_DIV2, APIC, REF [0-1] outputs and CORE DESCRIPTION
PCI [0-9] PWR_DWN REF0, REF1 SEL0, SEL1 SEL133/100 SPREAD VDD2.5V VDD3.3V XIN XOUT
3.3 V, Type 5, 33-MHz PCI clock outputs Power down for complete device with outputs forced low 3.3 V, Type 3, 14.318-MHz reference clock outputs LVTTL level logic select terminals for function selection LVTTL level logic select terminal for enabling 100/133 MHz Disables SSC function Power for CPU, CPU_DIV2, and APIC outputs Power for the REF, PCI, 3V66, 48MHz outputs and CORE Crystal input - 14.318 MHz Crystal output - 14.318 MHz
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
spread spectrum clock (SSC) implementation for CDC921
Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency, which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation of the CPU-PLL allows to distribute the energy to many different frequencies which reduces the power peak. A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in Figure 1.
Highest Peak
Non-SSC
SSC
of fnom
fnom
Figure 1. Frequency Power Spectrum With and Without the Use of SSC The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a "down-spread modulation". The peak reduction depends on the modulation scheme and modulation profile. System performance and timing requirements are the limiting factors for actual design implementations. The implementation was driven to keep the average clock frequency closed to its upper specification limit. The modulation amount was set to approximately -0.5%. In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for CDC921 is shown in Figure 2.
Period of Output Frequency - ns
10.03 10.02 10.01 10 9.99 9.98 9.97 5 10 15 20 25 30 35 Period of Modulation Signal - s 40 45
Figure 2. SSC Modulation Profile
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
functional block diagram
SEL133/100 SEL0 SEL1 25 29 30 Control Logic 3-State 48-MHz Inactive Test SEL 133/100 2*REF 14.318 MHz (1,2) XIN XOUT 4 5 Xtal Oscillator 48 MHz PLL 1*48MHz 48 MHz (27) 3*CPU 100/133 MHz (36,37,40) Spread Logic CPU PLL 1*CPU_DIV2 50/66 MHz (43)
SPREAD
Sync Logic & Power Down Logic
31
/2
/2
/3 /4 /2
10*PCI 33 MHz (7,8,10,11,12, 13,15,16,18,19) 1*APIC 16.67 MHz (46) 3*AGP (3V66) 66 MHz (21,22,23)
/3 /4
PWR_DWN
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Voltage range applied to any output in the high-impedance state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VDD + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x IOL Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATNG DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING
DL 1315.7 mW 10.53 mW/C 842.1 mW 684.2 mW This is the inverse of the traditional junction-to-case thermal resistance (RJA) and uses a board-mounted device at 95C/W.
recommended operating conditions (see Note 2)
MIN Supply voltage VDD voltage, High-level input voltage, VIH Low-level input voltage, VIL Input voltage, VI CPUx, CPU_DIV2 High-level High level output current IOH current, APIC 48MHz, REFx PCIx, PCI_F, 3V66x CPUx, CPU_DIV2 Low-level Low level output current, IOL current APIC 48MHz, REFx PCIx, PCI_F, 3V66x Reference frequency, f(XTAL) Crystal frequency, f(XTAL) Operating free-air temperature, TA Test mode Normal mode 13.8 0 130 14.318 14.8 85 3.3 V 2.5 V 3.135 2.375 2 GND - 0.3 V 0 NOM MAX 3.465 2.625 VDD + 0.3 V 0.8 VDD -12 -12 -14 -18 12 12 9 12 MHz MHz C mA UNIT V V V V
mA
NOTE 2: Unused inputs must be held high or low to prevent them from floating. All nominal values are measured at their respective nominal VDD values. Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven externally up to f(XTAL) = 130 MHz. If XIN is driven externally, XOUT is floating. This is a series fundamental crystal with fO = 14.31818 MHz.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK RI Input clamp voltage Input resistance XIN, XOUT XOUT IIH High-level input current g SEL0, SEL1, SPREAD PWR_DWN SEL133/100 XOUT IIL Low-level input current SEL0, SEL1, SPREAD PWR_DWN SEL133/100 IOZ High-impedance-state output current TEST CONDITIONS VDD = 3.135 V, VDD = 3.465 V, VDD = 3.135 V, VDD = 3.465 V, VDD = 3.465 V, VDD = 3.465 V, VDD = 3.135 V, VDD = 3.465 V, VDD = 3.465 V, VDD = 3.465 V, |VDD| = max, VDD = 2.625 V, PWR_DWN = low IDD Supply current VDD = 2.625 V, VDD = 3.465 V, PWR_DWN = low VDD = 3.465 V, VDD = 2.625 V VDD = 3.465 V CL = 20 pF, CPU = 133 MHz VDD = 3.3 V, VDD = 3.3 V, VDD = 3.465 V VDD = 2.625 V VI = VDD or GND VI = 0.3 V 3.3 18 18.5 114 44 II = -18 mA VI = VDD -0.5 V VI = VDD -0.5 V VI = VDD VI = VDD VI = VDD VI = 0 V VI = GND VI = GND VI = GND VO = VDD or GND All outputs = low, All outputs = high All outputs = low, All outputs = high MIN 80 20 <10 <10 <10 -2 <10 <10 <10 TYP MAX -1.2 350 50 10 10 10 -5 -10 -10 -10 10 <20 <20 <50 12 100 100 200 37 1.4 30 156 60 5.8 22.5 UNIT V k mA A A A mA A A A A A A A mA mA mA pF pF
IDD(Z)
High-impedance-state supply g y current Dynamic IDD
CI
Input capacitance Crystal terminal capacitance
All typical values are measured at their respective nominal VDD values.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
CPUx, CPU_DIV2, APIC (Type 1)
PARAMETER VOH g g High-level output voltage TEST CONDITIONS VDD = min to max, VDD = 2.375 V, VDD = min to max, VDD = 2.375 V, VDD = 2.375 V, VDD = 2.5 V, VDD = 2.625 V, VDD = 2.375 V, VDD = 2.5 V, VDD = 2.625 V, High state Low state VDD = 3.3 V, VO = 0.5 VDD, IOH = - 1 mA IOH = -12 mA IOL = 1 mA IOL = 12 mA VO = 1 V VO = 1.25 V VO = 2.375 V VO = 1.2 V VO = 1.25 V VO = 0.3 V VO = VDD or GND VO/IOH VO/IOL 27 MIN VDD - 0.1 V 2 0.1 0.18 -26 -42 -46 -16 57 63 23 5.8 13.5 13.5 27 20 43 8.5 45 45 pF mA -27 mA 0.4 V TYP MAX UNIT V
VOL
Low level output voltage Low-level
IOH
High-level output current
IOL CO ZO
Low-level output current Output capacitance Output impedance
VO = 0.5 VDD, All typical values are measured at their respective nominal VDD values.
48MHz, REFx (Type 3)
PARAMETER VOH High-level output voltage g g TEST CONDITIONS VDD = min to max, VDD = 3.135 V, VDD = min to max, VDD = 3.135 V, VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, High state Low state VDD = 3.3 V, VO = 0.5 VDD, IOH = - 1 mA IOH = -14 mA IOL = 1 mA IOL = 9 mA VO = 1 V VO = 1.65 V VO = 3.135 V VO = 1.95 V VO = 1.65 V VO = 0.4 V VO = VDD or GND VO/IOH VO/IOL 29 MIN VDD - 0.1 V 2.4 0.1 0.18 -27 -41 -41 -12 50 53 20 4.5 20 20 40 31 37 7 60 60 pF mA -23 mA 0.4 V TYP MAX UNIT V
VOL
Low-level Low level output voltage
IOH
High-level output current
IOL CO ZO
Low-level output current Output capacitance Output impedance
VO = 0.5 VDD, All typical values are measured at their respective nominal VDD values.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
PCIx, 3V66x (Type 5)
PARAMETER VOH g g High-level output voltage TEST CONDITIONS VDD = min to max, VDD = 3.135 V, VDD = min to max, VDD = 3.135 V, VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, High state Low state VDD = 3.3 V, VO = 0.5 VDD, IOH = - 1 mA IOH = -18 mA IOL = 1 mA IOL = 12 mA VO = 1 V VO = 1.65 V VO = 3.135 V VO = 1.95 V VO = 1.65 V VO = 0.4 V VO = VDD or GND VO/IOH VO/IOL 30 MIN VDD - 0.1 V 2.4 0.1 0.15 -33 -53 -53 -16 67 70 27 4.5 12 12 31 24 49 7.5 55 55 pF mA -33 mA 0.4 V TYP MAX UNIT V
VOL
Low level output voltage Low-level
IOH
High-level output current
IOL CO ZO
Low-level output current Output capacitance Output impedance
VO = 0.5 VDD, All typical values are measured at their respective nominal VDD values.
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0C to 85C
PARAMETER Overshoot/undershoot Ring back Stabilization time, PWR_DWN to PCIx tdis3 tdis4 Disable time, PWR_DWN to PCIx Stabilization time, PWR_DWN to CPUx Disable time, PWR_DWN to CPUx Stabilization time f(CPU) = 133 MHz f(CPU) = 133 MHz f(CPU) = 133 MHz f(CPU) = 133 MHz After SEL1, SEL0 After power up TEST CONDITIONS MIN GND - 0.7 V VIL - 0.1 V 0.05 50 0.03 50 3 3 3 TYP MAX VDD + 0.7 V VIH + 0.1 V 3 UNIT V V ms ns ms ns ms
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
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switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0C to 85C (continued)
CPUx
PARAMETER ten1 tdis1 tc Output enable time Output disable time CPU clock period Cycle to cycle jitter Duty cycle tsk(o) tsk(p) t(off) t(off) tw1 1 tw2 2 CPU bus skew CPU pulse skew CPU clock to APIC clock offset, rising edge CPU clock to 3V66 clock offset, rising edge Pulse duration width, high width Pulse duration width low width, f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 MHz f(CPU) = 133 MHz CPUx CPUn CPUx CPUn FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) CPUx CPUx TEST CONDITIONS f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz 1.5 0 2.6 1.4 2.8 1.7 0.4 0.4 10 7.5 45 50 2.8 0.75 4.3 3.7 4.3 4 1.5 1.4 2.2 2 MIN TYP 6 8 10.04 7.53 MAX 10 10 10.2 7.7 250 55 175 2.2 4 1.5 UNIT ns ns ns ns ps % ps ns ns ns ns ns ns ns
tr Rise time VO = 0.4 V to 2.0 V tf Fall time VO = 0.4 V to 2.0 V The average over any 1-s period of time is greater than the minimum specified period.
CPU_DIV2
PARAMETER ten1 tdis1 tc Output enable time Output disable time CPU_DIV2 CPU DIV2 clock period Cycle to cycle jitter Duty cycle tsk(p) tw1 1 tw2 2 CPU_DIV2 pulse skew Pulse duration width, high width Pulse duration width low width, FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) CPU_DIV2 CPU_DIV2 TEST CONDITIONS f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 MHz f(CPU) = 133 MHz VO = 0.4 V to 2.0 V 20 15 45 7.1 4.7 7.3 5 0.4 0.4 8.9 6.6 1.4 1.3 2 1.8 MIN TYP 6 8 20.08 15.06 MAX 10 10 20.4 15.3 250 55 1.6 UNIT ns ns ns ns ps % ns ns ns ns ns
tr Rise time tf Fall time VO = 0.4 V to 2.0 V The average over any 1-s period of time is greater than the minimum specified period.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
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switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0C to 85C (continued)
APIC
PARAMETER ten1 tdis1 tc Output enable time Output disable time APIC clock period Cycle to cycle jitter Duty cycle tsk(p) t(off) tw1 tw2 APIC pulse skew APIC clock to CPU clock offset, rising edge Pulse duration width, high Pulse duration width, low APIC CPUx f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) APIC APIC TEST CONDITIONS f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz f(CPU) = 100 or 133 MHz f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz 60 45 MIN TYP 6 8 60.24 MAX 10 10 60.6 400 55 3 -1.5 25.5 25.3 0.4 0.4 28 29.2 1.6 1.2 2.1 1.7 -4 UNIT ns ns ns ps % ns ns ns ns ns ns
tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V The average over any 1-s period of time is greater than the minimum specified period.
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0C to 85C
3V66
PARAMETER ten1 tdis1 tc Output enable time Output disable time 3V66 clock period Cycle to cycle jitter Duty cycle tsk(o) tsk(p) t(off) t(off) tw1 tw2 3V66 bus skew 3V66 pulse skew 3V66 clock to CPU clock offset Pulse duration width, high Pulse duration width, low 3V66x 3V66n 3V66x 3V66x 3V66n CPUx f(3V66) = 66 MHz f(3V66) = 66 MHz FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) 3V66x 3V66x TEST CONDITIONS f(3V66) = 66 MHz f(3V66) = 66 MHz f(3V66) = 66 MHz f(CPU) = 100 or 133 MHz f(3V66) = 66 MHz f(3V66) = 66 MHz f(3V66) = 66 MHz 0 1.2 5.2 5 0.5 0.5 1.5 1.5 2 2 -0.75 2.1 15 45 50 MIN TYP 6 8 15.06 MAX 10 10 15.3 400 55 150 2.6 -1.5 3 UNIT ns ns ns ps % ps ns ns ns ns ns ns ns
3V66 clock to PCI clock offset, rising edge
tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V The average over any 1-s period of time is greater than the minimum specified period.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0C to 85C (continued)
48MHz
PARAMETER ten1 tdis1 tc Output enable time Output disable time 48MHz clock period Cycle to cycle jitter Duty cycle tsk(p) tw1 tw2 tr 48MHz pulse skew Pulse duration width, high Pulse duration width, low 48MHz 48MHz FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) 48MHz 48MHz TEST CONDITIONS f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(CPU) = 100 or 133 MHz f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(48MHz) = 48 MHz 20.5 45 7.8 7.8 1 1 2.1 1.9 2.8 2.8 MIN TYP 6 8 20.83 MAX 10 10 21.1 500 55 3 UNIT ns ns ns ps % ns ns ns ns ns
Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V The average over any 1-s period of time is greater than the minimum specified period.
REF
PARAMETER ten1 tdis1 tc Output enable time Output disable time REF clock period Cycle to cycle jitter Duty cycle tsk(o) tsk(p) tw1 tw2 REF bus skew REF pulse skew Pulse duration width, high REFx REFn REFx REFn FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) REFx REFx TEST CONDITIONS f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(CPU) = 100 or 133 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz 45 150 26.2 26.2 1 1 32.7 31.2 2 1.9 2.8 2.8 MIN TYP 6 8 69.84 700 55 250 2 MAX 10 10 UNIT ns ns ns ps % ps ns ns ns ns ns
Pulse duration width, low f(REF) = 14.318 MHz tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V The average over any 1-s period of time is greater than the minimum specified period.
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CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0C to 85C (continued)
PCI
PARAMETER ten1 tdis1 tc Output enable time Output disable time PCIx clock period Cycle to cycle jitter Duty cycle tsk(o) tsk(p) t(off) tw1 tw2 tr PCIx bus skew PCIx pulse skew PCIx clock to 3V66 clock offset Pulse duration width, high Pulse duration width, low Rise time f(PCI) = 33 MHz f(PCI) = 33 MHz VO = 0.4 V to 2 V VO = 0.4 V to 2 V PCIx PCIn PCIx PCIn FROM (INPUT) SEL133/100 SEL133/100 TO (OUTPUT) PCIx PCIx TEST CONDITIONS f(PCI) = 33 MHz f(PCI) = 33 MHz f(PCI) = 33 MHz f(CPU) = 100 or 133 MHz f(PCI) = 33 MHz f(PCI) = 33 MHz f(PCI) = 33 MHz -1.2 12 12 0.5 0.5 1.6 1.5 2 2 30 45 70 MIN TYP 6 8 30.12 MAX 10 10 30.5 300 55 300 4 -3 UNIT ns ns ns ps % ps ns ns ns ns ns ns
tf Fall time The average over any 1-s period of time is greater than the minimum specified period.
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13
CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL (see Note A) RL = 500 RL = 500 S1 VO_REF OPEN GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VO_REF GND
LOAD CIRCUIT for tpd and tsk
From Output Under Test
Test Point CL (see Note A)
3V Input 0V
LOAD CIRCUIT FOR tr and tf
VOLTAGE WAVEFORMS
3V Input VT_REF tPLH VT_REF 0V tPHL VOH
Output Enable (high-level enabling) tPZL
VT_REF
VIH_REF Output VT_REF VIL_REF tr tw_high tw_low
VOL tf
Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. CL = 20 pF (CPUx, APIC, 48MHz, REF), CL = 30 pF (PCIx) B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 14.318 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
PARAMETER VIH_REF VIL_REF VT_REF VO_REF High-level reference voltage Low-level reference voltage Input Threshold reference voltage Off-state reference voltage
3.3-V INTERFACE 2.4 0.4 1.5 6
2.5-V INTERFACE 2 0.4 1.25 4.6
Figure 3. Load Circuit and Voltage Waveforms
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II
VT_REF VT_REF VT_REF
tw
VIH_REF VT_REF VIL_REF
VDD
0V tPLZ 3 V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0 V VOL
v
UNIT V V V V
CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
PARAMETER MEASUREMENT INFORMATION
CPUx or PCIx Clock tc CPUx or PCIx Clock tsk(o) t(low) t(high) VT_REF VT_REF
t
sk(p)
+
t
PLH PHL
-t
Duty Cycle
+
t
(low) tc
100
3V66 or CPUx VT_REF
3V66, PCIx, or APIC
VT_REF
t(off) [3V66 to PCIx] t(off) [CPUx to APIC] t(off) [CPUx to 3V66]
Figure 4. Waveforms for Calculation of Skew, Offset, and Jitter
CPU (internal) PCI (internal)
PWR_DWN CPU (external) PCI (external) VCO
CRYSTAL
NOTE A: Shaded sections on the VCO and Crystal waveforms indicate that the VCO and crystal oscillators are active and there is a valid clock.
Figure 5. Power-Down Timing
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C CCCCCCCCCCCC CCCCCCCCCC CCCCCCCCCCC
CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC
15
CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
SCAS623 -MAY 27, 1999
MECHANICAL DATA
DL (R-PDSO-G**)
48-PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,635)
0.012 (0,305) 0.008 (0,203) 25
0.005 (0,13) M
48
0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03)
Gage Plane 0.010 (0,25)
1 A
24
0- 8 0.040 (1,02) 0.020 (0,51)
Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10)
PINS ** DIM A MAX
28 0.380 (9,65) 0.370 (9,40)
48 0.630 (16,00) 0.620 (15,75)
56 0.730 (18,54) 0.720 (18,29) 4040048 / D 08/97
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118
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Copyright (c) 1999, Texas Instruments Incorporated

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