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CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
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description
The CDCV857 is a high-performance, low-skew, 20 29 low-jitter zero delay buffer that distributes a 21 28 differential clock input pair (CLK, CLK) to ten 22 27 differential pairs of clock outputs (Y[0:9], Y[0:9]) 23 26 and one differential pair feedback clock output 24 25 (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). All outputs can be enabled or disabled via a single output enable input. When PWRDWN is high, the outputs switch in phase and frequency with CLK; when PWRDWN is low, the outputs are disabled to high impedance state (3-state). When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The output pairs are put into a 3-state condition, the PLL is shut down, and the device will enter a low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typ 10 MHz). An input frequency detection circuit detects the low frequency condition and puts the output clock pairs into a high-impedance state. The CDCV857 is also able to track spread spectrum clocking for reduced EMI. Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857 is characterized for operation from 0C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 to 170 MHz Low Jitter (cyc-cyc): 75 ps Distributes One Differential Clock Input to Ten Differential Outputs Three-State Outputs When the Input Differential Clocks Are <20 MHz Operates From Dual 2.5-V and 3.3-V Supplies 48-Pin TSSOP Package Consumes < TBD-A Quiescent Current External Feedback PIN (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks
DGG PACKAGE (TOP VIEW)
GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND Y5 Y5 VDDQ Y6 Y6 GND GND Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 VDDQ Y9 Y9 GND
CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
FUNCTION TABLE (Select Functions) INPUTS AVDD GND GND X X 2.5 V (nom) 2.5 V (nom) 2.5 V (nom) PWRDWN H H L L H H X CLK L H L H L H <20 MHz CLK H L H L H L <20 MHz Y[0:9] L H Z Z L H Z H L Z Z H L Z OUTPUTS Y[0:9] FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z Bypassed/Off Bypassed/Off Off Off On On Off PLL
functional block diagram
3 2 37 16 Powerdown and Test Logic 5 6 10 9 20 19 22 23 46 47 CK CK FBIN FBIN 13 14 36 35 PLL 39 40 29 30 27 26 32 33 44 43 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT
PRODUCT PREVIEW
PWRDWN AVDD
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CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
Terminal Functions
TERMINAL NAME AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND NO. 17 16 13, 14 35, 36 32, 33 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 37 4, 11, 12, 15, 21, 28, 34, 38, 45 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 O I I I O I/O Ground for 2.5-V analog supply 2.5-V Analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground DESCRIPTION
PWRDWN VDDQ
Output enable for Y and Y 2.5-V Supply
Y[0:9]
Buffered output copies of input clock, CLK
Y[0:9]
O
Buffered output copies of input clock, CLK
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89C/W Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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PRODUCT PREVIEW
CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
recommended operating conditions (see Note 4)
MIN Supply voltage, VDDQ, AVDD Low level input voltage VIL voltage, High level input voltage VIH voltage, DC input signal voltage (see Note 5) Differential input signal voltage VID (see Note 6) voltage, Output differential cross-voltage, VOX (see Note 7) Input differential pair cross-voltage, VIX (see Note 7) High-level output current, IOH Low-level output current, IOL Input slew rate, SR Operating free-air temperature, TA 1 0 DC AC CLK, FBIN CLK, FBIN CLK, CLK, FBIN, FBIN PWRDWN CLK, CLK, FBIN, FBIN PWRDWN -0.3 VDDQ/2 + 0.18 1.7 -0.3 0.36 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 VDDQ/2 2.3 TYP MAX 2.7 VDDQ/2 - 0.18 0.7 VDDQ + 0.3 VDDQ VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 -12 12 4 85 UNIT V V V V V V V mA mA V/ns C
PRODUCT PREVIEW
NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. DC input signal voltage specifies the allowable dc execution of differential input. 6. Differentialinputsignalvoltagespecifiesthedifferentialvoltage|VTR-VCP|requiredforswitching,whereVTRisthetrueinputlevelandVCPisthe complementary input level (see Figure 3). 7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL IOH IOL VO II IOZ IDDPD IDD I(AVDD) CI Input voltage High-level High level output voltage Low-level Low level output voltage High-level output current Low-level output current Output voltage swing Input current Power down current on VDDQ + AVDD Dynamic current on VDDQ Supply current on AVDD Input capacitance CLK, FBIN High-impedance-state output current All inputs TEST CONDITIONS VDDQ = 2.3 V, II = -18 mA VDDQ = min to max, IOH = -1 mA VDDQ = 2.3 V, IOH = -12 mA VDDQ = min to max, IOL = 1 mA VDDQ = 2.3 V, VDDQ = 2.3 V, IOL = 12 mA VO = 1 V MIN VDDQ- 0.1 1.7 0.1 0.6 -18 26 1.1 -32 35 VDDQ- 0.4 10 10 TBD TYP MAX -1.2 UNIT V V V mA mA V A A A
VDDQ = 2.3 V, VO = 1.2 V For load condition see Figure 3 VDDQ = 2.7 V, VDDQ = 2.7 V, VI = 0 V to 2.7 V VO= VDDQ or GND
CLK at 0 MHz; of IDD and AIDD VCC = 2.7 V, fO = 167 MHz All outputs switching 14 pF in 60 environment, See Figure 3 AVCC = 2.7 V, VCC = 2.5 V fO = 167 MHz VI = VCC or GND 9 2
TBD 12
mA mA pF
CO Output capacitance VCC = 2.5 V VO = VCC or GND 3 pF All typical values are at respective nominal VDDQ. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120- resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage (see Figure 3).
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CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
timing requirements over recommended ranges of supply voltage and operating free-air temperature
MIN Clock frequency Input clock duty cycle Stabilization time (PLL mode) Stabilization time (Bypass mode) 60 40% MAX 170 60% 0.1 30 ms ms UNIT MHz
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.
switching characteristics
PARAMETER tPLH tPHL ten tdis tjit(per) jit( ) t(jit_cc) (jit ) t(jit_hper) t(sir_i) t(sl_o) t(phase) t(skew_o) t(skew_p) Low to high level propagation delay time, see Figure 2 High-to low level propagation delay time, see Figure 2 Output enable time Output disable time Jitter (period) see Figure 6 (period), Jitter (cycle-to-cycle), see Figure 3 (cycle to cycle) Half-period jitter, see Figure 7 Input clock slew rate, see Figure 8 Output clock slew rate, see Figures 1 and 8 Phase error, see Figure 4 Output skew, see Figure 5 Pulse skew Duty cycle# 66 MHz to 100 MHz 101 MHz to 167 MHz 49.5% 49% TEST CONDITIONS Test mode/CLK to any output Test mode/CLK to any output PWRDWN to Y output PWRDWN to Y output 66 MHz 100/133/167 MHz 66 MHz 100/133/167 MHz 100/133/167 MHz -75 -100 1 1 -100 75 100 4 2 100 100 100 50.5% 51% -75 75 MIN TYP 3.5 3.5 3 3 MAX UNIT ns ns ns ps ps ps ps V/ns V/ns ps ps ps ns
tr, tf Output rise and fall times (20% - 80%) Load: 120 /4 pF ps All typical values are at respective nominal VDDQ. Refers to transition of noninverting output. All differential output pins are terminated with 120 / 14 pF # While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where the cycle time (tC) decreases as the frequency goes up.
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PRODUCT PREVIEW
CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
VDD V(CK)
R = 60
R = 60
VDD/2
V(CK) CDCV857 GND
PRODUCT PREVIEW
Figure 1. IBIS Model Output Load
VDD/2 CDCV857 Z = 60 C = 14 pF -VDD/2 Z = 50 SCOPE
R = 10
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT)= GND
R = 50 V(TT)
Figure 2. Output Load Test Circuit
Yx, FBOUT Yx, FBOUT tc(n) tc(n+1) t(jit_cc) = tc(n) - tc(n+1)
Figure 3. Cycle-to-Cycle Jitter
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CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
CK CK
FBIN FBIN
t( ) n
t ( ) n+1
t( ) =
1
n=N
t( ) n
N
(N is a large number of samples)
Figure 4. Static Phase Offset
Yx Yx
Yx, FBOUT Yx, FBOUT
t(sk_o)
Figure 5. Output Skew
Yx, FBOUT Yx, FBOUT
tcycle n
Yx, FBOUT Yx, FBOUT
1 fO
1 t(jit_per) = tc(n) - f O Figure 6. Period Jitter
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PRODUCT PREVIEW
CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645 - AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT Yx, FBOUT
t(hper_n) 1 fO t(jit_hper) = t(hper_n)
t(hper_N+1)
1 2xfO
Figure 7. Half-Period Jitter
80% 80% VID, VOD
PRODUCT PREVIEW
Clock Inputs and Outputs
20% t(slrr_i) t(slrf_i), t(slrf_o)
20%
Figure 8. Input and Output Slew Rates
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Copyright (c) 2000, Texas Instruments Incorporated

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