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| SN74BCT29846 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS023C - MARCH 1989 - REVISED APRIL 1994 * * * * * * * * BiCMOS Process With CMOS Inputs and TTL Outputs Substantially Reduces Standby Current Input Has 50- Pullup Resister Bus-Structured Pinout Functionally Equivalent to SN74ALS29846 and AMD Am29846 Provides Extra Data Width Necessary For Wider Address / Data Paths or Buses With Parity Power-Up High-Impedance State Buffered Control Inputs to Reduce DC Loading Effects Packaged in Standard Plastic 300-mil DIP (NT) NT PACKAGE (TOP VIEW) OE1 OE2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC OE3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE description The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs will follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output enables do not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74BCT29846 is characterized for operation from 0C to 70C. FUNCTION TABLE INPUTS PRE L H H H H X X X CLR X L H H H X X X OE1 L L L L L X X H OE2 L L L L L X H X OE3 L L L L L H X X LE X X H H L X X X D X X L H X X X X OUTPUT Q H L H L Q0 Z Z Z PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1994, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74BCT29846 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS023C - MARCH 1989 - REVISED APRIL 1994 logic symbol 1 OE1 OE2 OE3 PRE CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 2 23 14 11 13 3 4 5 6 7 8 9 10 S2 R C1 1D 2 22 21 20 19 18 17 16 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q & EN logic diagram (positive logic) OE1 OE2 OE3 PRE LE 1 2 23 14 13 S2 C1 1D R S2 C1 1D R S2 C1 1D R S2 C1 1D R S2 C1 1D R S2 C1 1D R S2 C1 1D R S2 C1 1D R 1D 3 2 22 1Q 2D 4 2 21 2Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 3D 5 2 20 3Q 4D 6 2 19 4Q 5D 7 2 18 5Q 6D 8 2 17 6Q 7D 9 2 16 7Q 8D 10 2 15 8Q CLR 11 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74BCT29846 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS023C - MARCH 1989 - REVISED APRIL 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 0 4.5 2 0.8 - 24 48 70 MAX 5.5 UNIT V V V mA mA C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IOS ICC VCC = 4.5 V, VCC = 4 5 V 4.5 VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V TEST CONDITIONS II = - 18 mA IOH = - 15 mA IOH = - 24 mA IOL = 48 mA VO = 2.7 V VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 0 Outputs high Outputs low Outputs disabled All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. -10 - 75 3 24 3 MIN 2.4 2 0.35 0.5 20 - 20 0.1 -75 - 0.2 - 275 7 35 7 mA TYP 3.2 MAX - 1.2 UNIT V V V mA mA mA A mA mA POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74BCT29846 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS023C - MARCH 1989 - REVISED APRIL 1994 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN PRE low tw Pulse duration CLR low LE high tsu th Setup time before LE Hold time, data after LE Data PRE or CLR, inactive state 7 5 4 1.5 2 3.5 ns ns ns MAX UNIT switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 1) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) Any Q Any Q Any Q VCC = 5 V, TA = 25C MIN 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2 2 2 2 TYP 5.7 4.5 6 6 6 6 6 6 10 10 6 6 MAX 8 7 8 8 11 11 11 11 13 13 8 8 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2 2 2 2 9 8 10 10 12 12 12 12 15 15 10 10 ns ns ns MIN MAX UNIT D LE PRE CLR OE OE Any Q Any Q Any Q ns ns ns NOTE 1: Load circuits and voltage waveforms are shown in Section 1. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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