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| SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 D D D D D D State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Drive Outputs (-32-mA IOH, 64-mA IOL) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package SN54ABT533 . . . J OR W PACKAGE SN74ABT533A . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE SN54ABT533 . . . FK PACKAGE (TOP VIEW) 1D 1Q OE VCC description These octal transparent D-type latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse of the levels at the D inputs. 2D 2Q 3Q 3D 4D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 8Q 8D 7D 7Q 6Q 6D A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT533 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT533A is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1997, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 4Q GND LE 5Q 5D 1 SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q L H Q0 Z logic symbol 1 OE LE 11 logic diagram (positive logic) OE EN C1 2 5 6 9 12 15 16 19 7Q 8Q 3Q 4Q 5Q 6Q To Seven Other Channels LE 11 C1 1Q 2Q 1D 3 1D 2 1Q 1 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 1D 1 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT533A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT533 MIN VCC VIH VIL VI IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate -55 0 4.5 2 0.8 VCC -24 48 10 125 -40 0 MAX 5.5 SN74ABT533A MIN 4.5 2 0.8 VCC -32 64 10 85 MAX 5.5 UNIT V V V V mA mA ns/V C TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZH IOZL Ioff ICEX IO ICC VCC = 4 5 V 4.5 TEST CONDITIONS II = -18 mA IOH = -3 mA IOH = -3 mA IOH = -24 mA IOH = -32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VI = VCC or GND VO = 2.7 V VO = 0.5 V VI or VO 4.5 V VO = 5.5 V VO = 2.5 V Outputs high -50 Outputs high VCC = 5.5 V, IO = 0, 55V 0 VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Outputs low Outputs disabled Outputs high Outputs low Outputs disabled 3.5 6.5 -140 1 24 0.5 1 10 -10 150 50 -180 250 30 250 1.5 1.5 1.5 -50 50 -180 250 30 250 1.5 1.5 1.5 -50 1 10 -10 1 10 -10 150 50 -180 250 30 250 1.5 1.5 1.5 pF pF mA MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25C TYP MAX -1.2 2.5 3 2 2 V mV A A A A A mA A mA A SN54ABT533 MIN MAX -1.2 2.5 3 V SN74ABT533A MIN MAX -1.2 UNIT V VOH ICC Ci Co * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT533 VCC = 5 V, TA = 25C MIN tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE High or low High or low 3.3 2.1 1.5 MAX 3.3 2.1 1.5 ns ns ns MIN MAX UNIT timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ABT533A VCC = 5 V, TA = 25C MIN tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE High or low High or low 3.3 2.1 2.1 MAX 3.3 2.1 2.1 ns ns ns MIN MAX UNIT switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT533 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ D 1.9 Q Q Q Q 3.1 2.7 LE OE OE 3.5 1.6 2.4 2.8 2 TYP 4.2 4.9 4.9 5.4 3.7 4.2 5.1 4.1 MAX 5.4 6.3 6.2 6.8 4.8 6.2 6.2 6 1.9 3.1 2.7 3.5 1.6 2.4 2.8 2 6.7 6.9 7.6 7.5 5.8 6.9 7.2 6.9 ns ns ns ns MIN MAX UNIT 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT533A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ D 1.7 Q Q Q Q 2.6 2.7 LE OE OE 3.5 1.6 2.4 1.6 2 TYP 4.2 4.9 4.9 5.4 3.7 4.2 5.1 4.1 MAX 5.4 6.3 6.2 6.8 4.8 6.2 6.2 6 1.7 2.6 2.7 3.5 1.6 2.4 1.6 2 6.4 6.6 7.3 7.3 5.7 6.7 6.9 6.5 ns ns ns ns MIN MAX UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS186D - JANUARY 1991 - REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 500 S1 7V Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Timing Input 1.5 V 0V tsu Data Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control tPZL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING tPLZ 1.5 V tPHZ 3.5 V VOL + 0.3 V VOL 1.5 V 1.5 V 0V th 3V 1.5 V 0V 3V Input tPLH Output tPHL 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH Output 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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