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SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
* * * * * * *
description
The ABT2952 consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
B5 B4 B3 NC B2 B1 OEAB
5 6 7 8 9
4
3 2 1 28 27 26 25 24 23 22 21
10
20 11 19 12 13 14 15 16 17 18
A6 A5 A4 NC A3 A2 A1
NC - No internal connection
The SN74ABT2952 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT2952 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ABT2952 is characterized for operation from - 40C to 85C.
EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
CLKAB CLKENAB GND NC CLKENBA CLKBA OEBA
Copyright (c) 1992, Texas Instruments Incorporated
2-1
PRODUCT PREVIEW
State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions Noninverting Outputs Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C Package Options Include Plastic Small-Outline (SOIC) and Shrink Small-Outline (SSOP) Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
SN54ABT2952 . . . JT PACKAGE SN74ABT2952 . . . DB, DW, OR NT PACKAGE (TOP VIEW)
B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CLKENAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CLKENBA
SN54ABT2952 . . . FK PACKAGE (TOP VIEW)
B6 B7 B8 NC VCC A8 A7
SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
FUNCTION TABLE INPUTS CLKENAB H X L L X CLKAB X H or L X OEAB L L L L H A X X L H X OUTPUT B B0 B0 L H
Z A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA. Level of B before the indicated steady-state input conditions were established.
logic symbol
15 OEBA CLKENBA CLKBA 13 14 9 OEAB CLKENAB CLKAB A1 11 10 16 EN3 G1 1 C5 EN4 G2 2 C6 3 6D A2 A3 A4 A5 A6 A7 A8 17 18 19 20 21 22 23 1 1 5D 4 7 6 5 4 3 2 1 B2 B3 B4 B5 B6 B7 B8 8 B1
PRODUCT PREVIEW
2-2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, and NT packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
logic diagram (positive logic)
CLKENAB 11
CLKAB
10
9 OEAB
CLKENBA
13
CLKBA
14
OEBA
15 C1 A1 16 1D 8 B1
C1 1D
To Seven Other Channels Pin numbers shown are for the DB, DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-3
PRODUCT PREVIEW
SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
recommended operating conditions (see Note 2)
SN54ABT2952 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Outputs enabled - 55 0 4.5 2 0.8 VCC - 24 48 10 125 - 40 0 MAX 5.5 SN74ABT2952 MIN 4.5 2 0.8 VCC - 32 64 10 85 MAX 5.5 UNIT V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, , VI = VCC or GND VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 24 mA IOH = - 32 mA IOL = 48 mA IOL = 64 mA Control inputs A or B ports VO = 2.7 V VO = 0.5 V VI or VO 4.5 V Outputs high VO = 2.5 V Outputs high A or B orts ports Outputs low Outputs disabled - 50 -100 1 24 0.5 MIN 2.5 3 2 2 0.55 0.55 1 100 50 - 50 100 50 -180 250 35 250 1.5 3.5 7.5 - 50 50 -180 250 35 250 1.5 - 50 TA = 25C TYP MAX -1.2 2.5 3 2 2 0.55 0.55 1 100 50 - 50 1 100 50 - 50 100 50 -180 250 35 250 1.5 V A A A A A mA A mA A mA pF pF SN54ABT2952 MIN MAX -1.2 2.5 3 V SN74ABT2952 MIN MAX -1.2 UNIT V
PRODUCT PREVIEW
2-4
VIK
VOH
VOL II IOZH IOZL Ioff ICEX IO ICC
ICC# Ci Cio
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Control inputs A or B ports
All typical values are at VCC = 5 V. On products compliant to MIL-STD-883, Class B, this parameter does not apply. The parameters IOZH and IOZL include the input leakage current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V, TA = 25C MIN fclock tw Clock frequency Pulse duration A or B tsu Setup time before CLK CLKEN th Hold time after CLK A or B CLKEN CLK high CLK low High Low High Low 0 3 3.5 4 3 3.5 2.5 0 0 MAX 150 SN54ABT2952 MIN 0 3 3.5 4 3 3.5 2.5 0 0 MAX 150 SN74ABT2952 MIN 0 3 3.5 4 3 3.5 2.5 0 0 ns ns MAX 150 MHz ns UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 150 CLKAB or CLKBA OEBA or OEAB OEBA or OEAB B or A A or B A or B TYP MAX SN54ABT2952 MIN 150 MAX SN74ABT2952 MIN 150 MAX MHz ns ns ns UNIT
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-5
PRODUCT PREVIEW
SN54ABT2952, SN74ABT2952 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS202 - NOVEMBER 1990 - REVISED OCTOBER 1992
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT FOR OUTPUTS 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V Data Input tsu 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
Input (see Note B) tPLH Output
3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL
Output Control tPZL Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) tPZH
3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH
3.5 V VOL + 0.3 V VOL
Output
1.5 V
[0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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