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SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
D D D D D D D D D
Members of the Texas Instruments Widebus TM Family Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT162244 . . . WD PACKAGE SN74ABT162244 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
The 'ABT162244 are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low outputenable (OE) inputs.
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT162244 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT162244 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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1
SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
logic symbol
1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 1 2 1 48 25 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
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SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
logic diagram (positive logic)
1OE 1 3OE 2 25
1A1
47
1Y1
3A1
36
13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE
48
4OE 8
24
2A1
41
2Y1
4A1
30
19
4Y1
2A2
40
9
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
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SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT162244 MIN VCC VIH VIL VI IOH IOL t /v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 0 4.5 2 0.8 VCC -12 12 10 200 -40 85 0 MAX 5.5 SN74ABT162244 MIN 4.5 2 0.8 VCC -12 12 10 MAX 5.5 UNIT V V V V mA mA ns/V s/V C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
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POST OFFICE BOX 655303
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SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZPU IOZPD IOZH IOZL Ioff ICEX IO ICC VCC = 4 5 V 4.5 II = -18 mA IOH = -1 mA IOH = -1 mA IOH = -3 mA IOH = -12 mA IOL = 8 mA IOL = 12 mA 100 VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 2 V VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 2 V VCC = 0, VI or VO 4.5 V VCC = 5.5 V, Ouptputs high VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, , Other inputs at VCC or GND VO = 2.5 V Outputs high Outputs low Outputs disabled Outputs enabled Outputs disabled -25 -55 1 50 50 10 -10 100 50 -100 2 30 2 50 50 50 3 8 -25 50 -100 2 30 2 50 50 50 -25 1 50 50 10 -10 1 50 50 10 -10 100 50 -100 2 30 2 50 50 50 pF pF A mA MIN 3.35 3.85 3.1 2.6* 0.4 0.8 0.8 TA = 25C TYP MAX -1.2 3.35 3.85 3.1 SN54ABT162244 MIN MAX -1.2 3.35 3.85 3.1 2.6 0.65 0.8 V mV A A A A A A A mA V SN74ABT162244 MIN MAX -1.2 UNIT V
VOH
Data inputs ICC Control inputs Ci Co
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V
* On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. This parameter is characterized, but not production tested. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT162244 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN tPLH tPHL tPZH tPZL tPHZ tPLZ A Y Y Y 1 1 1 1 1 1 TYP 2.5 3.1 3.2 3.2 3.2 3.1 MAX 3.6 4.7 4.8 4.7 5.3 4.6 1 1 1 1 1 1 4.1 5.3 5.6 5.5 6.3 4.9 ns ns ns MIN MAX UNIT
OE OE
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT162244 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN tPLH tPHL tPZH tPZL tPHZ tPLZ A Y Y Y 1 1 1 1 1 1 TYP 2.5 3.1 3.2 3.2 3.2 3.1 MAX 3.2 4 4.2 4.1 4 3.9 1 1 1 1 1 1 3.9 4.8 5.4 5.1 4.6 4.5 ns ns ns MIN MAX UNIT
OE OE
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT162244, SN74ABT162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS238D - JUNE 1992 - REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 S1 7V Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
From Output Under Test CL = 50 pF (see Note A)
LOAD CIRCUIT tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION
3V Timing Input 1.5 V 0V tsu Data Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control tPZL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING tPLZ 1.5 V tPHZ 3.5 V VOL + 0.3 V VOL 1.5 V 1.5 V 0V th 3V 1.5 V 0V
3V Input tPLH Output tPHL 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH Output 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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