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| SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 * * * * * State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions Simultaneously Generates and Checks Parity Packaged in Plastic Small-Outline Package DW PACKAGE (TOP VIEW) description The SN74BCT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data buses in either direction. It has a current-sinking capability of 24 mA at the A bus and 64 mA at the B bus. The SN74BCT899 features independent latchenable (LEAB or LEBA) inputs, a select (SEL) input for ODD/EVEN parity, and separate error-signal (ERRA or ERRB) outputs for checking parity. The SN74BCT899 is characterized for operation from 0C to 70C. ODD/EVEN ERRA LEAB A1 A2 A3 A4 A5 A6 A7 A8 APAR OEBA GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC OEAB B1 B2 B3 B4 B5 B6 B7 B8 BPAR LEBA SEL ERRB PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1993, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-1 SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 FUNCTION TABLE INPUTS OEAB H H OEBA H L SEL X L LEAB X X LEBA X H OPERATION OR FUNCTION Buses A and B are in the high-impedance state. Generates parity from B1 - B8 based on ODD/EVEN. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B1 - B8 based on ODD/EVEN. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B-latch data based on ODD/EVEN. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB. BPAR /B1 - B8 APAR/A1 - A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR /B1 - B8 APAR/A1 - A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from A1 - A8 based on ODD/EVEN. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A1 - A8 based on ODD/EVEN. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A-latch data based on ODD/EVEN. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA. APAR /A1 - A8 BPAR/B1-B8 feed-through mode. Generated parity checked against APAR and output as ERRA. APAR /A1 - A8 BPAR/B1-B8 feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Output to A bus and B bus PARITY FUNCTION TABLE INPUTS OUTPUTS ODD/EVEN L L L L H H H OF INPUTS A1 - A8 = H 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 APAR L L H H L L H BPAR L H L H H L H ERRA H L L H L H H H L L H H H H H L L L L H L H H L X X H H L H H X L H L H H L L L L H H H L L H H X L H H X X X X X H 1, 3, 5, 7 H L L If LE = H, current A1 - A8 and APAR data is used. If LE = L, latched A1-A8 and APAR data is used. This is the value of BPAR if SEL = L. If SEL = H, BPAR = APAR. 2-2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 logic diagram (positive logic) ODD/EVEN SEL OEBA LEAB OEAB LEBA 9-Bit Transp. Latch A1 A2 A3 A4 A5 A6 A7 A8 APAR ERRA 9-Bit Buffer B1 B2 B3 B4 B5 B6 B7 B8 BPAR Parity Generator ERRB Parity Generator 9-Bit Buffer 9-Bit Transp. Latch absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-3 SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 recommended operating conditions (see Note 2) MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate A1 - A8 B1 - B8 A1 - A8 B1 - B8 Outputs enabled 0 0 4.5 2 0.8 VCC -3 -15 24 64 10 70 NOM 5 MAX 5.5 UNIT V V V V mA mA ns / V C TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low. 2-4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A1 - A8, APAR, ERRA, ERRB VOH B1 - B8, BPAR B8 TEST CONDITIONS VCC = 4.5 V, VCC = 4.75 V, VCC = 4 5 V 4.5 VCC = 4.75 V, VCC = 4.5 V II = -18 mA IOH = -1 mA IOH = -1 mA IOH = - 3 mA IOH = - 3 mA IOH = - 3 mA IOH = -12 mA IOH = -15 mA IOL = 20 mA IOL = 24 mA IOL = 48 mA IOL = 64 mA VI = 5.5 V VI = 2.7 V VI = 0.5 V VO = 0 - 60 -100 0.5 0.5 43 VCC = 5 5 V 5.5 V, Outputs open 22 6 6 0.5 0.5 VCC = 5 V, A ports B ports VCC = 5 V V, VI = 0.5 V VO = 0.5 V 05 6.5 10.5 12.5 MIN 2.7 2.5 2.4 2.7 2.4 2 TYP 3.4 3.4 3.3 3.4 3.4 3.1 0.35 0.42 0.5 0.55 100 20 -20 -150 - 225 2 2 69 34 10 10 2 2 pF pF mA A A A mA V MAX -1.2 UNIT V A1 - A8, APAR, ERRA ERRB A8 APAR ERRA, VOL B1 - B8, BPAR B8 II IIH IIL IOS A1 - A8, APAR, ERRA, ERRB B1 - B8, BPAR Outputs high Outputs low ICC Outputs disabled ERR outputs low disabled, Outputs disabled ERR outputs high disabled, Ci Cio i A to B B to A A to B B to A A to B B to A A to B B to A VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 V, VCC = 4 5 V 4.5 V All typical values are at VCC = 5 V, TA = 25C. For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25C MIN tw tsu th Pulse duration Setup time before LE Hold time after LE Data high or low Data high or low 5 4.5 1.5 MAX 5 4.5 1.5 ns ns ns MIN MAX UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-5 SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 - JUNE 1992 - REVISED NOVEMBER 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 3) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B A or B APAR or BPAR A, APAR, or , , B, BPAR ODD/EVEN ODD/EVEN SEL LEAB OR LEBA LEAB OR LEBA LEAB OR LEBA LEAB OR LEBA TO (OUTPUT) B or A BPAR or APAR BPAR or APAR VCC = 5 V, TA = 25C MIN 1.9 1.8 4.3 4.5 2.2 1.7 3.4 ERRA or ERRB ERRA or ERRB BPAR or APAR BPAR or APAR B or A BPAR or APAR (parity feed-through) BPAR or APAR (parity generated) ERRB or ERRA B or A B or A 3.6 4.6 4.1 4.5 4.4 1.4 1.6 2.6 3.3 3 3 5.2 5.1 5.3 5 1.8 2.1 2.9 2.1 TYP 6 5.2 11 10.7 5.2 4.7 10.6 10.5 8.8 8.4 9 8.5 4.6 4.4 7.6 6.5 6.7 6.1 10.2 8.9 10.3 9.2 5.6 10.5 6.4 5.5 MAX 7.6 6.8 13 12.7 6.7 6.3 12.6 12.5 10.5 10.2 10.7 10.7 6.2 5.9 9.3 8.2 8.3 7.7 12.1 10.7 12.3 11 7.2 12.2 8.1 7.1 1.9 1.8 4.3 4.5 2.2 1.7 3.4 3.6 4.6 4.1 4.5 4.4 1.4 1.6 2.6 3.3 3 3 5.2 5.1 5.3 5 1.8 2.1 2.9 2.1 9.1 8.1 16.1 15.3 8 7.6 15.7 15.3 12.8 12.8 13.1 13.3 7.7 7.1 10.9 9.3 9.9 8.7 14.8 12.5 14.9 12.9 9 13.9 9.8 8.1 ns ns ns ns ns ns ns ns ns ns ns ns ns MIN MAX UNIT OEAB or OEBA OEAB or OEBA NOTE 3: Load circuits and voltage waveforms are shown in Section 1. 2-6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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