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| SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 D D D D 4- Switch Connection Between Two Ports Isolation Under Power-Off Conditions Break-Before-Make Feature Packaged in Plastic Thin Shrink Small-Outline Package For tape and reel order entry: The DGGR package is abbreviated to GR. DGG PACKAGE (TOP VIEW) NOTE: description The SN74CBTLV16235 is an 18-bit 1-of-2 FET multiplexer/demultiplexer used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single path. This device can be used for memory interleaving, where two different banks of memory need to be addressed simultaneously. The device is organized as a dual 9-bit 1-of-2 multiplexer/demultiplexer with separate control inputs. It can be used as two 9-bit multiplexers/demultiplexers or as one 18-bit multiplexer/demultiplexer. Two select (S0 and S1) inputs control the data flow. When the test (T0 and T1) inputs are asserted, port A is connected to both ports B1 and B2. The control inputs can be driven with a low-voltage TTL or an SSTL_3 driver. The SN74CBTLV16235 is specified by the break-before-make design to have no through current when switching directions. The SN74CBTLV16235 is characterized for operation from -40C to 85C. 1A 2B1 2B2 3A 4B1 4B2 5A 6B1 6B2 7A 8B1 8B2 GND VCC 9A 10B1 10B2 11A 12B1 12B2 13A 14B1 14B2 15A 16B1 16B2 17A 18B1 18B2 GND T0 T1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1B1 1B2 2A 3B1 3B2 4A 5B1 5B2 6A 7B1 7B2 8A GND VCC 9B1 9B2 10A 11B1 11B2 12A 13B1 13B2 14A 15B1 15B2 16A 17B1 17B2 18A GND S0 S1 FUNCTION TABLE (each 9-bit multiplexer/demultiplexer) INPUTS T L L H S L H X FUNCTION A port = B1 port A port = B2 port A port = B1 port = B2 port Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 PRODUCT PREVIEW SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 logic diagram (positive logic) 1A 1 64 SW 63 1B2 1B1 SW 9A 15 SW 50 9B1 SW 49 9B2 34 PRODUCT PREVIEW S0 31 T0 10A 48 16 SW 17 10B2 10B1 SW 18A 36 SW 28 18B1 SW 29 18B2 33 S1 32 T1 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN VCC VIH VIL Supply voltage High-level High level control input voltage Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0.7 0.8 MAX 3.6 UNIT V V V TA Operating free-air temperature -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 PRODUCT PREVIEW Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II Ioff ICC ICC Ci Ci (OFF) io(OFF) Control input Control input A port B port VCC = 3 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, VCC = 3.6 V, VI = 3 V or 0 VO = 3 V or 0 VCC = 2 3 V 2.3 V, TYP at VCC = 2.5 V ron VCC = 3 V VI = 0 VI = 1.7 V, VI = 0 II = 64 mA II = 24 mA II = 15 mA II = 64 mA II = 24 mA TEST CONDITIONS II = -18 mA VI = VCC or GND VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND MIN TYP MAX -1.2 5 10 10 300 UNIT V A A A A pF pF PRODUCT PREVIEW VI = 2.4 V, II = 15 mA All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) PARAMETER tpd ten tdis ten tdis FROM (INPUT) A or B S S T TO (OUTPUT) B or A A or B A or B A or B VCC = 2.5 V 0.2 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX ns ns ns ns UNIT T A or B ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL LOAD CIRCUIT VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PRODUCT PREVIEW tPHZ SN74CBTLV16235 LOW-VOLTAGE 18-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS060D - MARCH 1998 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V 2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT Output Control tPZL VCC Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B) VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Input VCC/2 tPLH VCC/2 0V tPHL PRODUCT PREVIEW Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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