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DESIGN GOAL DESIGN GOAL
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A - APRIL 1999 - REVISED MAY 1999
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Member of the Texas Instruments WidebusTM Family Supports SSTL_2 Signal Data Inputs Supports LVTTL Switching Levels on the RESET Pin Flow-Through Architecture Optimizes PCB Layout
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Differential CLK Signal Advanced ULTTL Output Circuitry Eliminates Switching Noise in Unterminated Line Packaged in Plastic Fine-Pitch Ball-Grid-Array Package
description
This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation and SSTL_2 input and unterminated LVCMOS-output applications. Data flow from A to Y is controlled by differential clock (CLK, CLK) inputs and the LVTTL reset (RESET) input. Data are triggered on the positive edge of the positive clock (CLK). The negative clock (CLK) is used to maintain noise margins. When RESET is low, all registers are reset, and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
GKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T A1 A3 A5 A7 A9 A11 A13 A15 CLK CLK A16 A18 A20 A22 A24 A26 2 VCC A2 A4 A6 A8 A10 A12 A14 NC RESET A17 A19 A21 A23 A25 VCC 3 GND VREF NC GND VCC GND VCC GND GND VCC GND VCC GND NC NC GND 4 VDDQ GND GND VDDQ GND VDDQ VDDQ GND GND VDDQ VDDQ GND VDDQ GND GND VDDQ 5 Y1 Y3 Y5 Y7 Y9 Y10 Y12 GND GND Y15 Y17 Y18 Y20 Y22 Y24 Y26 6 Y2 Y4 Y6 Y8 VDDQ GND Y11 Y13 Y14 Y16 GND VDDQ Y19 Y21 Y23 Y25
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1999, Texas Instruments Incorporated
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PRODUCT PREVIEW
The SN74SSTL32867 is characterized for operation from 0C to 70C.
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A - APRIL 1999 - REVISED MAY 1999
DESIGN GOAL
FUNCTION TABLE INPUTS RESET H H H L CLK L or H X CLK L or H X A H L X X OUTPUT Y H L Y0 L
logic diagram (positive logic)
RESET CLK CLK VREF K2 J1 K1 B3 A1 1D C1 R A5 Y1
PRODUCT PREVIEW
A1
To 25 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, qJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. Current flows only when the output is in the high state and VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.
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DESIGN GOAL
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A - APRIL 1999 - REVISED MAY 1999
recommended operating conditions (see Note 4)
MIN VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VI(PP) IOH IOL Supply voltage Output supply voltage Reference voltage (VREF = VDDQ/2) Termination voltage Input voltage AC high-level input voltage AC low-level input voltage DC high-level input voltage DC low-level input voltage High-level input voltage Low-level input voltage Common-mode input voltage range Peak-to-peak input voltage High-level output current Low-level output current Data input Data input Data input Data input RESET RESET CLK, CLK CLK, CLK 0.97 360 -8 8 1.7 0.7 1.53 VREF+180mV VREF-180mV VDDQ 2.3 1.15 VREF-40mV 0 VREF+350mV VREF-350mV 1.25 VREF NOM MAX 2.7 2.7 1.35 VREF+40mV VCC UNIT V V V V V V V V V V V V mV mA
TA Operating free-air temperature 0 70 _C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH II = -18 mA IOH = -100 A IOH = -4 mA IOH = -8 mA IOL = 100 A IOL = 4 mA Data inputs RESET input II CLK, CLK CLK VREF ICC Ci Co RESET input Data inputs Outputs IOL = 8 mA VI = 1.7 V or 0.8V VI = 2.7 V or 0 VI = 1.7 V or 0.8V VI = 2.7 V or 0 VREF = 1 15 V or 1 35 V 1.15 1.35 VI = 1.7 V or 0.8 V VI = 2.7 V or 0 VI = 1 7 V or 0 8 V 1.7 0.8 VO = 1 7 V or 0 8 V 1.7 0.8 IO = 0 VREF = 1.15 V or 1.35 V TEST CONDITIONS VCC 2.3 V 2.3 V to 2.7 V 2.3 23V 2.3 V to 2.7 V 2.3 23V 2.7 27V 2.7 27V 27V 2.7 2.7 27V 2 5 V 2.5 2.5 2 5 V MIN TYP MAX -1.2 VCC-0.2 2 1.7 0.2 0.3 0.6 5 5 5 5 5 mA pF pF A V UNIT V V
VOL
VREF = 1 15 V or 1 35 V 1.15 1.35
All typical values are at VCC = 2.5 V, TA = 25C.
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PRODUCT PREVIEW
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A - APRIL 1999 - REVISED MAY 1999
DESIGN GOAL
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V 0.2 V MIN TYP MAX fclock tw tsu th Clock frequency Pulse duration, CLK, CLK high or low Setup time Hold time, data after CLK, CLK Data before CLK, CLK RESET high before CLK, CLK 200 1.6 1.1 1.1 0.5 0.8 0.5 0.5 0 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VREF = VDDQ/2 and CL = 10 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd FROM (INPUT) TO (OUTPUT) VCC = 2.5 V 0.2 V MIN TYP MAX 200 CLK and CLK RESET Y Y 1.9 2.2 2.8 3.2 UNIT MHz ns ns
PRODUCT PREVIEW
tPHL
switching characteristics over recommended operating free-air temperature range, VREF = VDDQ/2 and CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd tPHL FROM (INPUT) TO (OUTPUT) VCC = 2.5 V 0.2 V MIN TYP MAX 200 CLK and CLK RESET Y Y 2.6 2.9 3.8 4.4 UNIT MHz ns ns
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DESIGN GOAL
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A - APRIL 1999 - REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
From Output Under Test CL = 10 pF or 30 pF (see Note A) Test Point
LOAD CIRCUIT tw Input tPLH VREF VREF tPHL VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS Timing Input tsu Data Input VREF VREF VIH VIL VIH VIL Input VREF VREF VIL VOLTAGE WAVEFORMS PULSE DURATION VIH
th VIH VREF VIL
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VREF = VDDQ/2 VIH = VREF+350mV (ac voltage levels) for SSTL inputs. VIH = VCC for LVTTL inputs. VIL = VREF-350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVTTL inputs. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 1.25 ns/V, tf 1.25 ns/V. C. The outputs are measured one at a time with one transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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PRODUCT PREVIEW
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Copyright (c) 1999, Texas Instruments Incorporated

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