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| SN74LVCZ245A OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES275B - JUNE 1999 - REVISED JANUARY 2000 D D D D D D D EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Shrink Small-Outline (DB), Plastic Thin Very Small-Outline (DGV), Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages DB, DGV, DW, OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 description This octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVCZ245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN74LVCZ245A is characterized for operation from -40C to 85C. FUNCTION TABLE INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74LVCZ245A OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES275B - JUNE 1999 - REVISED JANUARY 2000 logic symbol OE DIR 19 1 G3 3 EN1 [BA] 3 EN2 [AB] 1 2 A2 A3 A4 A5 A6 A7 A8 3 4 5 6 7 8 9 17 16 15 14 13 12 11 B2 B3 B4 B5 B6 B7 B8 18 B1 A1 2 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) DIR 1 19 OE A1 2 18 B1 To Seven Other Channels 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVCZ245A OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES275B - JUNE 1999 - REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN VCC VIH VIL VI VO IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature -40 High or low state 3-state VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 0 5.5 VCC 5.5 -12 -24 12 24 6 150 85 MAX 3.6 UNIT V V V V V mA mA ns/V s/V C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74LVCZ245A OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES275B - JUNE 1999 - REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = -100 A VOH IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL II Ioff IOZ IOZPU IOZPD ICC ICC Ci Cio Control inputs IOL = 12 mA IOL = 24 mA VI = 0 to 5.5 V VI or VO = 5.5 V VO = 0 to 5.5 V VO = 0.5 V to 2.5 V, VO = 0.5 V to 2.5 V, VI = VCC or GND 3.6 V VI 5.5 V Control inputs A or B ports VI = VCC or GND VO = VCC or GND OE = don't care OE = don't care IO = 0 TEST CONDITIONS VCC 2.7 V to 3.6 V 2.7 V 3V 3V 2.7 V to 3.6 V 2.7 V 3V 3.6 V 0 3.6 V 0 to 1.5 V 1.5 V to 0 3.6 36V 2.7 V to 3.6 V 3.3 V 3.3 V 4 6 MIN VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.55 5 5 5 5 5 100 100 100 A A A A A A A pF pF V TYP MAX UNIT V One input at VCC - 0.6 V, Other inputs at VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 2.7 V MIN MAX 7.3 9.5 8.5 VCC = 3.3 V 0.3 V MIN 1.5 1.5 1.7 MAX 6.3 8.5 7.5 ns ns ns UNIT operating characteristics, TA = 25C PARAMETER Cpd Outputs enabled Power dissipation capacitance per transceiver Outputs disabled f = 10 MHz TEST CONDITIONS VCC = 3.3 V TYP 42 3 pF UNIT 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVCZ245A OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES275B - JUNE 1999 - REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC VCC/2 0V tsu th VCC VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 0V Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input Output Control (low-level enabling) tPZL VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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